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[hal_vepu_v2]: Fix vepu hor_stride setup

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vepu h264 input stride must be aligned to 8 for vepu limitation.
If it is not 8 aligned some buffer conversion preprocess should be done
before the buffer is sent encoder.

1. The hor_stride in vepu hardware is in pixel unit not byte unit.
2. The hor_stride in vepu must be 8 pixels aligned.
3. The YUV420P should be 16 pixels aligned for chroma.
4. Fix log print when hor_stride != width 8align

Change-Id: If30136a4673399c3be40a41a055e832db4c321d5
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>
This commit is contained in:
sayon.chen
2020-08-26 15:17:24 +08:00
committed by Herman Chen
parent a4cbfd54fa
commit c0fef41211
9 changed files with 59 additions and 30 deletions
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14
utils/mpi_enc_utils.c
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@@ -33,8 +33,11 @@ RK_S32 mpi_enc_width_default_stride(RK_S32 width, MppFrameFormat fmt)
RK_S32 stride = 0;
switch (fmt & MPP_FRAME_FMT_MASK) {
case MPP_FMT_YUV420SP :
case MPP_FMT_YUV420SP : {
stride = MPP_ALIGN(width, 8);
} break;
case MPP_FMT_YUV420P : {
/* NOTE: 420P need to align to 16 so chroma can align to 8 */
stride = MPP_ALIGN(width, 16);
} break;
case MPP_FMT_YUV422P:
@@ -49,17 +52,20 @@ RK_S32 mpi_enc_width_default_stride(RK_S32 width, MppFrameFormat fmt)
case MPP_FMT_YUV422_YVYU :
case MPP_FMT_YUV422_UYVY :
case MPP_FMT_YUV422_VYUY : {
stride = MPP_ALIGN(width * 2, 16);
/* NOTE: for vepu limitation */
stride = MPP_ALIGN(width, 8) * 2;
} break;
case MPP_FMT_RGB888 :
case MPP_FMT_BGR888 : {
stride = width * 3;
/* NOTE: for vepu limitation */
stride = MPP_ALIGN(width, 8) * 3;
} break;
case MPP_FMT_ARGB8888 :
case MPP_FMT_ABGR8888:
case MPP_FMT_BGRA8888:
case MPP_FMT_RGBA8888: {
stride = width * 4;
/* NOTE: for vepu limitation */
stride = MPP_ALIGN(width, 8) * 4;
} break;
default : {
mpp_err_f("do not support type %d\n", fmt);