diff --git a/mpp/hal/common/h264/hal_h264e_com.h b/mpp/hal/common/h264/hal_h264e_com.h
index a710fefc..55df6978 100644
--- a/mpp/hal/common/h264/hal_h264e_com.h
+++ b/mpp/hal/common/h264/hal_h264e_com.h
@@ -163,7 +163,7 @@ extern RK_U32 h264e_hal_log_mode;
 #define H264E_MB_RC_WIDE_RANGE    5
 #define H264E_MB_RC_M_NUM         6
 
-typedef enum H264eRkvCsp_t {
+typedef enum H264eRkvCsp_e {
     H264E_RKV_CSP_BGRA8888,     // 0
     H264E_RKV_CSP_BGR888,       // 1
     H264E_RKV_CSP_BGR565,       // 2
@@ -178,7 +178,7 @@ typedef enum H264eRkvCsp_t {
 } H264eRkvCsp;
 
 /* transplant from vpu_api.h:EncInputPictureType */
-typedef enum H264VpuCsp_t {
+typedef enum H264VpuCsp_e {
     H264E_VPU_CSP_YUV420P   = 0,    // YYYY... UUUU... VVVV
     H264E_VPU_CSP_YUV420SP  = 1,    // YYYY... UVUVUV...
     H264E_VPU_CSP_YUYV422   = 2,    // YUYVYUYV...
@@ -197,34 +197,40 @@ typedef enum H264VpuCsp_t {
     H264E_VPU_CSP_BUTT,
 } H264eVpuCsp;
 
-typedef enum H264eChromaFmt_t {
+typedef enum H264eChromaFmt_e {
     H264E_CHROMA_400 = 0,
     H264E_CHROMA_420 = 1,
     H264E_CHROMA_422 = 2,
     H264E_CHROMA_444 = 3,
 } H264eChromaFmt;
 
-typedef enum H264eCqm4_t {
+typedef enum H264eCqm4_e {
     H264E_CQM_4IY = 0,
     H264E_CQM_4PY = 1,
     H264E_CQM_4IC = 2,
     H264E_CQM_4PC = 3
 } H264eCqm4;
 
-typedef enum H264eCqm8_t {
+typedef enum H264eCqm8_e {
     H264E_CQM_8IY = 0,
     H264E_CQM_8PY = 1,
     H264E_CQM_8IC = 2,
     H264E_CQM_8PC = 3,
 } H264eCqm8;
 
-typedef enum H264eSliceType_t {
+typedef enum H264eSliceType_e {
     H264E_HAL_SLICE_TYPE_P  = 0,
     H264E_HAL_SLICE_TYPE_B  = 1,
     H264E_HAL_SLICE_TYPE_I  = 2,
 } H264eSliceType;
 
-typedef struct H264eSps_t {
+typedef enum H264eOsdPltType_e {
+    H264E_OSD_PLT_TYPE_NONE     = -1,
+    H264E_OSD_PLT_TYPE_USERDEF  = 0,
+    H264E_OSD_PLT_TYPE_DEFAULT  = 1,
+} H264eOsdPltType;
+
+typedef struct H264eSps_e {
     RK_S32 i_id;
 
     RK_S32 i_profile_idc;
@@ -421,7 +427,7 @@ typedef struct H264eHalContext_t {
     void                            *param_buf;
     MppPacket                       packeted_param;
 
-    RK_U32                          osd_plt_type; //0:user define, 1:default
+    H264eOsdPltType                 osd_plt_type; //-1:invalid, 0:user define, 1:default
     MppEncOSDData                   osd_data;
     MppEncSeiMode                   sei_mode;
 
diff --git a/mpp/hal/rkenc/h264e/hal_h264e_rkv.c b/mpp/hal/rkenc/h264e/hal_h264e_rkv.c
index cce97a33..8a320a52 100644
--- a/mpp/hal/rkenc/h264e/hal_h264e_rkv.c
+++ b/mpp/hal/rkenc/h264e/hal_h264e_rkv.c
@@ -2013,7 +2013,7 @@ static MPP_RET h264e_rkv_set_osd_plt(H264eHalContext *ctx, void *param)
     MppEncOSDPlt *plt = (MppEncOSDPlt *)param;
     h264e_hal_enter();
     if (plt->buf) {
-        ctx->osd_plt_type = 0;
+        ctx->osd_plt_type = H264E_OSD_PLT_TYPE_USERDEF;
 #ifdef RKPLATFORM
         if (MPP_OK != mpp_device_send_reg_with_id(ctx->vpu_fd,
                                                   H264E_IOC_SET_OSD_PLT, param,
@@ -2023,7 +2023,7 @@ static MPP_RET h264e_rkv_set_osd_plt(H264eHalContext *ctx, void *param)
         }
 #endif
     } else {
-        ctx->osd_plt_type = 1;
+        ctx->osd_plt_type = H264E_OSD_PLT_TYPE_DEFAULT;
     }
 
     h264e_hal_leave();
@@ -2037,6 +2037,9 @@ static MPP_RET h264e_rkv_set_osd_data(H264eHalContext *ctx, void *param)
     RK_U32 num = src->num_region;
 
     h264e_hal_enter();
+    if (ctx->osd_plt_type == H264E_OSD_PLT_TYPE_NONE)
+        mpp_err("warning: plt type is invalid\n");
+
     if (num > 8) {
         h264e_hal_err("number of region %d exceed maxinum 8");
         return MPP_NOK;
@@ -2114,6 +2117,7 @@ MPP_RET hal_h264e_rkv_init(void *hal, MppHalCfg *cfg)
     ctx->frame_cnt_gen_ready = 0;
     ctx->frame_cnt_send_ready = 0;
     ctx->num_frames_to_send = 1;
+    ctx->osd_plt_type = H264E_OSD_PLT_TYPE_NONE;
 
     /* support multi-refs */
     dpb_ctx = (H264eRkvDpbCtx *)ctx->dpb_ctx;
@@ -2395,7 +2399,9 @@ h264e_rkv_set_osd_regs(H264eHalContext *ctx, H264eRkvRegSet *regs)
             MppEncOSDRegion *region = osd_data->region;
 
             regs->swreg65.osd_clk_sel    = 1;
-            regs->swreg65.osd_plt_type   = ctx->osd_plt_type;
+            regs->swreg65.osd_plt_type   = ctx->osd_plt_type == H264E_OSD_PLT_TYPE_NONE ?
+                                           H264E_OSD_PLT_TYPE_DEFAULT :
+                                           ctx->osd_plt_type;
 
             for (k = 0; k < num; k++) {
                 regs->swreg65.osd_en |= region[k].enable << k;