From b3fd37aa0806106af7a00dd100184f6003e8db57 Mon Sep 17 00:00:00 2001 From: Lin Kesheng Date: Wed, 18 Jan 2017 09:53:30 +0800 Subject: [PATCH] [hal_h264e]: always set pps.pic_init_qp to 26 Pps.pic_init_qp is different from codec_cfg.qp_init, and is not included in user configuration, thus we fix pps.pic_init_qp to 26. Change-Id: I408528891f91cd394aa55fe3b8b0e51bdb0e051f Signed-off-by: Lin Kesheng --- mpp/common/h264e_syntax.h | 1 - mpp/hal/common/h264/hal_h264e_com.c | 6 ++--- mpp/hal/common/h264/test/h264e_hal_test.c | 7 ------ mpp/hal/rkenc/h264e/hal_h264e_rkv.c | 29 +++++++++++------------ mpp/hal/vpu/h264e/hal_h264e_vpu.c | 10 ++++---- 5 files changed, 21 insertions(+), 32 deletions(-) diff --git a/mpp/common/h264e_syntax.h b/mpp/common/h264e_syntax.h index de99fa74..f419c39d 100644 --- a/mpp/common/h264e_syntax.h +++ b/mpp/common/h264e_syntax.h @@ -66,7 +66,6 @@ typedef struct H264eHwCfg_t { RK_S32 enable_cabac; RK_S32 cabac_init_idc; RK_S32 constrained_intra_prediction; - RK_S32 pic_init_qp; RK_S32 transform8x8_mode; RK_S32 pps_id; diff --git a/mpp/hal/common/h264/hal_h264e_com.c b/mpp/hal/common/h264/hal_h264e_com.c index da0e3b65..784f9448 100644 --- a/mpp/hal/common/h264/hal_h264e_com.c +++ b/mpp/hal/common/h264/hal_h264e_com.c @@ -686,10 +686,8 @@ MPP_RET hal_h264e_set_pps(h264e_hal_context *ctx, h264e_hal_pps *pps, h264e_hal_ pps->b_weighted_pred = analyse_weighted_pred > 0; pps->i_weighted_bipred_idc = analyse_b_weighted_bipred ? 2 : 0; - pps->i_pic_init_qp = cfg->qp_init; - if (pps->i_pic_init_qp < 0 || pps->i_pic_init_qp > 51) { - pps->i_pic_init_qp = 26; - } + /* pps.pic_init_qp is not included in user interface, just fix it */ + pps->i_pic_init_qp = 26; pps->i_pic_init_qs = pps->i_pic_init_qp; // only for SP/SI slices pps->b_transform_8x8_mode = cfg->transform8x8_mode; diff --git a/mpp/hal/common/h264/test/h264e_hal_test.c b/mpp/hal/common/h264/test/h264e_hal_test.c index b6ada974..a3889f38 100644 --- a/mpp/hal/common/h264/test/h264e_hal_test.c +++ b/mpp/hal/common/h264/test/h264e_hal_test.c @@ -424,11 +424,6 @@ static MPP_RET get_vpu_syntax_in(H264eHwCfg *syn, MppBuffer hw_in_buf, MppBuffer fgets(temp, 512, fp_golden_syntax_in); syn->frame_type = data; - - fscanf(fp_golden_syntax_in, "%d", &data); - fgets(temp, 512, fp_golden_syntax_in); - syn->pic_init_qp = data; - fscanf(fp_golden_syntax_in, "%d", &data); fgets(temp, 512, fp_golden_syntax_in); syn->slice_alpha_offset = data; @@ -618,7 +613,6 @@ static MPP_RET get_rkv_syntax_in( H264eHwCfg *syn, MppBuffer *hw_in_buf, MppBuff syn->input_format = h264e_rkv_revert_csp(csp_info); syn->enable_cabac = 1; - syn->pic_init_qp = 26; syn->chroma_qp_index_offset = 0; syn->second_chroma_qp_index_offset = 0; @@ -810,7 +804,6 @@ static void h264e_hal_set_extra_info_cfg(h264e_control_extra_info_cfg *info, H26 { info->chroma_qp_index_offset = syn->chroma_qp_index_offset; info->enable_cabac = syn->enable_cabac; - info->pic_init_qp = syn->pic_init_qp; info->pic_luma_height = syn->height; info->pic_luma_width = syn->width; info->transform8x8_mode = syn->transform8x8_mode; diff --git a/mpp/hal/rkenc/h264e/hal_h264e_rkv.c b/mpp/hal/rkenc/h264e/hal_h264e_rkv.c index eaba0ab7..703610bb 100644 --- a/mpp/hal/rkenc/h264e/hal_h264e_rkv.c +++ b/mpp/hal/rkenc/h264e/hal_h264e_rkv.c @@ -308,7 +308,6 @@ static void hal_h264e_rkv_dump_mpp_syntax_in(H264eHwCfg *syn, h264e_hal_context fprintf(fp, "%-16d %s\n", syn->input_format, "swreg14.src_cfmt"); fprintf(fp, "%-16d %s\n", syn->enable_cabac, "swreg59.etpy_mode"); - fprintf(fp, "%-16d %s\n", syn->pic_init_qp, "swreg59.pic_init_qp"); fprintf(fp, "%-16d %s\n", syn->chroma_qp_index_offset, "swreg59.cb_ofst"); fprintf(fp, "%-16d %s\n", syn->second_chroma_qp_index_offset, "swreg59.cr_ofst"); @@ -2295,7 +2294,6 @@ MPP_RET hal_h264e_rkv_set_ioctl_extra_info(h264e_rkv_ioctl_extra_info *extra_inf MPP_RET hal_h264e_rkv_set_rc_regs(h264e_hal_context *ctx, h264e_rkv_reg_set *regs, H264eHwCfg *syn, RcSyntax *rc_syn, h264e_hal_rkv_coveragetest_cfg *test) { - regs->swreg59.pic_init_qp = syn->pic_init_qp - H264_QP_BD_OFFSET; if (test && test->mbrc) { RK_U32 num_mbs_oneframe = (syn->width + 15) / 16 * ((syn->height + 15) / 16); RK_U32 frame_target_bitrate = (syn->width * syn->height / 1920 / 1080) * 10000000 / 8; //Bytes @@ -2727,7 +2725,6 @@ static MPP_RET hal_h264e_rkv_update_hw_cfg(h264e_hal_context *ctx, HalEncTask *t hw_cfg->enable_cabac = codec->entropy_coding_mode; hw_cfg->cabac_init_idc = codec->cabac_init_idc; hw_cfg->transform8x8_mode = codec->transform8x8_mode; - hw_cfg->pic_init_qp = codec->qp_init; hw_cfg->chroma_qp_index_offset = codec->chroma_cb_qp_offset; hw_cfg->second_chroma_qp_index_offset = codec->chroma_cr_qp_offset; hw_cfg->filter_disable = codec->deblock_disable; @@ -2735,9 +2732,9 @@ static MPP_RET hal_h264e_rkv_update_hw_cfg(h264e_hal_context *ctx, HalEncTask *t hw_cfg->slice_beta_offset = codec->deblock_offset_beta; hw_cfg->inter4x4_disabled = (codec->profile >= 31) ? (1) : (0); hw_cfg->constrained_intra_prediction = codec->constrained_intra_pred_mode; + hw_cfg->qp = codec->qp_init; - hw_cfg->qp_prev = hw_cfg->pic_init_qp; - hw_cfg->qp = hw_cfg->pic_init_qp; + hw_cfg->qp_prev = hw_cfg->qp; codec->change = 0; } @@ -2745,10 +2742,11 @@ static MPP_RET hal_h264e_rkv_update_hw_cfg(h264e_hal_context *ctx, HalEncTask *t /* init qp calculate, if outside doesn't set init qp. * mpp will use bpp to estimates one. */ - if (hw_cfg->pic_init_qp <= 0) { + if (hw_cfg->qp <= 0) { RK_S32 qp_tbl[2][9] = { {27, 44, 72, 119, 192, 314, 453, 653, 0x7FFFFFFF}, - {49, 45, 41, 37, 33, 29, 25, 21, 17}}; + {49, 45, 41, 37, 33, 29, 25, 21, 17} + }; RK_S32 pels = ctx->cfg->prep.width * ctx->cfg->prep.height; RK_S32 bits_per_pic = axb_div_c(rc->bps_target, rc->fps_out_denorm, @@ -2757,7 +2755,7 @@ static MPP_RET hal_h264e_rkv_update_hw_cfg(h264e_hal_context *ctx, HalEncTask *t if (pels) { RK_S32 upscale = 8000; if (bits_per_pic > 1000000) - hw_cfg->pic_init_qp = codec->qp_min; + hw_cfg->qp = codec->qp_min; else { RK_S32 j = -1; @@ -2770,8 +2768,8 @@ static MPP_RET hal_h264e_rkv_update_hw_cfg(h264e_hal_context *ctx, HalEncTask *t while (qp_tbl[0][++j] < bits_per_pic); - hw_cfg->pic_init_qp = qp_tbl[1][j]; - hw_cfg->qp_prev = hw_cfg->pic_init_qp; + hw_cfg->qp = qp_tbl[1][j]; + hw_cfg->qp_prev = hw_cfg->qp; } } } @@ -3138,11 +3136,11 @@ MPP_RET hal_h264e_rkv_gen_regs(void *hal, HalTaskInfo *task) hal_h264e_rkv_set_rc_regs(ctx, regs, syn, (RcSyntax *)enc_task->syntax.data, test_cfg); - regs->swreg56.rect_size = (sps->i_profile_idc == H264_PROFILE_BASELINE && sps->i_level_idc <= 30); - regs->swreg56.inter_4x4 = 1; - regs->swreg56.arb_sel = 0; //syn->swreg56.arb_sel; - regs->swreg56.vlc_lmt = (sps->i_profile_idc < H264_PROFILE_HIGH && !syn->enable_cabac); - regs->swreg56.rdo_mark = 0; //syn->swreg56.rdo_mark; + regs->swreg56.rect_size = (sps->i_profile_idc == H264_PROFILE_BASELINE && sps->i_level_idc <= 30); + regs->swreg56.inter_4x4 = 1; + regs->swreg56.arb_sel = 0; //syn->swreg56.arb_sel; + regs->swreg56.vlc_lmt = (sps->i_profile_idc < H264_PROFILE_HIGH && !syn->enable_cabac); + regs->swreg56.rdo_mark = 0; //syn->swreg56.rdo_mark; /*if (syn->transform8x8_mode == 0 && (syn->swreg56.rdo_mark & 0xb5) == 0xb5) //NOTE: bug may exist here { h264e_hal_log_err("RdoMark and trans8x8 conflict!"); @@ -3186,6 +3184,7 @@ MPP_RET hal_h264e_rkv_gen_regs(void *hal, HalTaskInfo *task) regs->swreg59.csip_flg = par->constrained_intra; //syn->swreg59.csip_flg; regs->swreg59.num_ref0_idx = pps->i_num_ref_idx_l0_default_active - 1; //syn->swreg59.num_ref0_idx; regs->swreg59.num_ref1_idx = pps->i_num_ref_idx_l1_default_active - 1; //syn->swreg59.num_ref1_idx; + regs->swreg59.pic_init_qp = pps->i_pic_init_qp - H264_QP_BD_OFFSET; regs->swreg59.cb_ofst = pps->i_chroma_qp_index_offset; //syn->chroma_qp_index_offset; regs->swreg59.cr_ofst = pps->i_second_chroma_qp_index_offset; //syn->second_chroma_qp_index_offset; regs->swreg59.wght_pred = 0x0; diff --git a/mpp/hal/vpu/h264e/hal_h264e_vpu.c b/mpp/hal/vpu/h264e/hal_h264e_vpu.c index a6c61a5e..2d025288 100644 --- a/mpp/hal/vpu/h264e/hal_h264e_vpu.c +++ b/mpp/hal/vpu/h264e/hal_h264e_vpu.c @@ -121,7 +121,6 @@ static void hal_h264e_vpu_dump_mpp_syntax_in(H264eHwCfg *syn, h264e_hal_context RK_S32 k = 0; fprintf(fp, "#FRAME %d:\n", ctx->frame_cnt); fprintf(fp, "%-16d %s\n", syn->frame_type, "frame_coding_type"); - fprintf(fp, "%-16d %s\n", syn->pic_init_qp, "pic_init_qp"); fprintf(fp, "%-16d %s\n", syn->slice_alpha_offset, "slice_alpha_offset"); fprintf(fp, "%-16d %s\n", syn->slice_beta_offset, "slice_beta_offset"); fprintf(fp, "%-16d %s\n", syn->chroma_qp_index_offset, "chroma_qp_index_offset"); @@ -1037,7 +1036,6 @@ static MPP_RET hal_h264e_vpu_update_hw_cfg(h264e_hal_context *ctx, HalEncTask *t hw_cfg->enable_cabac = codec->entropy_coding_mode; hw_cfg->cabac_init_idc = codec->cabac_init_idc; hw_cfg->transform8x8_mode = codec->transform8x8_mode; - hw_cfg->pic_init_qp = codec->qp_init; hw_cfg->chroma_qp_index_offset = codec->chroma_cb_qp_offset; hw_cfg->second_chroma_qp_index_offset = codec->chroma_cr_qp_offset; hw_cfg->filter_disable = codec->deblock_disable; @@ -1045,9 +1043,9 @@ static MPP_RET hal_h264e_vpu_update_hw_cfg(h264e_hal_context *ctx, HalEncTask *t hw_cfg->slice_beta_offset = codec->deblock_offset_beta; hw_cfg->inter4x4_disabled = (codec->profile >= 31) ? (1) : (0); hw_cfg->constrained_intra_prediction = codec->constrained_intra_pred_mode; + hw_cfg->qp = codec->qp_init; - hw_cfg->qp_prev = hw_cfg->pic_init_qp; - hw_cfg->qp = hw_cfg->pic_init_qp; + hw_cfg->qp_prev = hw_cfg->qp; codec->change = 0; } @@ -1140,6 +1138,8 @@ MPP_RET hal_h264e_vpu_gen_regs(void *hal, HalTaskInfo *task) { MPP_RET ret = MPP_OK; h264e_hal_context *ctx = (h264e_hal_context *)hal; + h264e_hal_vpu_extra_info *extra_info = (h264e_hal_vpu_extra_info *)ctx->extra_info; + h264e_hal_pps *pps = &extra_info->pps; h264e_hal_vpu_buffers *bufs = (h264e_hal_vpu_buffers *)ctx->buffers; MppEncH264Cfg *codec = &ctx->cfg->codec.h264; MppEncPrepCfg *prep = &ctx->cfg->prep; @@ -1293,7 +1293,7 @@ MPP_RET hal_h264e_vpu_gen_regs(void *hal, HalTaskInfo *task) | VEPU_REG_INTER_MODE(h264_inter_favor[hw_cfg->qp]); H264E_HAL_SET_REG(reg, VEPU_REG_INTRA_INTER_MODE, val); - val = VEPU_REG_PPS_INIT_QP(hw_cfg->pic_init_qp) + val = VEPU_REG_PPS_INIT_QP(pps->i_pic_init_qp) | VEPU_REG_SLICE_FILTER_ALPHA(hw_cfg->slice_alpha_offset) | VEPU_REG_SLICE_FILTER_BETA(hw_cfg->slice_beta_offset) | VEPU_REG_CHROMA_QP_OFFSET(hw_cfg->chroma_qp_index_offset)