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[vdpu34x]: add rcb_info for rkvdec

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tips:
    according to rcb_size descending, and sent rcb_info to the kernel.

Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
Change-Id: I85e951d9cc1c15962e702ab9781df35e6739bb6a
This commit is contained in:
Ding Wei
2021-01-13 17:19:29 +08:00
committed by Herman Chen
parent b84425e15d
commit b3ce4085f7
7 changed files with 110 additions and 55 deletions
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23
mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c
View File

@@ -88,9 +88,7 @@ typedef struct Vdpu34xH264dRegCtx_t {
RK_S32 width;
RK_S32 height;
RK_S32 rcb_buf_size;
RK_S32 rcb_reg[RCB_BUF_COUNT];
RK_S32 rcb_size[RCB_BUF_COUNT];
RK_S32 rcb_offset[RCB_BUF_COUNT];
Vdpu34xRcbInfo rcb_info[RCB_BUF_COUNT];
MppBuffer rcb_buf;
Vdpu34xH264dRegSet *regs;
@@ -787,8 +785,7 @@ MPP_RET vdpu34x_h264d_gen_regs(void *hal, HalTaskInfo *task)
rcb_buf = NULL;
}
ctx->rcb_buf_size = get_rcb_buf_size(ctx->rcb_reg, ctx->rcb_size,
ctx->rcb_offset, width, height);
ctx->rcb_buf_size = get_rcb_buf_size(ctx->rcb_info, width, height);
mpp_buffer_get(p_hal->buf_group, &rcb_buf, ctx->rcb_buf_size);
ctx->rcb_buf = rcb_buf;
@@ -796,7 +793,10 @@ MPP_RET vdpu34x_h264d_gen_regs(void *hal, HalTaskInfo *task)
ctx->height = height;
}
vdpu34x_setup_rcb(&regs->common_addr, rcb_buf, ctx->rcb_offset);
vdpu34x_setup_rcb(&regs->common_addr, rcb_buf, ctx->rcb_info);
/* sort by dec*/
qsort(ctx->rcb_info, MPP_ARRAY_ELEMS(ctx->rcb_info),
sizeof(ctx->rcb_info[0]), vdpu34x_compare_rcb_size);
__RETURN:
return ret = MPP_OK;
@@ -872,7 +872,18 @@ MPP_RET vdpu34x_h264d_start(void *hal, HalTaskInfo *task)
mpp_err_f("set register read failed %d\n", ret);
break;
}
/* rcb info for sram */
{
RK_U32 i = 0;
MppDevRcbInfoCfg rcb_cfg;
for (i = 0; i < MPP_ARRAY_ELEMS(reg_ctx->rcb_info); i++) {
rcb_cfg.reg_idx = reg_ctx->rcb_info[i].reg;
rcb_cfg.size = reg_ctx->rcb_info[i].size;
if (rcb_cfg.size > 0)
mpp_dev_ioctl(dev, MPP_DEV_RCB_INFO, &rcb_cfg);
}
}
/* send request to hardware */
ret = mpp_dev_ioctl(dev, MPP_DEV_CMD_SEND, NULL);
if (ret) {

4
mpp/hal/rkdec/h265d/hal_h265d_ctx.h
View File

@@ -53,9 +53,7 @@ typedef struct HalH265dCtx_t {
RK_S32 width;
RK_S32 height;
RK_S32 rcb_buf_size;
RK_S32 rcb_reg[RCB_BUF_COUNT];
RK_S32 rcb_size[RCB_BUF_COUNT];
RK_S32 rcb_offset[RCB_BUF_COUNT];
Vdpu34xRcbInfo rcb_info[RCB_BUF_COUNT];
MppBuffer rcb_buf;
void* hw_regs;

20
mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
View File

@@ -998,8 +998,7 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn)
rcb_buf = NULL;
}
reg_cxt->rcb_buf_size = get_rcb_buf_size(reg_cxt->rcb_reg, reg_cxt->rcb_size,
reg_cxt->rcb_offset, width, height);
reg_cxt->rcb_buf_size = get_rcb_buf_size(reg_cxt->rcb_info, width, height);
mpp_buffer_get(reg_cxt->group, &rcb_buf, reg_cxt->rcb_buf_size);
reg_cxt->rcb_buf = rcb_buf;
@@ -1007,7 +1006,10 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn)
reg_cxt->height = height;
}
vdpu34x_setup_rcb(&hw_regs->common_addr, rcb_buf, reg_cxt->rcb_offset);
vdpu34x_setup_rcb(&hw_regs->common_addr, rcb_buf, reg_cxt->rcb_info);
/* sort by dec */
qsort(reg_cxt->rcb_info, MPP_ARRAY_ELEMS(reg_cxt->rcb_info),
sizeof(reg_cxt->rcb_info[0]), vdpu34x_compare_rcb_size);
return ret;
}
@@ -1020,7 +1022,7 @@ static MPP_RET hal_h265d_vdpu34x_start(void *hal, HalTaskInfo *task)
HalH265dCtx *reg_cxt = (HalH265dCtx *)hal;
RK_S32 index = task->dec.reg_index;
RK_S32 i;
RK_U32 i;
if (task->dec.flags.parse_err ||
task->dec.flags.ref_err) {
@@ -1100,7 +1102,17 @@ static MPP_RET hal_h265d_vdpu34x_start(void *hal, HalTaskInfo *task)
mpp_err_f("set register read failed %d\n", ret);
break;
}
/* rcb info for sram */
{
MppDevRcbInfoCfg rcb_cfg;
for (i = 0; i < MPP_ARRAY_ELEMS(reg_cxt->rcb_info); i++) {
rcb_cfg.reg_idx = reg_cxt->rcb_info[i].reg;
rcb_cfg.size = reg_cxt->rcb_info[i].size;
if (rcb_cfg.size > 0)
mpp_dev_ioctl(reg_cxt->dev, MPP_DEV_RCB_INFO, &rcb_cfg);
}
}
ret = mpp_dev_ioctl(reg_cxt->dev, MPP_DEV_CMD_SEND, NULL);
if (ret) {
mpp_err_f("send cmd failed %d\n", ret);

12
mpp/hal/rkdec/inc/vdpu34x_com.h
View File

@@ -410,13 +410,19 @@ typedef struct Vdpu34xRegStatistic_t {
RK_U16 reg276_v_max_value;
} Vdpu34xRegStatistic;
typedef struct vdpu34x_rcb_info_t {
RK_S32 reg;
RK_S32 size;
RK_S32 offset;
} Vdpu34xRcbInfo;
#ifdef __cplusplus
extern "C" {
#endif
RK_S32 get_rcb_buf_size(RK_S32 *regs, RK_S32 *sizes,
RK_S32 *offsets, RK_S32 width, RK_S32 height);
void vdpu34x_setup_rcb(Vdpu34xRegCommonAddr *reg, MppBuffer buf, RK_S32 *offsets);
RK_S32 get_rcb_buf_size(Vdpu34xRcbInfo *info, RK_S32 width, RK_S32 height);
void vdpu34x_setup_rcb(Vdpu34xRegCommonAddr *reg, MppBuffer buf, Vdpu34xRcbInfo *info);
RK_S32 vdpu34x_compare_rcb_size(const void *a, const void *b);
void vdpu34x_setup_statistic(Vdpu34xRegCommon *com, Vdpu34xRegStatistic *sta);
#ifdef __cplusplus

78
mpp/hal/rkdec/vdpu34x_com.c
View File

@@ -37,51 +37,63 @@ static RK_U32 rcb_coeff[RCB_BUF_COUNT] = {
[RCB_FILT_COL] = 67, /* RCB_FILT_COL_COEF */
};
#define UPDATE_SIZE_OFFSET(regs, reg, sizes, offsets, offset, len, idx) \
do { \
RK_S32 buf_size = MPP_ALIGN(len * rcb_coeff[idx], RCB_ALLINE_SIZE);\
regs[idx] = reg; \
offsets[idx] = offset; \
sizes[idx] = buf_size; \
offset += buf_size; \
} while (0)
static RK_S32 update_size_offset(Vdpu34xRcbInfo *info, RK_U32 reg,
RK_S32 offset, RK_S32 len, RK_S32 idx)
{
RK_S32 buf_size = 0;
RK_S32 get_rcb_buf_size(RK_S32 *regs, RK_S32 *sizes,
RK_S32 *offsets, RK_S32 width, RK_S32 height)
buf_size = MPP_ALIGN(len * rcb_coeff[idx], RCB_ALLINE_SIZE);
info[idx].reg = reg;
info[idx].offset = offset;
info[idx].size = buf_size;
return buf_size;
}
RK_S32 get_rcb_buf_size(Vdpu34xRcbInfo *info, RK_S32 width, RK_S32 height)
{
RK_S32 offset = 0;
mpp_assert(sizes);
UPDATE_SIZE_OFFSET(regs, 139, sizes, offsets, offset, width, RCB_DBLK_ROW);
UPDATE_SIZE_OFFSET(regs, 133, sizes, offsets, offset, width, RCB_INTRA_ROW);
UPDATE_SIZE_OFFSET(regs, 134, sizes, offsets, offset, width, RCB_TRANSD_ROW);
UPDATE_SIZE_OFFSET(regs, 136, sizes, offsets, offset, width, RCB_STRMD_ROW);
UPDATE_SIZE_OFFSET(regs, 137, sizes, offsets, offset, width, RCB_INTER_ROW);
UPDATE_SIZE_OFFSET(regs, 140, sizes, offsets, offset, width, RCB_SAO_ROW);
UPDATE_SIZE_OFFSET(regs, 141, sizes, offsets, offset, width, RCB_FBC_ROW);
offset += update_size_offset(info, 139, offset, width, RCB_DBLK_ROW);
offset += update_size_offset(info, 133, offset, width, RCB_INTRA_ROW);
offset += update_size_offset(info, 134, offset, width, RCB_TRANSD_ROW);
offset += update_size_offset(info, 136, offset, width, RCB_STRMD_ROW);
offset += update_size_offset(info, 137, offset, width, RCB_INTER_ROW);
offset += update_size_offset(info, 140, offset, width, RCB_SAO_ROW);
offset += update_size_offset(info, 141, offset, width, RCB_FBC_ROW);
/* col rcb */
UPDATE_SIZE_OFFSET(regs, 135, sizes, offsets, offset, height, RCB_TRANSD_COL);
UPDATE_SIZE_OFFSET(regs, 138, sizes, offsets, offset, height, RCB_INTER_COL);
UPDATE_SIZE_OFFSET(regs, 142, sizes, offsets, offset, height, RCB_FILT_COL);
offset += update_size_offset(info, 135, offset, height, RCB_TRANSD_COL);
offset += update_size_offset(info, 138, offset, height, RCB_INTER_COL);
offset += update_size_offset(info, 142, offset, height, RCB_FILT_COL);
return offset;
}
void vdpu34x_setup_rcb(Vdpu34xRegCommonAddr *reg, MppBuffer buf, RK_S32 *offset)
void vdpu34x_setup_rcb(Vdpu34xRegCommonAddr *reg, MppBuffer buf, Vdpu34xRcbInfo *info)
{
RK_S32 fd = mpp_buffer_get_fd(buf);
reg->reg139_rcb_dblk_base = fd + (offset[RCB_DBLK_ROW] << 10);
reg->reg133_rcb_intra_base = fd + (offset[RCB_INTRA_ROW] << 10);
reg->reg134_rcb_transd_row_base = fd + (offset[RCB_TRANSD_ROW] << 10);
reg->reg136_rcb_streamd_row_base = fd + (offset[RCB_STRMD_ROW] << 10);
reg->reg137_rcb_inter_row_base = fd + (offset[RCB_INTER_ROW] << 10);
reg->reg140_rcb_sao_base = fd + (offset[RCB_SAO_ROW] << 10);
reg->reg141_rcb_fbc_base = fd + (offset[RCB_FBC_ROW] << 10);
reg->reg135_rcb_transd_col_base = fd + (offset[RCB_TRANSD_COL] << 10);
reg->reg138_rcb_inter_col_base = fd + (offset[RCB_INTER_COL] << 10);
reg->reg142_rcb_filter_col_base = fd + (offset[RCB_FILT_COL] << 10);
reg->reg139_rcb_dblk_base = fd + (info[RCB_DBLK_ROW].offset << 10);
reg->reg133_rcb_intra_base = fd + (info[RCB_INTRA_ROW].offset << 10);
reg->reg134_rcb_transd_row_base = fd + (info[RCB_TRANSD_ROW].offset << 10);
reg->reg136_rcb_streamd_row_base = fd + (info[RCB_STRMD_ROW].offset << 10);
reg->reg137_rcb_inter_row_base = fd + (info[RCB_INTER_ROW].offset << 10);
reg->reg140_rcb_sao_base = fd + (info[RCB_SAO_ROW].offset << 10);
reg->reg141_rcb_fbc_base = fd + (info[RCB_FBC_ROW].offset << 10);
reg->reg135_rcb_transd_col_base = fd + (info[RCB_TRANSD_COL].offset << 10);
reg->reg138_rcb_inter_col_base = fd + (info[RCB_INTER_COL].offset << 10);
reg->reg142_rcb_filter_col_base = fd + (info[RCB_FILT_COL].offset << 10);
}
RK_S32 vdpu34x_compare_rcb_size(const void *a, const void *b)
{
RK_S32 val = 0;
Vdpu34xRcbInfo *p0 = (Vdpu34xRcbInfo *)a;
Vdpu34xRcbInfo *p1 = (Vdpu34xRcbInfo *)b;
val = (p0->size > p1->size) ? -1 : 1;
return val;
}
void vdpu34x_setup_statistic(Vdpu34xRegCommon *com, Vdpu34xRegStatistic *sta)

23
mpp/hal/rkdec/vp9d/hal_vp9d_vdpu34x.c
View File

@@ -58,9 +58,7 @@ typedef struct Vdpu34xVp9dCtx_t {
RK_S32 height;
/* rcb buffers info */
RK_S32 rcb_buf_size;
RK_S32 rcb_reg[RCB_BUF_COUNT];
RK_S32 rcb_size[RCB_BUF_COUNT];
RK_S32 rcb_offset[RCB_BUF_COUNT];
Vdpu34xRcbInfo rcb_info[RCB_BUF_COUNT];
MppBuffer rcb_buf;
/* colmv buffers info */
HalBufs cmv_bufs;
@@ -687,8 +685,7 @@ static MPP_RET hal_vp9d_vdpu34x_gen_regs(void *hal, HalTaskInfo *task)
rcb_buf = NULL;
}
hw_ctx->rcb_buf_size = get_rcb_buf_size(hw_ctx->rcb_reg, hw_ctx->rcb_size,
hw_ctx->rcb_offset, width, height);
hw_ctx->rcb_buf_size = get_rcb_buf_size(hw_ctx->rcb_info, width, height);
mpp_buffer_get(p_hal ->group, &rcb_buf, hw_ctx->rcb_buf_size);
hw_ctx->rcb_buf = rcb_buf;
@@ -696,7 +693,10 @@ static MPP_RET hal_vp9d_vdpu34x_gen_regs(void *hal, HalTaskInfo *task)
hw_ctx->height = height;
}
vdpu34x_setup_rcb(&vp9_hw_regs->common_addr, rcb_buf, hw_ctx->rcb_offset);
vdpu34x_setup_rcb(&vp9_hw_regs->common_addr, rcb_buf, hw_ctx->rcb_info);
/* sort by dec */
qsort(hw_ctx->rcb_info, MPP_ARRAY_ELEMS(hw_ctx->rcb_info),
sizeof(hw_ctx->rcb_info[0]), vdpu34x_compare_rcb_size);
}
// whether need update counts
@@ -809,7 +809,18 @@ static MPP_RET hal_vp9d_vdpu34x_start(void *hal, HalTaskInfo *task)
mpp_err_f("set register read failed %d\n", ret);
break;
}
/* rcb info for sram */
{
RK_U32 i = 0;
MppDevRcbInfoCfg rcb_cfg;
for (i = 0; i < MPP_ARRAY_ELEMS(hw_ctx->rcb_info); i++) {
rcb_cfg.reg_idx = hw_ctx->rcb_info[i].reg;
rcb_cfg.size = hw_ctx->rcb_info[i].size;
if (rcb_cfg.size > 0)
mpp_dev_ioctl(dev, MPP_DEV_RCB_INFO, &rcb_cfg);
}
}
ret = mpp_dev_ioctl(dev, MPP_DEV_CMD_SEND, NULL);
if (ret) {
mpp_err_f("send cmd failed %d\n", ret);

5
osal/driver/mpp_service.c
View File

@@ -387,6 +387,11 @@ MPP_RET mpp_service_reg_offset(void *ctx, MppDevRegOffsetCfg *cfg)
MPP_RET mpp_service_rcb_info(void *ctx, MppDevRcbInfoCfg *cfg)
{
MppDevMppService *p = (MppDevMppService *)ctx;
RK_U32 rcb_info_disable = 0;
mpp_env_get_u32("disable_rcb_info", &rcb_info_disable, 0);
if (rcb_info_disable)
return MPP_OK;
if (!p->support_set_rcb_info)
return MPP_OK;