From b25d0b475d61e28ce5bc794f1750c4e2ce78d48f Mon Sep 17 00:00:00 2001 From: Herman Chen Date: Fri, 14 Jan 2022 17:28:58 +0800 Subject: [PATCH] [h264e_vepu580]: Update tinetune parameter Fix tailing at low light scene. Change-Id: I57df8b8d6ac48c1090076a586c07cd816c1e6dfb Signed-off-by: Herman Chen --- mpp/hal/rkenc/h264e/hal_h264e_vepu580.c | 34 ++++++++++++------------- mpp/hal/rkenc/h265e/hal_h265e_vepu580.c | 4 +-- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/mpp/hal/rkenc/h264e/hal_h264e_vepu580.c b/mpp/hal/rkenc/h264e/hal_h264e_vepu580.c index 04e38716..c9a57623 100644 --- a/mpp/hal/rkenc/h264e/hal_h264e_vepu580.c +++ b/mpp/hal/rkenc/h264e/hal_h264e_vepu580.c @@ -81,8 +81,6 @@ typedef struct HalH264eVepu580Ctx_t { HalVepu580RegSet regs_set; } HalH264eVepu580Ctx; -#include "hal_h264e_vepu580_tune.c" - #define CHROMA_KLUT_TAB_SIZE (24 * sizeof(RK_U32)) static RK_U32 h264e_klut_weight[30] = { @@ -120,6 +118,8 @@ static RK_S32 h264_I_aq_step_default[16] = { 4, 5, 6, 8, }; +#include "hal_h264e_vepu580_tune.c" + static MPP_RET hal_h264e_vepu580_deinit(void *hal) { HalH264eVepu580Ctx *p = (HalH264eVepu580Ctx *)hal; @@ -827,15 +827,15 @@ static void setup_vepu580_rdo_cfg(Vepu580RdoCfg *regs) regs->rdo_intra_var_thd3.atf_rdo_intra_var_thd31 = 100; /* 0x20E4 ~ 0x20F0 */ - regs->rdo_intra_atf_wgt0.atf_rdo_intra_wgt00 = 80; - regs->rdo_intra_atf_wgt0.atf_rdo_intra_wgt01 = 64; - regs->rdo_intra_atf_wgt0.atf_rdo_intra_wgt02 = 48; - regs->rdo_intra_atf_wgt1.atf_rdo_intra_wgt10 = 33; - regs->rdo_intra_atf_wgt1.atf_rdo_intra_wgt11 = 32; - regs->rdo_intra_atf_wgt1.atf_rdo_intra_wgt12 = 30; - regs->rdo_intra_atf_wgt2.atf_rdo_intra_wgt20 = 28; - regs->rdo_intra_atf_wgt2.atf_rdo_intra_wgt21 = 27; - regs->rdo_intra_atf_wgt2.atf_rdo_intra_wgt22 = 26; + regs->rdo_intra_atf_wgt0.atf_rdo_intra_wgt00 = 24; + regs->rdo_intra_atf_wgt0.atf_rdo_intra_wgt01 = 22; + regs->rdo_intra_atf_wgt0.atf_rdo_intra_wgt02 = 21; + regs->rdo_intra_atf_wgt1.atf_rdo_intra_wgt10 = 22; + regs->rdo_intra_atf_wgt1.atf_rdo_intra_wgt11 = 21; + regs->rdo_intra_atf_wgt1.atf_rdo_intra_wgt12 = 20; + regs->rdo_intra_atf_wgt2.atf_rdo_intra_wgt20 = 20; + regs->rdo_intra_atf_wgt2.atf_rdo_intra_wgt21 = 19; + regs->rdo_intra_atf_wgt2.atf_rdo_intra_wgt22 = 18; regs->rdo_intra_atf_wgt3.atf_rdo_intra_wgt30 = 16; regs->rdo_intra_atf_wgt3.atf_rdo_intra_wgt31 = 16; regs->rdo_intra_atf_wgt3.atf_rdo_intra_wgt32 = 16; @@ -1043,13 +1043,13 @@ static void setup_vepu580_rc_base(HalVepu580RegSet *regs, H264eSps *sps, { /* 0x1070 ~ 0x1074 */ - regs->reg_rc_klut.md_sad_thd.md_sad_thd0 = 25; - regs->reg_rc_klut.md_sad_thd.md_sad_thd1 = 25; - regs->reg_rc_klut.md_sad_thd.md_sad_thd2 = 25; + regs->reg_rc_klut.md_sad_thd.md_sad_thd0 = 4; + regs->reg_rc_klut.md_sad_thd.md_sad_thd1 = 9; + regs->reg_rc_klut.md_sad_thd.md_sad_thd2 = 15; - regs->reg_rc_klut.madi_thd.madi_thd0 = 25; - regs->reg_rc_klut.madi_thd.madi_thd1 = 25; - regs->reg_rc_klut.madi_thd.madi_thd2 = 25; + regs->reg_rc_klut.madi_thd.madi_thd0 = 4; + regs->reg_rc_klut.madi_thd.madi_thd1 = 9; + regs->reg_rc_klut.madi_thd.madi_thd2 = 15; } hal_h264e_dbg_func("leave\n"); diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu580.c b/mpp/hal/rkenc/h265e/hal_h265e_vepu580.c index c9b8c132..c2ee34f5 100644 --- a/mpp/hal/rkenc/h265e/hal_h265e_vepu580.c +++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu580.c @@ -101,8 +101,6 @@ typedef struct H265eV580HalContext_t { void *tune; } H265eV580HalContext; -#include "hal_h265e_vepu580_tune.c" - #define TILE_BUF_SIZE MPP_ALIGN(128 * 1024, 256) static RK_U32 klut_weight[24] = { @@ -164,6 +162,8 @@ static RK_U32 lamd_modb_qp[52] = { 0x00700000, 0x00890000, 0x00b00000, 0x00e00000 }; +#include "hal_h265e_vepu580_tune.c" + static void vepu580_h265_set_me_ram(H265eSyntax_new *syn, hevc_vepu580_base *regs, RK_U32 index) { RK_S32 frm_sta = 0, frm_end = 0, pic_w = 0;