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[m4vd]: adjust register configuration

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The bit 19 of reg136 is similar with bit 6 of reg120, but only
the former is set based on C Model. After that, both field
and frame mode are OK.

Change-Id: I066b813a772def2a718d2fb7f90a6f73fb8afa20
Signed-off-by: timkingh.huang <timkingh.huang@rock-chips.com>
This commit is contained in:
timkingh.huang
2016-12-09 09:28:24 +08:00
parent 167f333065
commit ae1611601c
2 changed files with 8 additions and 2 deletions
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8
mpp/hal/vpu/mpg4d/hal_mpg4d_reg.c
View File

@@ -143,7 +143,13 @@ static void vpu_mpg4d_setup_regs_by_syntax(hal_mpg4_ctx *ctx, MppSyntax syntax)
regs->reg120.sw_mb_height_off = 0; regs->reg120.sw_mb_height_off = 0;
} }
regs->reg53_dec_mode = 1; regs->reg53_dec_mode = 1;
regs->reg120.sw_alt_scan_e = pp->alternate_vertical_scan_flag;
/* note: When comparing bit 19 of reg136(that is sw_alt_scan_flag_e) with bit 6 of
** reg120(that is sw_alt_scan_e), we may be confused about the function of
** these two bits. According to C Model, just sw_alt_scan_flag_e is set,
** but not sw_alt_scan_e.
*/
regs->reg136.sw_alt_scan_flag_e = pp->alternate_vertical_scan_flag;
regs->reg52_error_concealment.sw_startmb_x = 0; regs->reg52_error_concealment.sw_startmb_x = 0;
regs->reg52_error_concealment.sw_startmb_y = 0; regs->reg52_error_concealment.sw_startmb_y = 0;
regs->reg50_dec_ctrl.sw_filtering_dis = 1; regs->reg50_dec_ctrl.sw_filtering_dis = 1;

2
mpp/hal/vpu/mpg4d/hal_mpg4d_reg.h
View File

@@ -300,7 +300,7 @@ typedef struct {
RK_U32 sw_hrz_bit_of_bwd_mv : 4; RK_U32 sw_hrz_bit_of_bwd_mv : 4;
RK_U32 sw_vrz_bit_of_fwd_mv : 4; RK_U32 sw_vrz_bit_of_fwd_mv : 4;
RK_U32 sw_hrz_bit_of_fwd_mv : 4; RK_U32 sw_hrz_bit_of_fwd_mv : 4;
RK_U32 sw_alt_scan : 1; RK_U32 sw_alt_scan_flag_e : 1;
RK_U32 sw_reserve : 12; RK_U32 sw_reserve : 12;
} reg136; } reg136;