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[h264e_vepu]: add cfg to disable mb rc

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Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I71e72164756b23f181a67a8b8799b9867a0854fb
This commit is contained in:
Yandong Lin
2021-11-09 10:40:56 +08:00
committed by Herman Chen
parent 0bc33cf484
commit ac6f8b1384
4 changed files with 12 additions and 3 deletions
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4
inc/rk_venc_cmd.h
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@@ -374,6 +374,7 @@ typedef enum MppEncHwCfgChange_e {
MPP_ENC_HW_CFG_CHANGE_AQ_THRD_P = (1 << 3), MPP_ENC_HW_CFG_CHANGE_AQ_THRD_P = (1 << 3),
MPP_ENC_HW_CFG_CHANGE_AQ_STEP_I = (1 << 4), MPP_ENC_HW_CFG_CHANGE_AQ_STEP_I = (1 << 4),
MPP_ENC_HW_CFG_CHANGE_AQ_STEP_P = (1 << 5), MPP_ENC_HW_CFG_CHANGE_AQ_STEP_P = (1 << 5),
MPP_ENC_HW_CFG_CHANGE_MB_RC = (1 << 6),
MPP_ENC_HW_CFG_CHANGE_ALL = (0xFFFFFFFF), MPP_ENC_HW_CFG_CHANGE_ALL = (0xFFFFFFFF),
} MppEncHwCfgChange; } MppEncHwCfgChange;
@@ -393,6 +394,9 @@ typedef struct MppEncHwCfg_t {
RK_U32 aq_thrd_p[16]; RK_U32 aq_thrd_p[16];
RK_S32 aq_step_i[16]; RK_S32 aq_step_i[16];
RK_S32 aq_step_p[16]; RK_S32 aq_step_p[16];
/* vepu1/2 */
RK_S32 mb_rc_disable;
} MppEncHwCfg; } MppEncHwCfg;
/* /*

5
mpp/base/mpp_enc_cfg.cpp
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@@ -239,7 +239,8 @@ RK_U32 mpp_enc_cfg_debug = 0;
ENTRY(hw, aq_thrd_i, St, RK_S32 *, MPP_ENC_HW_CFG_CHANGE_AQ_THRD_I, hw, aq_thrd_i) \ ENTRY(hw, aq_thrd_i, St, RK_S32 *, MPP_ENC_HW_CFG_CHANGE_AQ_THRD_I, hw, aq_thrd_i) \
ENTRY(hw, aq_thrd_p, St, RK_S32 *, MPP_ENC_HW_CFG_CHANGE_AQ_THRD_P, hw, aq_thrd_p) \ ENTRY(hw, aq_thrd_p, St, RK_S32 *, MPP_ENC_HW_CFG_CHANGE_AQ_THRD_P, hw, aq_thrd_p) \
ENTRY(hw, aq_step_i, St, RK_S32 *, MPP_ENC_HW_CFG_CHANGE_AQ_STEP_I, hw, aq_step_i) \ ENTRY(hw, aq_step_i, St, RK_S32 *, MPP_ENC_HW_CFG_CHANGE_AQ_STEP_I, hw, aq_step_i) \
ENTRY(hw, aq_step_p, St, RK_S32 *, MPP_ENC_HW_CFG_CHANGE_AQ_STEP_P, hw, aq_step_p) ENTRY(hw, aq_step_p, St, RK_S32 *, MPP_ENC_HW_CFG_CHANGE_AQ_STEP_P, hw, aq_step_p) \
ENTRY(hw, mb_rc_disable, S32, RK_S32, MPP_ENC_HW_CFG_CHANGE_MB_RC, hw, mb_rc_disable)
ENTRY_TABLE(EXPAND_AS_FUNC) ENTRY_TABLE(EXPAND_AS_FUNC)
ENTRY_TABLE(EXPAND_AS_API) ENTRY_TABLE(EXPAND_AS_API)
@@ -253,7 +254,7 @@ RK_S32 const_strlen(const char* str)
return *str ? 1 + const_strlen(str + 1) : 0; return *str ? 1 + const_strlen(str + 1) : 0;
} }
static RK_S32 node_len = ENTRY_TABLE(EXPAND_AS_STRLEN) - 61; static RK_S32 node_len = ENTRY_TABLE(EXPAND_AS_STRLEN) - 52;
class MppEncCfgService class MppEncCfgService
{ {

3
mpp/codec/mpp_enc_impl.cpp
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@@ -637,6 +637,9 @@ MPP_RET mpp_enc_proc_hw_cfg(MppEncHwCfg *dst, MppEncHwCfg *src)
if (change & MPP_ENC_HW_CFG_CHANGE_AQ_STEP_P) if (change & MPP_ENC_HW_CFG_CHANGE_AQ_STEP_P)
memcpy(dst->aq_step_p, src->aq_step_p, sizeof(dst->aq_step_p)); memcpy(dst->aq_step_p, src->aq_step_p, sizeof(dst->aq_step_p));
if (change & MPP_ENC_HW_CFG_CHANGE_MB_RC)
dst->mb_rc_disable = src->mb_rc_disable;
if (dst->qp_delta_row < 0 || dst->qp_delta_row_i < 0) { if (dst->qp_delta_row < 0 || dst->qp_delta_row_i < 0) {
mpp_err("invalid hw qp delta row [%d:%d]\n", mpp_err("invalid hw qp delta row [%d:%d]\n",
dst->qp_delta_row_i, dst->qp_delta_row); dst->qp_delta_row_i, dst->qp_delta_row);

3
mpp/hal/vpu/h264e/hal_h264e_vepu_v2.c
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@@ -495,6 +495,7 @@ MPP_RET h264e_vepu_mbrc_setup(HalH264eVepuMbRcCtx ctx, MppEncCfgSet*cfg)
HalH264eVepuMbRcImpl *p = (HalH264eVepuMbRcImpl *)ctx; HalH264eVepuMbRcImpl *p = (HalH264eVepuMbRcImpl *)ctx;
MppEncPrepCfg *prep = &cfg->prep; MppEncPrepCfg *prep = &cfg->prep;
MppEncRcCfg *rc = &cfg->rc; MppEncRcCfg *rc = &cfg->rc;
MppEncHwCfg* hw_cfg = &cfg->hw;
hal_h264e_dbg_func("enter\n"); hal_h264e_dbg_func("enter\n");
@@ -523,7 +524,7 @@ MPP_RET h264e_vepu_mbrc_setup(HalH264eVepuMbRcCtx ctx, MppEncCfgSet*cfg)
p->fps_count = p->fps_threshold; p->fps_count = p->fps_threshold;
// if not constant // if not constant
p->mb_bit_rc_enable = rc->rc_mode != MPP_ENC_RC_MODE_FIXQP; p->mb_bit_rc_enable = !hw_cfg->mb_rc_disable && (rc->rc_mode != MPP_ENC_RC_MODE_FIXQP);
hal_h264e_dbg_rc("estimated init qp %d\n", p->qp_init_est); hal_h264e_dbg_rc("estimated init qp %d\n", p->qp_init_est);