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feat[h265d]: Add vdpu383 hevc yuv444_10bit support

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Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
Change-Id: I14d7a8fac9f14283ecc364142ea93d80eda43fcd
This commit is contained in:
Chandler Chen
2024-12-31 18:05:34 +08:00
committed by Herman Chen
parent fb957ea36a
commit a524df5361
4 changed files with 51 additions and 12 deletions
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10
mpp/base/mpp_buf_slot.cpp
View File

@@ -294,7 +294,8 @@ static void prepare_info_set_legacy(MppBufSlotsImpl *impl, MppFrame frame,
const RK_U32 height = mpp_frame_get_height(frame);
const MppFrameFormat fmt = mpp_frame_get_fmt(frame);
RK_U32 depth = ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV420SP_10BIT ||
(fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV422SP_10BIT) ? 10 : 8;
(fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV422SP_10BIT ||
(fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV444SP_10BIT) ? 10 : 8;
RK_U32 codec_hor_stride = mpp_frame_get_hor_stride(frame);
RK_U32 codec_ver_stride = mpp_frame_get_ver_stride(frame);
RK_U32 hal_hor_stride = (codec_hor_stride) ?
@@ -319,7 +320,8 @@ static void prepare_info_set_legacy(MppBufSlotsImpl *impl, MppFrame frame,
switch (fmt & MPP_FRAME_FMT_MASK) {
case MPP_FMT_YUV420SP_10BIT:
case MPP_FMT_YUV422SP_10BIT: {
case MPP_FMT_YUV422SP_10BIT:
case MPP_FMT_YUV444SP_10BIT: {
hor_stride_pixel = hal_hor_stride * 8 / 10;
} break;
case MPP_FMT_YUV422_YVYU:
@@ -357,6 +359,9 @@ static void prepare_info_set_legacy(MppBufSlotsImpl *impl, MppFrame frame,
case MPP_FMT_YUV444SP : {
size = get_afbc_min_size(hor_stride_pixel, hal_ver_stride, 24);
} break;
case MPP_FMT_YUV444SP_10BIT : {
size = get_afbc_min_size(hor_stride_pixel, hal_ver_stride, 30);
} break;
default : {
size = hal_hor_stride * hal_ver_stride * 3 / 2;
mpp_err("dec out fmt is no support");
@@ -466,6 +471,7 @@ static void generate_info_set(MppBufSlotsImpl *impl, MppFrame frame, RK_U32 forc
case MPP_FMT_YUV422SP : {
downscale_buf_size = down_scale_y_virstride * 2;
} break;
case MPP_FMT_YUV444SP_10BIT :
case MPP_FMT_YUV444SP : {
downscale_buf_size = down_scale_y_virstride * 3;
} break;

14
mpp/codec/dec/h265/h265d_ps.c
View File

@@ -1514,7 +1514,7 @@ RK_S32 mpp_hevc_decode_nal_sps(HEVCContext *s)
case 8: sps->pix_fmt = MPP_FMT_YUV420SP; break;
case 10: sps->pix_fmt = MPP_FMT_YUV420SP_10BIT; break;
default:
mpp_err( "Unsupported bit depth: %d\n",
mpp_err("Unsupported bit depth: %d\n",
sps->bit_depth);
ret = MPP_ERR_PROTOL;
goto err;
@@ -1525,7 +1525,7 @@ RK_S32 mpp_hevc_decode_nal_sps(HEVCContext *s)
case 8: sps->pix_fmt = MPP_FMT_YUV422SP; break;
case 10: sps->pix_fmt = MPP_FMT_YUV422SP_10BIT; break;
default:
mpp_err( "Unsupported bit depth: %d\n",
mpp_err("Unsupported bit depth: %d\n",
sps->bit_depth);
ret = MPP_ERR_PROTOL;
goto err;
@@ -1533,7 +1533,15 @@ RK_S32 mpp_hevc_decode_nal_sps(HEVCContext *s)
mpp_slots_set_prop(s->slots, SLOTS_LEN_ALIGN, rkv_len_align_422);
} break;
case H265_CHROMA_444 : {
sps->pix_fmt = MPP_FMT_YUV444SP;
switch (sps->bit_depth) {
case 8: sps->pix_fmt = MPP_FMT_YUV444SP; break;
case 10: sps->pix_fmt = MPP_FMT_YUV444SP_10BIT; break;
default:
mpp_err("Unsupported bit depth: %d\n",
sps->bit_depth);
ret = MPP_ERR_PROTOL;
goto err;
}
mpp_slots_set_prop(s->slots, SLOTS_LEN_ALIGN, rkv_len_align_444);
} break;
}

2
mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c
View File

@@ -1452,7 +1452,7 @@ static MPP_RET hal_h265d_vdpu383_control(void *hal, MpiCmd cmd_type, void *param
if (fmt == MPP_FMT_YUV422SP) {
mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, rkv_len_align_422);
} else if (fmt == MPP_FMT_YUV444SP) {
} else if (fmt == MPP_FMT_YUV444SP || fmt == MPP_FMT_YUV444SP_10BIT) {
mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, rkv_len_align_444);
}
if (MPP_FRAME_FMT_IS_FBC(fmt)) {

25
utils/utils.c
View File

@@ -189,6 +189,31 @@ void dump_mpp_frame_to_file(MppFrame frame, FILE *fp)
fwrite(tmp, 1, width * height * 2, fp);
mpp_free(tmp);
} break;
case MPP_FMT_YUV444SP_10BIT : {
RK_U32 i, k;
RK_U8 *base_y = base;
RK_U8 *base_c = base + h_stride * v_stride;
RK_U8 *tmp_line = (RK_U8 *)mpp_malloc(RK_U16, width);
if (!tmp_line) {
mpp_log("tmp_line malloc fail");
return;
}
for (i = 0; i < height; i++, base_y += h_stride) {
for (k = 0; k < MPP_ALIGN(width, 8) / 8; k++)
rearrange_pix(tmp_line, base_y, k);
fwrite(tmp_line, width * sizeof(RK_U16), 1, fp);
}
for (i = 0; i < (height * 2); i++, base_c += h_stride) {
for (k = 0; k < MPP_ALIGN(width, 8) / 8; k++)
rearrange_pix(tmp_line, base_c, k);
fwrite(tmp_line, width * sizeof(RK_U16), 1, fp);
}
MPP_FREE(tmp_line);
} break;
case MPP_FMT_YUV400: {
RK_U32 i;
RK_U8 *base_y = base;