From a05b01d84f4d4f9aab84d183be286e40c92fa2d5 Mon Sep 17 00:00:00 2001 From: Yandong Lin Date: Fri, 10 Feb 2023 14:47:58 +0800 Subject: [PATCH] [h264d_vdpu34x]: fix some filed video dec err for rk3588 In the case of rk3588 mutilcore decoding, some field sources are decoded error because the poc_hight is not configured correctly. Signed-off-by: Yandong Lin Change-Id: I850900a9139724bd58210ecbbd77ff46bf7e299c --- mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c | 54 ++++++++++--------------- 1 file changed, 21 insertions(+), 33 deletions(-) diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c b/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c index 2bef9e3a..c3291675 100644 --- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c +++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c @@ -539,7 +539,9 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal common->reg016_str_len = p_hal->strm_len; common->reg013.cur_pic_is_idr = p_hal->slice_long->idr_flag; common->reg012.colmv_compress_en = (pp->frame_mbs_only_flag) ? 1 : 0; - //!< caculate the yuv_frame_size + common->reg028.sw_poc_arb_flag = 0; + + /* caculate the yuv_frame_size */ { MppFrame mframe = NULL; RK_U32 hor_virstride = 0; @@ -566,7 +568,7 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal common->reg020_y_virstride.y_virstride = y_virstride / 16; } } - //!< set current + /* set current frame info */ { MppBuffer mbuffer = NULL; RK_S32 fd = -1; @@ -581,12 +583,17 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, pp->CurrPic.Index7Bits); regs->common_addr.reg131_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]); regs->common_addr.reg132_error_ref_base = fd; + /* + * poc_hight bit[0] : + * 0 -> top field or frame + * 1 -> bot field + */ if (pp->field_pic_flag) - regs->h264d_highpoc.reg204.cur_poc_highbit = 1 << pp->CurrPic.AssociatedFlag; // top:1 bot:2 + regs->h264d_highpoc.reg204.cur_poc_highbit = pp->CurrPic.AssociatedFlag; else - regs->h264d_highpoc.reg204.cur_poc_highbit = 0; // frame + regs->h264d_highpoc.reg204.cur_poc_highbit = 0; } - //!< set reference + /* set reference info */ { RK_S32 i = 0; RK_S32 ref_index = -1; @@ -595,7 +602,7 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal RK_U32 min_frame_num = 0; MppFrame mframe = NULL; - for (i = 0; i < 15; i++) { + for (i = 0; i <= 15; i++) { RK_U32 field_flag = (pp->RefPicFiledFlags >> i) & 0x01; RK_U32 top_used = (pp->UsedForReferenceFlags >> (2 * i + 0)) & 0x01; RK_U32 bot_used = (pp->UsedForReferenceFlags >> (2 * i + 1)) & 0x01; @@ -613,11 +620,15 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal } else { ref_index = (near_index < 0) ? pp->CurrPic.Index7Bits : near_index; } - /* mark 3 to differ from current frame */ - if (ref_index == pp->CurrPic.Index7Bits) { + + if (pp->field_pic_flag) { + SET_POC_HIGNBIT_INFO(regs->h264d_highpoc, 2 * i, poc_highbit, 0); + SET_POC_HIGNBIT_INFO(regs->h264d_highpoc, 2 * i + 1, poc_highbit, 1); + } else if (ref_index == pp->CurrPic.Index7Bits) { SET_POC_HIGNBIT_INFO(regs->h264d_highpoc, 2 * i, poc_highbit, 3); SET_POC_HIGNBIT_INFO(regs->h264d_highpoc, 2 * i + 1, poc_highbit, 3); } + mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_BUFFER, &mbuffer); mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_FRAME_PTR, &mframe); @@ -630,35 +641,12 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal common->reg021.error_intra_mode = 0; } - RK_S32 fd = mpp_buffer_get_fd(mbuffer); - regs->h264d_addr.ref_base[i] = fd; + regs->h264d_addr.ref_base[i] = mpp_buffer_get_fd(mbuffer); mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, ref_index); regs->h264d_addr.colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]); - } - regs->h264d_param.reg67_98_ref_poc[30] = pp->FieldOrderCntList[15][0]; - regs->h264d_param.reg67_98_ref_poc[31] = pp->FieldOrderCntList[15][1]; - regs->h264d_param.reg102.ref15_field = (pp->RefPicFiledFlags >> 15) & 0x01; - regs->h264d_param.reg102.ref15_topfield_used = (pp->UsedForReferenceFlags >> 30) & 0x01; - regs->h264d_param.reg102.ref15_botfield_used = (pp->UsedForReferenceFlags >> 31) & 0x01; - regs->h264d_param.reg102.ref15_colmv_use_flag = (pp->RefPicColmvUsedFlags >> 15) & 0x01; - - if (pp->RefFrameList[15].bPicEntry != 0xff) { - ref_index = pp->RefFrameList[15].Index7Bits; - } else { - ref_index = (near_index < 0) ? pp->CurrPic.Index7Bits : near_index; - } - /* mark 3 to differ from current frame */ - if (ref_index == pp->CurrPic.Index7Bits) { - regs->h264d_highpoc.reg203.ref30_poc_highbit = 3; - regs->h264d_highpoc.reg203.ref31_poc_highbit = 3; - } - mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_BUFFER, &mbuffer); - RK_S32 fd = mpp_buffer_get_fd(mbuffer); - regs->h264d_addr.ref_base[15] = fd; - mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, ref_index); - regs->h264d_addr.colmv_base[15] = mpp_buffer_get_fd(mv_buf->buf[0]); } + /* set input */ { MppBuffer mbuffer = NULL; Vdpu34xH264dRegCtx *reg_ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx;