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feat[venc]: Add qbias for rkvenc encoder

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Signed-off-by: hdl <hdl@rock-chips.com>
Change-Id: Ib463b777898a3c25bebbd2fcb95d872581f0b8f7
This commit is contained in:
hdl
2023-09-25 14:01:27 +08:00
committed by Herman Chen
parent de396c2ac2
commit 9ff2961dcf
11 changed files with 74 additions and 11 deletions
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6
inc/rk_venc_cmd.h
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@@ -428,6 +428,9 @@ typedef enum MppEncHwCfgChange_e {
MPP_ENC_HW_CFG_CHANGE_MB_RC = (1 << 6),
MPP_ENC_HW_CFG_CHANGE_CU_MODE_BIAS = (1 << 8),
MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS = (1 << 9),
MPP_ENC_HW_CFG_CHANGE_QBIAS_I = (1 << 10),
MPP_ENC_HW_CFG_CHANGE_QBIAS_P = (1 << 11),
MPP_ENC_HW_CFG_CHANGE_QBIAS_EN = (1 << 12),
MPP_ENC_HW_CFG_CHANGE_ALL = (0xFFFFFFFF),
} MppEncHwCfgChange;
@@ -443,6 +446,9 @@ typedef struct MppEncHwCfg_t {
/* vepu541/vepu540 */
RK_S32 qp_delta_row; /* delta qp between two row in P frame */
RK_S32 qp_delta_row_i; /* delta qp between two row in I frame */
RK_S32 qbias_i;
RK_S32 qbias_p;
RK_S32 qbias_en;
RK_U32 aq_thrd_i[16];
RK_U32 aq_thrd_p[16];
RK_S32 aq_step_i[16];

3
mpp/base/mpp_enc_cfg.cpp
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@@ -266,6 +266,9 @@ public:
ENTRY(hw, skip_bias_en, S32, RK_S32, MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS, hw, skip_bias_en) \
ENTRY(hw, skip_sad, S32, RK_S32, MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS, hw, skip_sad) \
ENTRY(hw, skip_bias, S32, RK_S32, MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS, hw, skip_bias) \
ENTRY(hw, qbias_i, S32, RK_S32, MPP_ENC_HW_CFG_CHANGE_QBIAS_I, hw, qbias_i) \
ENTRY(hw, qbias_p, S32, RK_S32, MPP_ENC_HW_CFG_CHANGE_QBIAS_P, hw, qbias_p) \
ENTRY(hw, qbias_en, S32, RK_S32, MPP_ENC_HW_CFG_CHANGE_QBIAS_EN, hw, qbias_en) \
/* quality fine tuning config */ \
ENTRY(tune, scene_mode, S32, MppEncSceneMode, MPP_ENC_TUNE_CFG_CHANGE_SCENE_MODE, tune, scene_mode)

9
mpp/codec/mpp_enc_impl.cpp
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@@ -800,6 +800,15 @@ MPP_RET mpp_enc_proc_hw_cfg(MppEncHwCfg *dst, MppEncHwCfg *src)
if (change & MPP_ENC_HW_CFG_CHANGE_AQ_STEP_P)
memcpy(dst->aq_step_p, src->aq_step_p, sizeof(dst->aq_step_p));
if (change & MPP_ENC_HW_CFG_CHANGE_QBIAS_I)
dst->qbias_i = src->qbias_i;
if (change & MPP_ENC_HW_CFG_CHANGE_QBIAS_P)
dst->qbias_p = src->qbias_p;
if (change & MPP_ENC_HW_CFG_CHANGE_QBIAS_EN)
dst->qbias_en = src->qbias_en;
if (change & MPP_ENC_HW_CFG_CHANGE_MB_RC)
dst->mb_rc_disable = src->mb_rc_disable;

8
mpp/hal/rkenc/h264e/hal_h264e_vepu540c.c
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@@ -173,6 +173,9 @@ static MPP_RET hal_h264e_vepu540c_init(void *hal, MppEncHalCfg *cfg)
hw->qp_delta_row_i = 1;
hw->qp_delta_row = 2;
hw->qbias_i = 683;
hw->qbias_p = 341;
hw->qbias_en = 0;
memcpy(hw->aq_thrd_i, h264_aq_tthd_default, sizeof(hw->aq_thrd_i));
memcpy(hw->aq_thrd_p, h264_aq_tthd_default, sizeof(hw->aq_thrd_p));
@@ -1278,8 +1281,13 @@ static void setup_vepu540c_l2(HalVepu540cRegSet *regs, H264eSlice *slice, MppEnc
memcpy(regs->reg_s3.rdo_wgta_qp_grpa_0_51, &h264e_lambda_default[6], H264E_LAMBDA_TAB_SIZE);
if (hw->qbias_en) {
regs->reg_s3.RDO_QUANT.quant_f_bias_I = hw->qbias_i;
regs->reg_s3.RDO_QUANT.quant_f_bias_P = hw->qbias_p;
} else {
regs->reg_s3.RDO_QUANT.quant_f_bias_I = 683;
regs->reg_s3.RDO_QUANT.quant_f_bias_P = 341;
}
regs->reg_s3.iprd_tthdy4_0.iprd_tthdy4_0 = 1;
regs->reg_s3.iprd_tthdy4_0.iprd_tthdy4_1 = 3;
regs->reg_s3.iprd_tthdy4_1.iprd_tthdy4_2 = 6;

7
mpp/hal/rkenc/h264e/hal_h264e_vepu541.c
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@@ -200,6 +200,9 @@ static MPP_RET hal_h264e_vepu541_init(void *hal, MppEncHalCfg *cfg)
hw->qp_delta_row_i = 0;
hw->qp_delta_row = 2;
hw->qbias_i = 683;
hw->qbias_p = 341;
hw->qbias_en = 0;
memcpy(hw->aq_thrd_i, h264_aq_tthd_default, sizeof(hw->aq_thrd_i));
memcpy(hw->aq_thrd_p, h264_aq_tthd_default, sizeof(hw->aq_thrd_p));
@@ -1507,6 +1510,10 @@ static void setup_vepu541_l2(Vepu541H264eRegL2Set *regs, H264eSlice *slice, MppE
/* 000556ab */
regs->qnt_bias_comb.qnt_bias_p = 171;
if (hw->qbias_en) {
regs->qnt_bias_comb.qnt_bias_i = hw->qbias_i;
regs->qnt_bias_comb.qnt_bias_p = hw->qbias_p;
}
regs->atr_thd0_h264.atr_thd0 = 1;
regs->atr_thd0_h264.atr_thd1 = 4;

3
mpp/hal/rkenc/h264e/hal_h264e_vepu580.c
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@@ -360,6 +360,9 @@ static MPP_RET hal_h264e_vepu580_init(void *hal, MppEncHalCfg *cfg)
hw->qp_delta_row_i = 2;
hw->qp_delta_row = 2;
hw->extra_buf = 1;
hw->qbias_i = 683;
hw->qbias_p = 341;
hw->qbias_en = 0;
memcpy(hw->aq_thrd_i, h264_aq_tthd_default, sizeof(hw->aq_thrd_i));
memcpy(hw->aq_thrd_p, h264_aq_tthd_default, sizeof(hw->aq_thrd_p));

6
mpp/hal/rkenc/h264e/hal_h264e_vepu580_tune.c
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@@ -124,6 +124,7 @@ static void vepu580_h264e_tune_reg_patch(void *p)
HalVepu580RegSet *regs = ctx->regs_set;
tune->ap_motion_flag = scene_mode;
RK_U32 scene_motion_flag = tune->ap_motion_flag * 2 + tune->curr_scene_motion_flag;
MppEncHwCfg *hw = &ctx->cfg->hw;
if (scene_motion_flag > 3) {
mpp_err_f("scene_motion_flag is a wrong value %d\n", scene_motion_flag);
@@ -212,6 +213,11 @@ static void vepu580_h264e_tune_reg_patch(void *p)
regs->reg_s3.rime_sqi_multi.rime_multi0 = rime_multi[scene_motion_flag][0];
regs->reg_s3.rime_sqi_multi.rime_multi1 = rime_multi[scene_motion_flag][1];
regs->reg_s3.rime_sqi_multi.rime_multi2 = rime_multi[scene_motion_flag][2];
if (hw->qbias_en) {
regs->reg_s3.RDO_QUANT.quant_f_bias_I = hw->qbias_i;
regs->reg_s3.RDO_QUANT.quant_f_bias_P = hw->qbias_p;
}
}
static void vepu580_h264e_tune_stat_update(void *p, HalEncTask *task)

7
mpp/hal/rkenc/h265e/hal_h265e_vepu540c.c
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@@ -449,6 +449,10 @@ static void vepu540c_h265_global_cfg_set(H265eV540cHalContext *ctx, H265eV540cRe
}
reg_wgt->reg1484_qnt_bias_comb.qnt_bias_i = 171;
reg_wgt->reg1484_qnt_bias_comb.qnt_bias_p = 85;
if (hw->qbias_en) {
reg_wgt->reg1484_qnt_bias_comb.qnt_bias_i = hw->qbias_i;
reg_wgt->reg1484_qnt_bias_comb.qnt_bias_p = hw->qbias_p;
}
/* CIME */
{
/* 0x1760 */
@@ -535,6 +539,9 @@ MPP_RET hal_h265e_v540c_init(void *hal, MppEncHalCfg *cfg)
hw->qp_delta_row_i = 2;
hw->qp_delta_row = 2;
hw->qbias_i = 171;
hw->qbias_p = 85;
hw->qbias_en = 0;
memcpy(hw->aq_thrd_i, aq_thd_default, sizeof(hw->aq_thrd_i));
memcpy(hw->aq_thrd_p, aq_thd_default, sizeof(hw->aq_thrd_p));

19
mpp/hal/rkenc/h265e/hal_h265e_vepu541.c
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@@ -122,8 +122,8 @@ static RK_U32 aq_thd_default[16] = {
static RK_S32 aq_qp_dealt_default[16] = {
-8, -7, -6, -5,
-4, -3, -2, -1,
0, 1, 2, 2,
3, 3, 4, 4,
0, 1, 2, 3,
4, 5, 7, 8,
};
static RK_U16 lvl32_intra_cst_thd[4] = {2, 6, 16, 36};
@@ -514,8 +514,8 @@ static void vepu541_h265_set_l2_regs(H265eV541HalContext *ctx, H265eV54xL2RegSet
memcpy(&regs->lvl16_intra_CST_THD0, lvl16_intra_cst_thd, sizeof(lvl16_intra_cst_thd));
memcpy(&regs->lvl32_intra_CST_WGT0, lvl32_intra_cst_wgt, sizeof(lvl32_intra_cst_wgt));
memcpy(&regs->lvl16_intra_CST_WGT0, lvl16_intra_cst_wgt, sizeof(lvl16_intra_cst_wgt));
regs->rdo_quant.quant_f_bias_I = 0;
regs->rdo_quant.quant_f_bias_P = 0;
regs->rdo_quant.quant_f_bias_I = 171;
regs->rdo_quant.quant_f_bias_P = 85;
memcpy(&regs->atr_thd0, atr_thd, sizeof(atr_thd));
memcpy(&regs->lvl16_atr_wgt, lvl16_4_atr_wgt, sizeof(lvl16_4_atr_wgt));
if (!ctx->is_vepu540) {
@@ -572,9 +572,6 @@ static void vepu541_h265_set_l2_regs(H265eV541HalContext *ctx, H265eV54xL2RegSet
thd[i] = hw->aq_thrd_i[i];
step[i] = hw->aq_step_i[i] & 0x3f;
}
regs->rdo_quant.quant_f_bias_I = 171;
regs->rdo_quant.quant_f_bias_P = 85;
} else {
RK_U8 *thd = (RK_U8 *)&regs->aq_thd0;
RK_S8 *step = (RK_S8 *)&regs->aq_qp_dlt0;
@@ -585,6 +582,11 @@ static void vepu541_h265_set_l2_regs(H265eV541HalContext *ctx, H265eV54xL2RegSet
}
}
if (hw->qbias_en) {
regs->rdo_quant.quant_f_bias_I = hw->qbias_i;
regs->rdo_quant.quant_f_bias_P = hw->qbias_p;
}
MppDevRegWrCfg cfg;
cfg.reg = regs;
if (ctx->is_vepu540) {
@@ -642,6 +644,9 @@ MPP_RET hal_h265e_v541_init(void *hal, MppEncHalCfg *cfg)
hw->qp_delta_row_i = 0;
hw->qp_delta_row = 1;
hw->qbias_i = 171;
hw->qbias_p = 85;
hw->qbias_en = 0;
memcpy(hw->aq_thrd_i, aq_thd_default, sizeof(hw->aq_thrd_i));
memcpy(hw->aq_thrd_p, aq_thd_default, sizeof(hw->aq_thrd_p));

3
mpp/hal/rkenc/h265e/hal_h265e_vepu580.c
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@@ -1449,6 +1449,9 @@ MPP_RET hal_h265e_v580_init(void *hal, MppEncHalCfg *cfg)
hw->qp_delta_row_i = 2;
hw->qp_delta_row = 2;
hw->qbias_i = 171;
hw->qbias_p = 85;
hw->qbias_en = 0;
memcpy(hw->aq_thrd_i, aq_thd_default, sizeof(hw->aq_thrd_i));
memcpy(hw->aq_thrd_p, aq_thd_default, sizeof(hw->aq_thrd_p));

6
mpp/hal/rkenc/h265e/hal_h265e_vepu580_tune.c
View File

@@ -247,6 +247,7 @@ static void vepu580_h265e_tune_reg_patch(void *p)
RdoAtfSkipCfg *p_rdo_atf_skip;
RdoAtfCfg* p_rdo_atf;
RK_U32 scene_motion_flag = tune->ap_motion_flag * 2 + tune->curr_scene_motion_flag;
MppEncHwCfg *hw = &ctx->cfg->hw;
if (scene_motion_flag > 3) {
mpp_err_f("scene_motion_flag is a wrong value %d\n", scene_motion_flag);
@@ -451,8 +452,13 @@ static void vepu580_h265e_tune_reg_patch(void *p)
reg_wgt->i32_sobel_c.intra_l32_sobel_c1_qp3 = intra_lvl32_sobel_c[scene_motion_flag][3];
reg_wgt->i32_sobel_c.intra_l32_sobel_c1_qp4 = intra_lvl32_sobel_c[scene_motion_flag][4];
if (hw->qbias_en) {
reg_wgt->reg1484_qnt_bias_comb.qnt_bias_i = hw->qbias_i;
reg_wgt->reg1484_qnt_bias_comb.qnt_bias_p = hw->qbias_p;
} else {
reg_wgt->reg1484_qnt_bias_comb.qnt_bias_i = qnt_bias_i[scene_motion_flag];
reg_wgt->reg1484_qnt_bias_comb.qnt_bias_p = qnt_bias_p[scene_motion_flag];
}
reg_wgt->rime_sqi_thd.cime_sad_th0 = rime_sqi_cime_sad_th[scene_motion_flag];
reg_wgt->fme_sqi_thd0.cime_sad_pu16_th = fme_sqi_cime_sad_pu16_th[scene_motion_flag];
reg_wgt->fme_sqi_thd0.cime_sad_pu32_th = fme_sqi_cime_sad_pu32_th[scene_motion_flag];