diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c b/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c
index 34e81cf8..e68530f6 100644
--- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c
+++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c
@@ -867,7 +867,7 @@ MPP_RET vdpu34x_h264d_gen_regs(void *hal, HalTaskInfo *task)
     regs->h264d_addr.scanlist_addr = mpp_buffer_get_fd(ctx->sclst_buf);
     regs->common.reg012.scanlist_addr_valid_en = 1;
     hal_h264d_rcb_info_update(p_hal, regs);
-    vdpu34x_setup_rcb(&regs->common_addr, ctx->rcb_buf, ctx->rcb_info);
+    vdpu34x_setup_rcb(&regs->common_addr, p_hal->dev, ctx->rcb_buf, ctx->rcb_info);
 
 __RETURN:
     return ret = MPP_OK;
diff --git a/mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c b/mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
index 819e5d19..4dbd56dd 100644
--- a/mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
+++ b/mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
@@ -1140,7 +1140,7 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal,  HalTaskInfo *syn)
     hw_regs->common.reg011.buf_empty_en = 1;
 
     hal_h265d_rcb_info_update(hal, dxva_cxt, hw_regs, width, height);
-    vdpu34x_setup_rcb(&hw_regs->common_addr, reg_cxt->rcb_buf, reg_cxt->rcb_info);
+    vdpu34x_setup_rcb(&hw_regs->common_addr, reg_cxt->dev, reg_cxt->rcb_buf, reg_cxt->rcb_info);
 
     return ret;
 }
diff --git a/mpp/hal/rkdec/inc/vdpu34x_com.h b/mpp/hal/rkdec/inc/vdpu34x_com.h
index c59eea69..ff2726df 100644
--- a/mpp/hal/rkdec/inc/vdpu34x_com.h
+++ b/mpp/hal/rkdec/inc/vdpu34x_com.h
@@ -17,7 +17,7 @@
 #ifndef __VDPU34X_COM_H__
 #define __VDPU34X_COM_H__
 
-#include "rk_type.h"
+#include "mpp_device.h"
 #include "vdpu34x.h"
 
 #define OFFSET_COMMON_REGS          (8 * sizeof(RK_U32))
@@ -423,7 +423,7 @@ extern "C" {
 #endif
 
 RK_S32 get_rcb_buf_size(Vdpu34xRcbInfo *info, RK_S32 width, RK_S32 height);
-void vdpu34x_setup_rcb(Vdpu34xRegCommonAddr *reg, MppBuffer buf, Vdpu34xRcbInfo *info);
+void vdpu34x_setup_rcb(Vdpu34xRegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdpu34xRcbInfo *info);
 RK_S32 vdpu34x_compare_rcb_size(const void *a, const void *b);
 void vdpu34x_setup_statistic(Vdpu34xRegCommon *com, Vdpu34xRegStatistic *sta);
 
diff --git a/mpp/hal/rkdec/vdpu34x_com.c b/mpp/hal/rkdec/vdpu34x_com.c
index f8705325..b8aa847d 100644
--- a/mpp/hal/rkdec/vdpu34x_com.c
+++ b/mpp/hal/rkdec/vdpu34x_com.c
@@ -69,20 +69,81 @@ RK_S32 get_rcb_buf_size(Vdpu34xRcbInfo *info, RK_S32 width, RK_S32 height)
     return offset;
 }
 
-void vdpu34x_setup_rcb(Vdpu34xRegCommonAddr *reg, MppBuffer buf, Vdpu34xRcbInfo *info)
+void vdpu34x_setup_rcb(Vdpu34xRegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdpu34xRcbInfo *info)
 {
+    MppDevRegOffsetCfg trans_cfg;
     RK_S32 fd = mpp_buffer_get_fd(buf);
 
-    reg->reg139_rcb_dblk_base           = fd + (info[RCB_DBLK_ROW].offset << 10);
-    reg->reg133_rcb_intra_base          = fd + (info[RCB_INTRA_ROW].offset << 10);
-    reg->reg134_rcb_transd_row_base     = fd + (info[RCB_TRANSD_ROW].offset << 10);
-    reg->reg136_rcb_streamd_row_base    = fd + (info[RCB_STRMD_ROW].offset << 10);
-    reg->reg137_rcb_inter_row_base      = fd + (info[RCB_INTER_ROW].offset << 10);
-    reg->reg140_rcb_sao_base            = fd + (info[RCB_SAO_ROW].offset << 10);
-    reg->reg141_rcb_fbc_base            = fd + (info[RCB_FBC_ROW].offset << 10);
-    reg->reg135_rcb_transd_col_base     = fd + (info[RCB_TRANSD_COL].offset << 10);
-    reg->reg138_rcb_inter_col_base      = fd + (info[RCB_INTER_COL].offset << 10);
-    reg->reg142_rcb_filter_col_base     = fd + (info[RCB_FILT_COL].offset << 10);
+    reg->reg139_rcb_dblk_base           = fd;
+    reg->reg133_rcb_intra_base          = fd;
+    reg->reg134_rcb_transd_row_base     = fd;
+    reg->reg136_rcb_streamd_row_base    = fd;
+    reg->reg137_rcb_inter_row_base      = fd;
+    reg->reg140_rcb_sao_base            = fd;
+    reg->reg141_rcb_fbc_base            = fd;
+    reg->reg135_rcb_transd_col_base     = fd;
+    reg->reg138_rcb_inter_col_base      = fd;
+    reg->reg142_rcb_filter_col_base     = fd;
+
+    if (info[RCB_DBLK_ROW].offset) {
+        trans_cfg.reg_idx = 139;
+        trans_cfg.offset = info[RCB_DBLK_ROW].offset;
+        mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
+    }
+
+    if (info[RCB_INTRA_ROW].offset) {
+        trans_cfg.reg_idx = 133;
+        trans_cfg.offset = info[RCB_INTRA_ROW].offset;
+        mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
+    }
+
+    if (info[RCB_TRANSD_ROW].offset) {
+        trans_cfg.reg_idx = 134;
+        trans_cfg.offset = info[RCB_TRANSD_ROW].offset;
+        mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
+    }
+
+    if (info[RCB_STRMD_ROW].offset) {
+        trans_cfg.reg_idx = 136;
+        trans_cfg.offset = info[RCB_STRMD_ROW].offset;
+        mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
+    }
+
+    if (info[RCB_INTER_ROW].offset) {
+        trans_cfg.reg_idx = 137;
+        trans_cfg.offset = info[RCB_INTER_ROW].offset;
+        mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
+    }
+
+    if (info[RCB_SAO_ROW].offset) {
+        trans_cfg.reg_idx = 140;
+        trans_cfg.offset = info[RCB_SAO_ROW].offset;
+        mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
+    }
+
+    if (info[RCB_FBC_ROW].offset) {
+        trans_cfg.reg_idx = 141;
+        trans_cfg.offset = info[RCB_FBC_ROW].offset;
+        mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
+    }
+
+    if (info[RCB_TRANSD_COL].offset) {
+        trans_cfg.reg_idx = 135;
+        trans_cfg.offset = info[RCB_TRANSD_COL].offset;
+        mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
+    }
+
+    if (info[RCB_INTER_COL].offset) {
+        trans_cfg.reg_idx = 138;
+        trans_cfg.offset = info[RCB_INTER_COL].offset;
+        mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
+    }
+
+    if (info[RCB_FILT_COL].offset) {
+        trans_cfg.reg_idx = 142;
+        trans_cfg.offset = info[RCB_FILT_COL].offset;
+        mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
+    }
 }
 
 RK_S32 vdpu34x_compare_rcb_size(const void *a, const void *b)
diff --git a/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu34x.c b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu34x.c
index 53ad99f9..cbd737bb 100644
--- a/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu34x.c
+++ b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu34x.c
@@ -768,7 +768,7 @@ static MPP_RET hal_vp9d_vdpu34x_gen_regs(void *hal, HalTaskInfo *task)
                      hw_ctx->ls_info.last_intra_only);
 
     hal_vp9d_rcb_info_update(hal, vp9_hw_regs, pic_param);
-    vdpu34x_setup_rcb(&vp9_hw_regs->common_addr, hw_ctx->rcb_buf, hw_ctx->rcb_info);
+    vdpu34x_setup_rcb(&vp9_hw_regs->common_addr, p_hal->dev, hw_ctx->rcb_buf, hw_ctx->rcb_info);
 
     // whether need update counts
     if (pic_param->refresh_frame_context && !pic_param->parallelmode) {