From 9c03426786ad77cc4f08be6ba965d2f23a898c4e Mon Sep 17 00:00:00 2001 From: "sayon.chen" Date: Mon, 13 Dec 2021 13:54:08 +0800 Subject: [PATCH] [vepu540c_hevc]: support hal_vepu 540c hevc reg cfg Signed-off-by: sayon.chen Signed-off-by: Chandler Chen Change-Id: Ia23ceef6d1f79dad2195bcb78dad7cd9a8c9f63e --- mpp/hal/common/h265/hal_h265e_api_v2.c | 4 + mpp/hal/rkenc/h265e/CMakeLists.txt | 1 + mpp/hal/rkenc/h265e/hal_h265e_vepu540c.c | 1605 ++++++++++++++++++ mpp/hal/rkenc/h265e/hal_h265e_vepu540c.h | 24 + mpp/hal/rkenc/h265e/hal_h265e_vepu540c_reg.h | 1159 +++++++++++++ 5 files changed, 2793 insertions(+) create mode 100644 mpp/hal/rkenc/h265e/hal_h265e_vepu540c.c create mode 100644 mpp/hal/rkenc/h265e/hal_h265e_vepu540c.h create mode 100644 mpp/hal/rkenc/h265e/hal_h265e_vepu540c_reg.h diff --git a/mpp/hal/common/h265/hal_h265e_api_v2.c b/mpp/hal/common/h265/hal_h265e_api_v2.c index 2316882a..164917d7 100644 --- a/mpp/hal/common/h265/hal_h265e_api_v2.c +++ b/mpp/hal/common/h265/hal_h265e_api_v2.c @@ -29,6 +29,7 @@ #include "hal_h265e_api_v2.h" #include "hal_h265e_vepu541.h" #include "hal_h265e_vepu580.h" +#include "hal_h265e_vepu540c.h" typedef struct HalH265eV2Ctx_t { const MppEncHalApi *api; @@ -52,6 +53,9 @@ static MPP_RET hal_h265ev2_init(void *hal, MppEncHalCfg *cfg) case HWID_VEPU58X : { api = &hal_h265e_vepu580; } break; + case HWID_VEPU540C : { + api = &hal_h265e_vepu540c; + } break; default : { api = &hal_h265e_vepu541; } break; diff --git a/mpp/hal/rkenc/h265e/CMakeLists.txt b/mpp/hal/rkenc/h265e/CMakeLists.txt index fe81bcc5..9c787f77 100644 --- a/mpp/hal/rkenc/h265e/CMakeLists.txt +++ b/mpp/hal/rkenc/h265e/CMakeLists.txt @@ -13,6 +13,7 @@ set(HAL_H265E_HDR set(HAL_H265E_SRC hal_h265e_vepu541.c hal_h265e_vepu580.c + hal_h265e_vepu540c.c ) add_library(hal_h265e_vepu541 STATIC diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu540c.c b/mpp/hal/rkenc/h265e/hal_h265e_vepu540c.c new file mode 100644 index 00000000..18414780 --- /dev/null +++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu540c.c @@ -0,0 +1,1605 @@ +/* + * Copyright 2022 Rockchip Electronics Co. LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define MODULE_TAG "hal_h265e_v540c" + +#include + +#include +#include +#include + +#include "mpp_env.h" +#include "mpp_mem.h" +#include "mpp_soc.h" +#include "mpp_common.h" +#include "mpp_frame_impl.h" + +#include "hal_h265e_debug.h" +#include "h265e_syntax_new.h" +#include "hal_bufs.h" +#include "rkv_enc_def.h" +#include "vepu541_common.h" +#include "vepu540c_common.h" +#include "hal_h265e_vepu540c.h" +#include "hal_h265e_vepu540c_reg.h" + +#define MAX_TITLE_NUM 2 + +#define hal_h265e_err(fmt, ...) \ + do {\ + mpp_err_f(fmt, ## __VA_ARGS__);\ + } while (0) + +typedef struct vepu540c_h265_fbk_t { + RK_U32 hw_status; /* 0:corret, 1:error */ + RK_U32 qp_sum; + RK_U32 out_strm_size; + RK_U32 out_hw_strm_size; + RK_S64 sse_sum; + RK_U32 st_lvl64_inter_num; + RK_U32 st_lvl32_inter_num; + RK_U32 st_lvl16_inter_num; + RK_U32 st_lvl8_inter_num; + RK_U32 st_lvl32_intra_num; + RK_U32 st_lvl16_intra_num; + RK_U32 st_lvl8_intra_num; + RK_U32 st_lvl4_intra_num; + RK_U32 st_cu_num_qp[52]; + RK_U32 st_madp; + RK_U32 st_madi; + RK_U32 st_mb_num; + RK_U32 st_ctu_num; +} vepu540c_h265_fbk; + +typedef struct H265eV540cHalContext_t { + MppEncHalApi api; + MppDev dev; + void *regs; + void *reg_out[MAX_TITLE_NUM]; + + vepu540c_h265_fbk feedback; + void *dump_files; + RK_U32 frame_cnt_gen_ready; + + RK_S32 frame_type; + RK_S32 last_frame_type; + + /* @frame_cnt starts from ZERO */ + RK_U32 frame_cnt; + void *roi_data; + MppEncCfgSet *cfg; + + MppBufferGroup tile_grp; + MppBuffer hw_tile_buf[2]; + + RK_U32 enc_mode; + RK_U32 frame_size; + RK_S32 max_buf_cnt; + RK_S32 hdr_status; + void *input_fmt; + RK_U8 *src_buf; + RK_U8 *dst_buf; + RK_S32 buf_size; + RK_U32 frame_num; + HalBufs dpb_bufs; + RK_S32 fbc_header_len; + RK_U32 title_num; +} H265eV540cHalContext; + +#define TILE_BUF_SIZE MPP_ALIGN(128 * 1024, 256) + +static RK_U32 aq_thd_default[16] = { + 0, 0, 0, 0, + 3, 3, 5, 5, + 8, 8, 8, 15, + 15, 20, 25, 35 +}; + +static RK_S32 aq_qp_dealt_default[16] = { + -8, -7, -6, -5, + -4, -3, -2, -1, + 0, 1, 2, 3, + 4, 5, 6, 8, +}; + +static RK_U32 lamd_moda_qp[52] = { + 0x00000049, 0x0000005c, 0x00000074, 0x00000092, 0x000000b8, 0x000000e8, 0x00000124, 0x00000170, + 0x000001cf, 0x00000248, 0x000002df, 0x0000039f, 0x0000048f, 0x000005bf, 0x0000073d, 0x0000091f, + 0x00000b7e, 0x00000e7a, 0x0000123d, 0x000016fb, 0x00001cf4, 0x0000247b, 0x00002df6, 0x000039e9, + 0x000048f6, 0x00005bed, 0x000073d1, 0x000091ec, 0x0000b7d9, 0x0000e7a2, 0x000123d7, 0x00016fb2, + 0x0001cf44, 0x000247ae, 0x0002df64, 0x00039e89, 0x00048f5c, 0x0005bec8, 0x00073d12, 0x00091eb8, + 0x000b7d90, 0x000e7a23, 0x00123d71, 0x0016fb20, 0x001cf446, 0x00247ae1, 0x002df640, 0x0039e88c, + 0x0048f5c3, 0x005bec81, 0x0073d119, 0x0091eb85 +}; + +static RK_U32 lamd_modb_qp[52] = { + 0x00000070, 0x00000089, 0x000000b0, 0x000000e0, 0x00000112, 0x00000160, 0x000001c0, 0x00000224, + 0x000002c0, 0x00000380, 0x00000448, 0x00000580, 0x00000700, 0x00000890, 0x00000b00, 0x00000e00, + 0x00001120, 0x00001600, 0x00001c00, 0x00002240, 0x00002c00, 0x00003800, 0x00004480, 0x00005800, + 0x00007000, 0x00008900, 0x0000b000, 0x0000e000, 0x00011200, 0x00016000, 0x0001c000, 0x00022400, + 0x0002c000, 0x00038000, 0x00044800, 0x00058000, 0x00070000, 0x00089000, 0x000b0000, 0x000e0000, + 0x00112000, 0x00160000, 0x001c0000, 0x00224000, 0x002c0000, 0x00380000, 0x00448000, 0x00580000, + 0x00700000, 0x00890000, 0x00b00000, 0x00e00000 +}; + +static MPP_RET vepu540c_h265_setup_hal_bufs(H265eV540cHalContext *ctx) +{ + MPP_RET ret = MPP_OK; + VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt; + RK_U32 frame_size; + Vepu541Fmt input_fmt = VEPU541_FMT_YUV420P; + RK_S32 mb_wd64, mb_h64; + MppEncRefCfg ref_cfg = ctx->cfg->ref_cfg; + MppEncPrepCfg *prep = &ctx->cfg->prep; + RK_S32 old_max_cnt = ctx->max_buf_cnt; + RK_S32 new_max_cnt = 2; + + hal_h265e_enter(); + + mb_wd64 = (prep->width + 63) / 64; + mb_h64 = (prep->height + 63) / 64; + + frame_size = MPP_ALIGN(prep->width, 16) * MPP_ALIGN(prep->height, 16); + vepu541_set_fmt(fmt, ctx->cfg->prep.format); + input_fmt = (Vepu541Fmt)fmt->format; + switch (input_fmt) { + case VEPU541_FMT_YUV420P: + case VEPU541_FMT_YUV420SP: { + frame_size = frame_size * 3 / 2; + } break; + case VEPU541_FMT_YUV422P: + case VEPU541_FMT_YUV422SP: + case VEPU541_FMT_YUYV422: + case VEPU541_FMT_UYVY422: + case VEPU541_FMT_BGR565: { + frame_size *= 2; + } break; + case VEPU541_FMT_BGR888: { + frame_size *= 3; + } break; + case VEPU541_FMT_BGRA8888: { + frame_size *= 4; + } break; + default: { + hal_h265e_err("invalid src color space: %d\n", input_fmt); + return MPP_NOK; + } + } + + if (ref_cfg) { + MppEncCpbInfo *info = mpp_enc_ref_cfg_get_cpb_info(ref_cfg); + new_max_cnt = MPP_MAX(new_max_cnt, info->dpb_size + 1); + } + + if (frame_size > ctx->frame_size || new_max_cnt > old_max_cnt) { + size_t size[3] = {0}; + + hal_bufs_deinit(ctx->dpb_bufs); + hal_bufs_init(&ctx->dpb_bufs); + + ctx->fbc_header_len = MPP_ALIGN(((mb_wd64 * mb_h64) << 6), SZ_8K); + size[0] = ctx->fbc_header_len + ((mb_wd64 * mb_h64) << 12) * 3 / 2; //fbc_h + fbc_b + size[1] = (mb_wd64 * mb_h64 << 8); + size[2] = MPP_ALIGN(mb_wd64 * mb_h64 * 16 * 4, 256) * 16; + new_max_cnt = MPP_MAX(new_max_cnt, old_max_cnt); + + hal_h265e_dbg_detail("frame size %d -> %d max count %d -> %d\n", + ctx->frame_size, frame_size, old_max_cnt, new_max_cnt); + + hal_bufs_setup(ctx->dpb_bufs, new_max_cnt, 3, size); + + ctx->frame_size = frame_size; + ctx->max_buf_cnt = new_max_cnt; + } + hal_h265e_leave(); + return ret; +} + +static void vepu540c_h265_rdo_cfg (vepu540c_rdo_cfg *reg) +{ + rdo_skip_par *p_rdo_skip = NULL; + rdo_noskip_par *p_rdo_noskip = NULL; + pre_cst_par *p_pre_cst = NULL; + + reg->rdo_segment_cfg.rdo_segment_multi = 0; + reg->rdo_segment_cfg.rdo_segment_en = 0; + reg->rdo_smear_cfg_comb.rdo_smear_en = 0; + reg->rdo_smear_cfg_comb.rdo_smear_lvl16_multi = 12; + reg->rdo_segment_cfg.rdo_smear_lvl8_multi = 10; + reg->rdo_segment_cfg.rdo_smear_lvl4_multi = 8 ; + reg->rdo_smear_cfg_comb.rdo_smear_dlt_qp = 0 ; + reg->rdo_smear_cfg_comb.rdo_smear_order_state = 0; + reg->rdo_smear_cfg_comb.stated_mode = 0; + reg->rdo_smear_cfg_comb.online_en = 0; + reg->rdo_smear_cfg_comb.smear_stride = 0; + reg->rdo_smear_madp_thd0_comb.rdo_smear_madp_cur_thd0 = 0 ; + reg->rdo_smear_madp_thd0_comb.rdo_smear_madp_cur_thd1 = 24; + reg->rdo_smear_madp_thd1_comb.rdo_smear_madp_cur_thd2 = 48; + reg->rdo_smear_madp_thd1_comb.rdo_smear_madp_cur_thd3 = 64; + reg->rdo_smear_madp_thd2_comb.rdo_smear_madp_around_thd0 = 16; + reg->rdo_smear_madp_thd2_comb.rdo_smear_madp_around_thd1 = 32; + reg->rdo_smear_madp_thd3_comb.rdo_smear_madp_around_thd2 = 48; + reg->rdo_smear_madp_thd3_comb.rdo_smear_madp_around_thd3 = 96; + reg->rdo_smear_madp_thd4_comb.rdo_smear_madp_around_thd4 = 48; + reg->rdo_smear_madp_thd4_comb.rdo_smear_madp_around_thd5 = 24; + reg->rdo_smear_madp_thd5_comb.rdo_smear_madp_ref_thd0 = 96; + reg->rdo_smear_madp_thd5_comb.rdo_smear_madp_ref_thd1 = 48; + reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd0 = 1 ; + reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd1 = 4 ; + reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd2 = 1 ; + reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd3 = 4 ; + reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd0 = 1 ; + reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd1 = 4 ; + reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd2 = 1 ; + reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd3 = 4 ; + reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd4 = 1 ; + reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd5 = 4 ; + reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd6 = 1 ; + reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd7 = 4 ; + reg->rdo_smear_cnt_thd3_comb.rdo_smear_cnt_ref_thd0 = 1 ; + reg->rdo_smear_cnt_thd3_comb.rdo_smear_cnt_ref_thd1 = 4 ; + reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_small_cur_th0 = 6; + reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_big_cur_th0 = 8; + reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_small_cur_th1 = 6; + reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_big_cur_th1 = 11; + reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_small_around_th0 = 6; + reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_big_around_th0 = 8; + reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_small_around_th1 = 6; + reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_big_around_th1 = 11; + reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_small_around_th2 = 9; + reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_big_around_th2 = 20; + reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_small_around_th3 = 9; + reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_big_around_th3 = 20; + reg->rdo_smear_resi_thd3_comb.rdo_smear_resi_small_ref_th0 = 9; + reg->rdo_smear_resi_thd3_comb.rdo_smear_resi_big_ref_th0 = 20; + reg->rdo_smear_st_thd0_comb.rdo_smear_resi_th0 = 12; + reg->rdo_smear_st_thd0_comb.rdo_smear_resi_th1 = 12; + reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th0 = 1; + reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th1 = 2; + reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th2 = 1; + reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th3 = 2; + reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th4 = 1; + reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th5 = 2; + + p_rdo_skip = ®->rdo_b32_skip; + p_rdo_skip->atf_thd0.madp_thd0 = 5 ; + p_rdo_skip->atf_thd0.madp_thd1 = 10 ; + p_rdo_skip->atf_thd1.madp_thd2 = 15 ; + p_rdo_skip->atf_thd1.madp_thd3 = 25 ; + p_rdo_skip->atf_wgt0.wgt0 = 14 ; + p_rdo_skip->atf_wgt0.wgt1 = 15 ; + p_rdo_skip->atf_wgt0.wgt2 = 16 ; + p_rdo_skip->atf_wgt0.wgt3 = 16 ; + p_rdo_skip->atf_wgt1.wgt4 = 20 ; + + p_rdo_noskip = ®->rdo_b32_inter; + p_rdo_noskip->ratf_thd0.madp_thd0 = 20; + p_rdo_noskip->ratf_thd0.madp_thd1 = 40; + p_rdo_noskip->ratf_thd1.madp_thd2 = 72; + p_rdo_noskip->atf_wgt.wgt0 = 16; + p_rdo_noskip->atf_wgt.wgt1 = 16; + p_rdo_noskip->atf_wgt.wgt2 = 16; + p_rdo_noskip->atf_wgt.wgt3 = 16; + + p_rdo_noskip = ®->rdo_b32_intra; + p_rdo_noskip->ratf_thd0.madp_thd0 = 20; + p_rdo_noskip->ratf_thd0.madp_thd1 = 40; + p_rdo_noskip->ratf_thd1.madp_thd2 = 72; + p_rdo_noskip->atf_wgt.wgt0 = 27; + p_rdo_noskip->atf_wgt.wgt1 = 25; + p_rdo_noskip->atf_wgt.wgt2 = 20; + p_rdo_noskip->atf_wgt.wgt3 = 16; + + p_rdo_skip = ®->rdo_b16_skip; + p_rdo_skip->atf_thd0.madp_thd0 = 5 ; + p_rdo_skip->atf_thd0.madp_thd1 = 10 ; + p_rdo_skip->atf_thd1.madp_thd2 = 15 ; + p_rdo_skip->atf_thd1.madp_thd3 = 25 ; + p_rdo_skip->atf_wgt0.wgt0 = 20 ; + p_rdo_skip->atf_wgt0.wgt1 = 14 ; + p_rdo_skip->atf_wgt0.wgt2 = 15 ; + p_rdo_skip->atf_wgt0.wgt3 = 16 ; + p_rdo_skip->atf_wgt1.wgt4 = 16 ; + + p_rdo_noskip = ®->rdo_b16_inter; + p_rdo_noskip->ratf_thd0.madp_thd0 = 20; + p_rdo_noskip->ratf_thd0.madp_thd1 = 40; + p_rdo_noskip->ratf_thd1.madp_thd2 = 72; + p_rdo_noskip->atf_wgt.wgt0 = 16; + p_rdo_noskip->atf_wgt.wgt1 = 16; + p_rdo_noskip->atf_wgt.wgt2 = 16; + p_rdo_noskip->atf_wgt.wgt3 = 16; + + p_rdo_noskip = ®->rdo_b16_intra; + p_rdo_noskip->ratf_thd0.madp_thd0 = 20; + p_rdo_noskip->ratf_thd0.madp_thd1 = 40; + p_rdo_noskip->ratf_thd1.madp_thd2 = 72; + p_rdo_noskip->atf_wgt.wgt0 = 27; + p_rdo_noskip->atf_wgt.wgt1 = 25; + p_rdo_noskip->atf_wgt.wgt2 = 20; + p_rdo_noskip->atf_wgt.wgt3 = 16; + + reg->rdo_b32_intra_atf_cnt_thd.thd0 = 14 ; + reg->rdo_b32_intra_atf_cnt_thd.thd1 = 15 ; + reg->rdo_b32_intra_atf_cnt_thd.thd2 = 16 ; + reg->rdo_b32_intra_atf_cnt_thd.thd3 = 17 ; + + reg->rdo_b16_intra_atf_cnt_thd_comb.thd0 = 8 ; + reg->rdo_b16_intra_atf_cnt_thd_comb.thd1 = 9 ; + reg->rdo_b16_intra_atf_cnt_thd_comb.thd2 = 10 ; + reg->rdo_b16_intra_atf_cnt_thd_comb.thd3 = 11 ; + reg->rdo_atf_resi_thd_comb.big_th0 = 10; + reg->rdo_atf_resi_thd_comb.big_th1 = 12; + reg->rdo_atf_resi_thd_comb.small_th0 = 11; + reg->rdo_atf_resi_thd_comb.small_th1 = 13; + + p_pre_cst = ®->preintra32_cst; + p_pre_cst->cst_madi_thd0.madi_thd0 = 2 ; + p_pre_cst->cst_madi_thd0.madi_thd1 = 6 ; + p_pre_cst->cst_madi_thd0.madi_thd2 = 16 ; + p_pre_cst->cst_madi_thd0.madi_thd3 = 36 ; + p_pre_cst->cst_madi_thd1.madi_thd4 = 16 ; + p_pre_cst->cst_madi_thd1.madi_thd5 = 16 ; + p_pre_cst->cst_wgt0.wgt0 = 16 ; + p_pre_cst->cst_wgt0.wgt1 = 16 ; + p_pre_cst->cst_wgt0.wgt2 = 16 ; + p_pre_cst->cst_wgt0.wgt3 = 16 ; + p_pre_cst->cst_wgt1.wgt4 = 16 ; + p_pre_cst->cst_wgt1.wgt5 = 16 ; + p_pre_cst->cst_wgt1.wgt6 = 16 ; + p_pre_cst->cst_wgt1.wgt7 = 16 ; + p_pre_cst->cst_wgt2.wgt8 = 16 ; + p_pre_cst->cst_wgt2.wgt9 = 16 ; + p_pre_cst->cst_wgt2.mode_th = 5 ; + + p_pre_cst = ®->preintra16_cst; + p_pre_cst->cst_madi_thd0.madi_thd0 = 2 ; + p_pre_cst->cst_madi_thd0.madi_thd1 = 6 ; + p_pre_cst->cst_madi_thd0.madi_thd2 = 16; + p_pre_cst->cst_madi_thd0.madi_thd3 = 36; + p_pre_cst->cst_madi_thd1.madi_thd4 = 16; + p_pre_cst->cst_madi_thd1.madi_thd5 = 16; + p_pre_cst->cst_wgt0.wgt0 = 16; + p_pre_cst->cst_wgt0.wgt1 = 16; + p_pre_cst->cst_wgt0.wgt2 = 16; + p_pre_cst->cst_wgt0.wgt3 = 16; + p_pre_cst->cst_wgt1.wgt4 = 16; + p_pre_cst->cst_wgt1.wgt5 = 16; + p_pre_cst->cst_wgt1.wgt6 = 16; + p_pre_cst->cst_wgt1.wgt7 = 16; + p_pre_cst->cst_wgt2.wgt8 = 16; + p_pre_cst->cst_wgt2.wgt9 = 16; + p_pre_cst->cst_wgt2.mode_th = 5 ; + + reg->preintra_sqi_cfg.pre_intra_qp_thd = 18; + reg->preintra_sqi_cfg.pre_intra4_lambda_mv_bit = 3; + reg->preintra_sqi_cfg.pre_intra8_lambda_mv_bit = 3; + reg->preintra_sqi_cfg.pre_intra16_lambda_mv_bit = 3; + reg->preintra_sqi_cfg.pre_intra32_lambda_mv_bit = 3; + reg->rdo_atr_i_cu32_madi_cfg0.i_cu32_madi_thd0 = 1; + reg->rdo_atr_i_cu32_madi_cfg0.i_cu32_madi_thd1 = 1; + reg->rdo_atr_i_cu32_madi_cfg0.i_cu32_madi_thd2 = 1; + reg->rdo_atr_i_cu32_madi_cfg1.i_cu32_madi_cnt_thd3 = 1; + reg->rdo_atr_i_cu32_madi_cfg1.i_cu32_madi_thd4 = 1; + reg->rdo_atr_i_cu32_madi_cfg1.i_cu32_madi_cost_multi = 16; + reg->rdo_atr_i_cu16_madi_cfg0.i_cu16_madi_thd0 = 1; + reg->rdo_atr_i_cu16_madi_cfg0.i_cu16_madi_thd1 = 1; + reg->rdo_atr_i_cu16_madi_cfg0.i_cu16_madi_cost_multi = 16; + +} + +static void vepu540c_h265_global_cfg_set(H265eV540cHalContext *ctx, H265eV540cRegSet *regs) +{ + MppEncHwCfg *hw = &ctx->cfg->hw; + RK_U32 i; + hevc_vepu540c_rc_roi *rc_regs = ®s->reg_rc_roi; + hevc_vepu540c_wgt *reg_wgt = ®s->reg_wgt; + vepu540c_rdo_cfg *reg_rdo = ®s->reg_rdo; + vepu540c_h265_rdo_cfg(reg_rdo); + + if (ctx->frame_type == INTRA_FRAME) { + RK_U8 *thd = (RK_U8 *)&rc_regs->aq_tthd0; + RK_S8 *step = (RK_S8 *)&rc_regs->aq_stp0; + + for (i = 0; i < MPP_ARRAY_ELEMS(aq_thd_default); i++) { + thd[i] = hw->aq_thrd_i[i]; + step[i] = hw->aq_step_i[i] & 0x3f; + } + reg_wgt->iprd_lamb_satd_ofst.lambda_satd_offset = 3; + memcpy(®_wgt->rdo_wgta_qp_grpa_0_51[0], lamd_moda_qp, sizeof(lamd_moda_qp)); + } else { + RK_U8 *thd = (RK_U8 *)&rc_regs->aq_tthd0; + RK_S8 *step = (RK_S8 *)&rc_regs->aq_stp0; + for (i = 0; i < MPP_ARRAY_ELEMS(aq_thd_default); i++) { + thd[i] = hw->aq_thrd_p[i]; + step[i] = hw->aq_step_p[i] & 0x3f; + } + reg_wgt->iprd_lamb_satd_ofst.lambda_satd_offset = 3; + memcpy(®_wgt->rdo_wgta_qp_grpa_0_51[0], lamd_modb_qp, sizeof(lamd_modb_qp)); + } + reg_wgt->reg1484_qnt_bias_comb.qnt_bias_i = 171; + reg_wgt->reg1484_qnt_bias_comb.qnt_bias_p = 85; + /* CIME */ + { + /* 0x1760 */ + regs->reg_wgt.me_sqi_cfg.cime_pmv_num = 1; + regs->reg_wgt.me_sqi_cfg.cime_fuse = 1; + regs->reg_wgt.me_sqi_cfg.itp_mode = 1; + regs->reg_wgt.me_sqi_cfg.move_lambda = 1; + regs->reg_wgt.me_sqi_cfg.rime_lvl_mrg = 1; + regs->reg_wgt.me_sqi_cfg.rime_prelvl_en = 0; + regs->reg_wgt.me_sqi_cfg.rime_prersu_en = 0; + + /* 0x1764 */ + regs->reg_wgt.cime_mvd_th.cime_mvd_th0 = 50; + regs->reg_wgt.cime_mvd_th.cime_mvd_th1 = 511; + regs->reg_wgt.cime_mvd_th.cime_mvd_th2 = 0; + + /* 0x1768 */ + regs->reg_wgt.cime_madp_th.cime_madp_th = 160; + + /* 0x176c */ + regs->reg_wgt.cime_multi.cime_multi0 = 192; + regs->reg_wgt.cime_multi.cime_multi1 = 255; + regs->reg_wgt.cime_multi.cime_multi2 = 0; + regs->reg_wgt.cime_multi.cime_multi3 = 15; + } + + /* RIME && FME */ + { + /* 0x1770 */ + regs->reg_wgt.rime_mvd_th.rime_mvd_th0 = 0; + regs->reg_wgt.rime_mvd_th.rime_mvd_th1 = 1; + regs->reg_wgt.rime_mvd_th.fme_madp_th = 0; + + /* 0x1774 */ + regs->reg_wgt.rime_madp_th.rime_madp_th0 = 192; + regs->reg_wgt.rime_madp_th.rime_madp_th1 = 1023; + + /* 0x1778 */ + regs->reg_wgt.rime_multi.rime_multi0 = 16; + regs->reg_wgt.rime_multi.rime_multi1 = 16; + regs->reg_wgt.rime_multi.rime_multi2 = 128; + + /* 0x177C */ + regs->reg_wgt.cmv_st_th.cmv_th0 = 64; + regs->reg_wgt.cmv_st_th.cmv_th1 = 96; + regs->reg_wgt.cmv_st_th.cmv_th2 = 128; + } +} + +MPP_RET hal_h265e_v540c_init(void *hal, MppEncHalCfg *cfg) +{ + MPP_RET ret = MPP_OK; + H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal; + RK_U32 i = 0; + + mpp_env_get_u32("hal_h265e_debug", &hal_h265e_debug, 0); + + hal_h265e_enter(); + + for ( i = 0; i < MAX_TITLE_NUM; i++) { + ctx->reg_out[i] = mpp_calloc(H265eV540cStatusElem, 1); + } + + ctx->regs = mpp_calloc(H265eV540cRegSet, 1); + ctx->input_fmt = mpp_calloc(VepuFmtCfg, 1); + ctx->cfg = cfg->cfg; + hal_bufs_init(&ctx->dpb_bufs); + + ctx->frame_cnt = 0; + ctx->frame_cnt_gen_ready = 0; + ctx->enc_mode = 1; + cfg->type = VPU_CLIENT_RKVENC; + ret = mpp_dev_init(&cfg->dev, cfg->type); + if (ret) { + mpp_err_f("mpp_dev_init failed. ret: %d\n", ret); + return ret; + } + + ctx->dev = cfg->dev; + ctx->frame_type = INTRA_FRAME; + + { /* setup default hardware config */ + MppEncHwCfg *hw = &cfg->cfg->hw; + + hw->qp_delta_row_i = 2; + hw->qp_delta_row = 2; + + memcpy(hw->aq_thrd_i, aq_thd_default, sizeof(hw->aq_thrd_i)); + memcpy(hw->aq_thrd_p, aq_thd_default, sizeof(hw->aq_thrd_p)); + memcpy(hw->aq_step_i, aq_qp_dealt_default, sizeof(hw->aq_step_i)); + memcpy(hw->aq_step_p, aq_qp_dealt_default, sizeof(hw->aq_step_p)); + } + + hal_h265e_leave(); + return ret; +} + +MPP_RET hal_h265e_v540c_deinit(void *hal) +{ + H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal; + RK_U32 i = 0; + + hal_h265e_enter(); + MPP_FREE(ctx->regs); + + for ( i = 0; i < MAX_TITLE_NUM; i++) { + MPP_FREE(ctx->reg_out[i]); + } + + MPP_FREE(ctx->input_fmt); + hal_bufs_deinit(ctx->dpb_bufs); + + if (ctx->hw_tile_buf[0]) { + mpp_buffer_put(ctx->hw_tile_buf[0]); + ctx->hw_tile_buf[0] = NULL; + } + + if (ctx->hw_tile_buf[1]) { + mpp_buffer_put(ctx->hw_tile_buf[1]); + ctx->hw_tile_buf[1] = NULL; + } + + if (ctx->dev) { + mpp_dev_deinit(ctx->dev); + ctx->dev = NULL; + } + hal_h265e_leave(); + return MPP_OK; +} + +static MPP_RET hal_h265e_vepu540c_prepare(void *hal) +{ + H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal; + MppEncPrepCfg *prep = &ctx->cfg->prep; + + hal_h265e_dbg_func("enter %p\n", hal); + + if (prep->change & (MPP_ENC_PREP_CFG_CHANGE_INPUT | MPP_ENC_PREP_CFG_CHANGE_FORMAT)) { + RK_S32 i; + + // pre-alloc required buffers to reduce first frame delay + vepu540c_h265_setup_hal_bufs(ctx); + for (i = 0; i < ctx->max_buf_cnt; i++) + hal_bufs_get_buf(ctx->dpb_bufs, i); + + prep->change = 0; + } + + hal_h265e_dbg_func("leave %p\n", hal); + + return MPP_OK; +} + +static MPP_RET +vepu540c_h265_set_patch_info(MppDev dev, H265eSyntax_new *syn, Vepu541Fmt input_fmt, HalEncTask *task) +{ + MppDevRegOffsetCfg cfg_fd; + RK_U32 hor_stride = syn->pp.hor_stride; + RK_U32 ver_stride = syn->pp.ver_stride ? syn->pp.ver_stride : syn->pp.pic_height; + RK_U32 frame_size = hor_stride * ver_stride; + RK_U32 u_offset = 0, v_offset = 0; + MPP_RET ret = MPP_OK; + + + if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(task->frame))) { + u_offset = mpp_frame_get_fbc_offset(task->frame); + v_offset = 0; + mpp_log("fbc case u_offset = %d", u_offset); + } else { + switch (input_fmt) { + case VEPU541_FMT_YUV420P: { + u_offset = frame_size; + v_offset = frame_size * 5 / 4; + } break; + case VEPU541_FMT_YUV420SP: + case VEPU541_FMT_YUV422SP: { + u_offset = frame_size; + v_offset = frame_size; + } break; + case VEPU541_FMT_YUV422P: { + u_offset = frame_size; + v_offset = frame_size * 3 / 2; + } break; + case VEPU541_FMT_YUYV422: + case VEPU541_FMT_UYVY422: { + u_offset = 0; + v_offset = 0; + } break; + case VEPU541_FMT_BGR565: + case VEPU541_FMT_BGR888: + case VEPU541_FMT_BGRA8888: { + u_offset = 0; + v_offset = 0; + } break; + default: { + hal_h265e_err("unknown color space: %d\n", input_fmt); + u_offset = frame_size; + v_offset = frame_size * 5 / 4; + } + } + } + + /* input cb addr */ + if (u_offset) { + cfg_fd.reg_idx = 161; + cfg_fd.offset = u_offset; + ret = mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &cfg_fd); + if (ret) + mpp_err_f("set input cb addr offset failed %d\n", ret); + } + + /* input cr addr */ + if (v_offset) { + cfg_fd.reg_idx = 162; + cfg_fd.offset = v_offset; + ret = mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &cfg_fd); + if (ret) + mpp_err_f("set input cr addr offset failed %d\n", ret); + } + + return ret; +} + + +#if 0 +static MPP_RET vepu540c_h265_set_roi_regs(H265eV540cHalContext *ctx, hevc_vepu540c_base *regs) +{ + /* memset register on start so do not clear registers again here */ + if (ctx->roi_data) { + /* roi setup */ + MppEncROICfg2 *cfg = ( MppEncROICfg2 *)ctx->roi_data; + + regs->reg0192_enc_pic.roi_en = 1; + regs->reg0178_roi_addr = mpp_dev_get_iova_address(ctx->dev, cfg->base_cfg_buf, 0); + if (cfg->roi_qp_en) { + regs->reg0179_roi_qp_addr = mpp_dev_get_iova_address(ctx->dev, cfg->qp_cfg_buf, 0); + regs->reg0228_roi_en.roi_qp_en = 1; + } + + if (cfg->roi_amv_en) { + regs->reg0180_roi_amv_addr = mpp_dev_get_iova_address(ctx->dev, cfg->amv_cfg_buf, 0); + regs->reg0228_roi_en.roi_amv_en = 1; + } + + if (cfg->roi_mv_en) { + regs->reg0181_roi_mv_addr = mpp_dev_get_iova_address(ctx->dev, cfg->mv_cfg_buf, 0); + regs->reg0228_roi_en.roi_mv_en = 1; + } + } + + return MPP_OK; +} +#endif + +static MPP_RET vepu540c_h265_set_rc_regs(H265eV540cHalContext *ctx, H265eV540cRegSet *regs, HalEncTask *task) +{ + H265eSyntax_new *syn = (H265eSyntax_new *)task->syntax.data; + EncRcTaskInfo *rc_cfg = &task->rc_task->info; + hevc_vepu540c_base *reg_base = ®s->reg_base; + hevc_vepu540c_rc_roi *reg_rc = ®s->reg_rc_roi; + MppEncCfgSet *cfg = ctx->cfg; + MppEncRcCfg *rc = &cfg->rc; + MppEncHwCfg *hw = &cfg->hw; + MppEncCodecCfg *codec = &cfg->codec; + MppEncH265Cfg *h265 = &codec->h265; + RK_S32 mb_wd64 = (syn->pp.pic_width + 63) / 64; + RK_S32 mb_h64 = (syn->pp.pic_height + 63) / 64; + + RK_U32 ctu_target_bits_mul_16 = (rc_cfg->bit_target << 4) / (mb_wd64 * mb_h64); + RK_U32 ctu_target_bits; + RK_S32 negative_bits_thd, positive_bits_thd; + + if (rc->rc_mode == MPP_ENC_RC_MODE_FIXQP) { + reg_base->reg0192_enc_pic.pic_qp = rc_cfg->quality_target; + reg_base->reg0240_synt_sli1.sli_qp = rc_cfg->quality_target; + + reg_base->reg213_rc_qp.rc_max_qp = rc_cfg->quality_target; + reg_base->reg213_rc_qp.rc_min_qp = rc_cfg->quality_target; + } else { + if (ctu_target_bits_mul_16 >= 0x100000) { + ctu_target_bits_mul_16 = 0x50000; + } + ctu_target_bits = (ctu_target_bits_mul_16 * mb_wd64) >> 4; + negative_bits_thd = 0 - 5 * ctu_target_bits / 16; + positive_bits_thd = 5 * ctu_target_bits / 16; + + reg_base->reg0192_enc_pic.pic_qp = rc_cfg->quality_target; + reg_base->reg0240_synt_sli1.sli_qp = rc_cfg->quality_target; + reg_base->reg212_rc_cfg.rc_en = 1; + reg_base->reg212_rc_cfg.aq_en = 1; + reg_base->reg212_rc_cfg.aq_mode = 1; + reg_base->reg212_rc_cfg.rc_ctu_num = mb_wd64; + reg_base->reg213_rc_qp.rc_qp_range = (ctx->frame_type == INTRA_FRAME) ? + hw->qp_delta_row_i : hw->qp_delta_row; + reg_base->reg213_rc_qp.rc_max_qp = rc_cfg->quality_max; + reg_base->reg213_rc_qp.rc_min_qp = rc_cfg->quality_min; + reg_base->reg214_rc_tgt.ctu_ebit = ctu_target_bits_mul_16; + + reg_rc->rc_dthd_0_8[0] = 2 * negative_bits_thd; + reg_rc->rc_dthd_0_8[1] = negative_bits_thd; + reg_rc->rc_dthd_0_8[2] = positive_bits_thd; + reg_rc->rc_dthd_0_8[3] = 2 * positive_bits_thd; + reg_rc->rc_dthd_0_8[4] = 0x7FFFFFFF; + reg_rc->rc_dthd_0_8[5] = 0x7FFFFFFF; + reg_rc->rc_dthd_0_8[6] = 0x7FFFFFFF; + reg_rc->rc_dthd_0_8[7] = 0x7FFFFFFF; + reg_rc->rc_dthd_0_8[8] = 0x7FFFFFFF; + + reg_rc->rc_adj0.qp_adj0 = -2; + reg_rc->rc_adj0.qp_adj1 = -1; + reg_rc->rc_adj0.qp_adj2 = 0; + reg_rc->rc_adj0.qp_adj3 = 1; + reg_rc->rc_adj0.qp_adj4 = 2; + reg_rc->rc_adj1.qp_adj5 = 0; + reg_rc->rc_adj1.qp_adj6 = 0; + reg_rc->rc_adj1.qp_adj7 = 0; + reg_rc->rc_adj1.qp_adj8 = 0; + + reg_rc->roi_qthd0.qpmin_area0 = h265->qpmin_map[0] > 0 ? h265->qpmin_map[0] : rc_cfg->quality_min; + reg_rc->roi_qthd0.qpmax_area0 = h265->qpmax_map[0] > 0 ? h265->qpmax_map[0] : rc_cfg->quality_max; + reg_rc->roi_qthd0.qpmin_area1 = h265->qpmin_map[1] > 0 ? h265->qpmin_map[1] : rc_cfg->quality_min; + reg_rc->roi_qthd0.qpmax_area1 = h265->qpmax_map[1] > 0 ? h265->qpmax_map[1] : rc_cfg->quality_max; + reg_rc->roi_qthd0.qpmin_area2 = h265->qpmin_map[2] > 0 ? h265->qpmin_map[2] : rc_cfg->quality_min;; + reg_rc->roi_qthd1.qpmax_area2 = h265->qpmax_map[2] > 0 ? h265->qpmax_map[2] : rc_cfg->quality_max; + reg_rc->roi_qthd1.qpmin_area3 = h265->qpmin_map[3] > 0 ? h265->qpmin_map[3] : rc_cfg->quality_min;; + reg_rc->roi_qthd1.qpmax_area3 = h265->qpmax_map[3] > 0 ? h265->qpmax_map[3] : rc_cfg->quality_max; + reg_rc->roi_qthd1.qpmin_area4 = h265->qpmin_map[4] > 0 ? h265->qpmin_map[4] : rc_cfg->quality_min;; + reg_rc->roi_qthd1.qpmax_area4 = h265->qpmax_map[4] > 0 ? h265->qpmax_map[4] : rc_cfg->quality_max; + reg_rc->roi_qthd2.qpmin_area5 = h265->qpmin_map[5] > 0 ? h265->qpmin_map[5] : rc_cfg->quality_min;; + reg_rc->roi_qthd2.qpmax_area5 = h265->qpmax_map[5] > 0 ? h265->qpmax_map[5] : rc_cfg->quality_max; + reg_rc->roi_qthd2.qpmin_area6 = h265->qpmin_map[6] > 0 ? h265->qpmin_map[6] : rc_cfg->quality_min;; + reg_rc->roi_qthd2.qpmax_area6 = h265->qpmax_map[6] > 0 ? h265->qpmax_map[6] : rc_cfg->quality_max; + reg_rc->roi_qthd2.qpmin_area7 = h265->qpmin_map[7] > 0 ? h265->qpmin_map[7] : rc_cfg->quality_min;; + reg_rc->roi_qthd3.qpmax_area7 = h265->qpmax_map[7] > 0 ? h265->qpmax_map[7] : rc_cfg->quality_max; + reg_rc->roi_qthd3.qpmap_mode = h265->qpmap_mode; + } + return MPP_OK; +} + +static MPP_RET vepu540c_h265_set_pp_regs(H265eV540cRegSet *regs, VepuFmtCfg *fmt, MppEncPrepCfg *prep_cfg) +{ + hevc_vepu540c_control_cfg *reg_ctl = ®s->reg_ctl; + hevc_vepu540c_base *reg_base = ®s->reg_base; + RK_S32 stridey = 0; + RK_S32 stridec = 0; + + reg_ctl->reg0012_dtrns_map.src_bus_edin = fmt->src_endian; + reg_base->reg0198_src_fmt.src_cfmt = fmt->format; + +// reg_base->reg0198_src_fmt.src_range = fmt->src_range; + reg_base->reg0198_src_fmt.out_fmt = 1; + + reg_base->reg0203_src_proc.src_mirr = prep_cfg->mirroring > 0; + reg_base->reg0203_src_proc.src_rot = prep_cfg->rotation; + + if (prep_cfg->hor_stride) { + stridey = prep_cfg->hor_stride; + } else { + if (reg_base->reg0198_src_fmt.src_cfmt == VEPU541_FMT_BGRA8888 ) + stridey = prep_cfg->width * 4; + else if (reg_base->reg0198_src_fmt.src_cfmt == VEPU541_FMT_BGR888 ) + stridey = prep_cfg->width * 3; + else if (reg_base->reg0198_src_fmt.src_cfmt == VEPU541_FMT_BGR565 || + reg_base->reg0198_src_fmt.src_cfmt == VEPU541_FMT_YUYV422 || + reg_base->reg0198_src_fmt.src_cfmt == VEPU541_FMT_UYVY422) + stridey = prep_cfg->width * 2; + } + + stridec = (reg_base->reg0198_src_fmt.src_cfmt == VEPU541_FMT_YUV422SP || + reg_base->reg0198_src_fmt.src_cfmt == VEPU541_FMT_YUV420SP) ? + stridey : stridey / 2; + + if (reg_base->reg0198_src_fmt.src_cfmt < VEPU541_FMT_NONE) { + reg_base->reg0199_src_udfy.csc_wgt_r2y = 66; + reg_base->reg0199_src_udfy.csc_wgt_g2y = 129; + reg_base->reg0199_src_udfy.csc_wgt_b2y = 25; + + reg_base->reg0200_src_udfu.csc_wgt_r2u = -38; + reg_base->reg0200_src_udfu.csc_wgt_g2u = -74; + reg_base->reg0200_src_udfu.csc_wgt_b2u = 112; + + reg_base->reg0201_src_udfv.csc_wgt_r2v = 112; + reg_base->reg0201_src_udfv.csc_wgt_g2v = -94; + reg_base->reg0201_src_udfv.csc_wgt_b2v = -18; + + reg_base->reg0202_src_udfo.csc_ofst_y = 16; + reg_base->reg0202_src_udfo.csc_ofst_u = 128; + reg_base->reg0202_src_udfo.csc_ofst_v = 128; + } + + reg_base->reg0205_src_strd0.src_strd0 = stridey; + reg_base->reg0206_src_strd1.src_strd1 = stridec; + + return MPP_OK; +} + +static void vepu540c_h265_set_slice_regs(H265eSyntax_new *syn, hevc_vepu540c_base *regs) +{ + regs->reg0237_synt_sps.smpl_adpt_ofst_e = syn->pp.sample_adaptive_offset_enabled_flag; + regs->reg0237_synt_sps.num_st_ref_pic = syn->pp.num_short_term_ref_pic_sets; + regs->reg0237_synt_sps.num_lt_ref_pic = syn->pp.num_long_term_ref_pics_sps; + regs->reg0237_synt_sps.lt_ref_pic_prsnt = syn->pp.long_term_ref_pics_present_flag; + regs->reg0237_synt_sps.tmpl_mvp_e = syn->pp.sps_temporal_mvp_enabled_flag; + regs->reg0237_synt_sps.log2_max_poc_lsb = syn->pp.log2_max_pic_order_cnt_lsb_minus4; + regs->reg0237_synt_sps.strg_intra_smth = syn->pp.strong_intra_smoothing_enabled_flag; + + regs->reg0238_synt_pps.dpdnt_sli_seg_en = syn->pp.dependent_slice_segments_enabled_flag; + regs->reg0238_synt_pps.out_flg_prsnt_flg = syn->pp.output_flag_present_flag; + regs->reg0238_synt_pps.num_extr_sli_hdr = syn->pp.num_extra_slice_header_bits; + regs->reg0238_synt_pps.sgn_dat_hid_en = syn->pp.sign_data_hiding_enabled_flag; + regs->reg0238_synt_pps.cbc_init_prsnt_flg = syn->pp.cabac_init_present_flag; + regs->reg0238_synt_pps.pic_init_qp = syn->pp.init_qp_minus26 + 26; + regs->reg0238_synt_pps.cu_qp_dlt_en = syn->pp.cu_qp_delta_enabled_flag; + regs->reg0238_synt_pps.chrm_qp_ofst_prsn = syn->pp.pps_slice_chroma_qp_offsets_present_flag; + regs->reg0238_synt_pps.lp_fltr_acrs_sli = syn->pp.pps_loop_filter_across_slices_enabled_flag; + regs->reg0238_synt_pps.dblk_fltr_ovrd_en = syn->pp.deblocking_filter_override_enabled_flag; + regs->reg0238_synt_pps.lst_mdfy_prsnt_flg = syn->pp.lists_modification_present_flag; + regs->reg0238_synt_pps.sli_seg_hdr_extn = syn->pp.slice_segment_header_extension_present_flag; + regs->reg0238_synt_pps.cu_qp_dlt_depth = syn->pp.diff_cu_qp_delta_depth; + regs->reg0238_synt_pps.lpf_fltr_acrs_til = syn->pp.loop_filter_across_tiles_enabled_flag; + + regs->reg0239_synt_sli0.cbc_init_flg = syn->sp.cbc_init_flg; + regs->reg0239_synt_sli0.mvd_l1_zero_flg = syn->sp.mvd_l1_zero_flg; + regs->reg0239_synt_sli0.mrg_up_flg = syn->sp.merge_up_flag; + regs->reg0239_synt_sli0.mrg_lft_flg = syn->sp.merge_left_flag; + regs->reg0239_synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0; + + regs->reg0239_synt_sli0.num_refidx_l1_act = syn->sp.num_refidx_l1_act; + regs->reg0239_synt_sli0.num_refidx_l0_act = syn->sp.num_refidx_l0_act; + + regs->reg0239_synt_sli0.num_refidx_act_ovrd = syn->sp.num_refidx_act_ovrd; + + regs->reg0239_synt_sli0.sli_sao_chrm_flg = syn->sp.sli_sao_chrm_flg; + regs->reg0239_synt_sli0.sli_sao_luma_flg = syn->sp.sli_sao_luma_flg; + regs->reg0239_synt_sli0.sli_tmprl_mvp_e = syn->sp.sli_tmprl_mvp_en; + regs->reg0192_enc_pic.num_pic_tot_cur = syn->sp.tot_poc_num; + + regs->reg0239_synt_sli0.pic_out_flg = syn->sp.pic_out_flg; + regs->reg0239_synt_sli0.sli_type = syn->sp.slice_type; + regs->reg0239_synt_sli0.sli_rsrv_flg = syn->sp.slice_rsrv_flg; + regs->reg0239_synt_sli0.dpdnt_sli_seg_flg = syn->sp.dpdnt_sli_seg_flg; + regs->reg0239_synt_sli0.sli_pps_id = syn->sp.sli_pps_id; + regs->reg0239_synt_sli0.no_out_pri_pic = syn->sp.no_out_pri_pic; + + + regs->reg0240_synt_sli1.sp_tc_ofst_div2 = syn->sp.sli_tc_ofst_div2;; + regs->reg0240_synt_sli1.sp_beta_ofst_div2 = syn->sp.sli_beta_ofst_div2; + regs->reg0240_synt_sli1.sli_lp_fltr_acrs_sli = syn->sp.sli_lp_fltr_acrs_sli; + regs->reg0240_synt_sli1.sp_dblk_fltr_dis = syn->sp.sli_dblk_fltr_dis; + regs->reg0240_synt_sli1.dblk_fltr_ovrd_flg = syn->sp.dblk_fltr_ovrd_flg; + regs->reg0240_synt_sli1.sli_cb_qp_ofst = syn->sp.sli_cb_qp_ofst; + regs->reg0240_synt_sli1.max_mrg_cnd = syn->sp.max_mrg_cnd; + + regs->reg0240_synt_sli1.col_ref_idx = syn->sp.col_ref_idx; + regs->reg0240_synt_sli1.col_frm_l0_flg = syn->sp.col_frm_l0_flg; + regs->reg0241_synt_sli2.sli_poc_lsb = syn->sp.sli_poc_lsb; + regs->reg0241_synt_sli2.sli_hdr_ext_len = syn->sp.sli_hdr_ext_len; + +} + +static void vepu540c_h265_set_ref_regs(H265eSyntax_new *syn, hevc_vepu540c_base *regs) +{ + regs->reg0242_synt_refm0.st_ref_pic_flg = syn->sp.st_ref_pic_flg; + regs->reg0242_synt_refm0.poc_lsb_lt0 = syn->sp.poc_lsb_lt0; + regs->reg0242_synt_refm0.num_lt_pic = syn->sp.num_lt_pic; + + regs->reg0243_synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0; + regs->reg0243_synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0; + regs->reg0243_synt_refm1.used_by_lt_flg0 = syn->sp.used_by_lt_flg0; + regs->reg0243_synt_refm1.used_by_lt_flg1 = syn->sp.used_by_lt_flg1; + regs->reg0243_synt_refm1.used_by_lt_flg2 = syn->sp.used_by_lt_flg2; + regs->reg0243_synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0; + regs->reg0243_synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0; + regs->reg0243_synt_refm1.dlt_poc_msb_prsnt1 = syn->sp.dlt_poc_msb_prsnt1; + regs->reg0243_synt_refm1.num_negative_pics = syn->sp.num_neg_pic; + regs->reg0243_synt_refm1.num_pos_pic = syn->sp.num_pos_pic; + + regs->reg0243_synt_refm1.used_by_s0_flg = syn->sp.used_by_s0_flg; + regs->reg0244_synt_refm2.dlt_poc_s0_m10 = syn->sp.dlt_poc_s0_m10; + regs->reg0244_synt_refm2.dlt_poc_s0_m11 = syn->sp.dlt_poc_s0_m11; + regs->reg0245_synt_refm3.dlt_poc_s0_m12 = syn->sp.dlt_poc_s0_m12; + regs->reg0245_synt_refm3.dlt_poc_s0_m13 = syn->sp.dlt_poc_s0_m13; + + regs->reg0246_synt_long_refm0.poc_lsb_lt1 = syn->sp.poc_lsb_lt1; + regs->reg0247_synt_long_refm1.dlt_poc_msb_cycl1 = syn->sp.dlt_poc_msb_cycl1; + regs->reg0246_synt_long_refm0.poc_lsb_lt2 = syn->sp.poc_lsb_lt2; + regs->reg0243_synt_refm1.dlt_poc_msb_prsnt2 = syn->sp.dlt_poc_msb_prsnt2; + regs->reg0247_synt_long_refm1.dlt_poc_msb_cycl2 = syn->sp.dlt_poc_msb_cycl2; + regs->reg0240_synt_sli1.lst_entry_l0 = syn->sp.lst_entry_l0; + regs->reg0239_synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0; + + return; +} +static void vepu540c_h265_set_me_regs(H265eV540cHalContext *ctx, H265eSyntax_new *syn, hevc_vepu540c_base *regs) +{ + + RK_S32 x_gmv = 0; + RK_S32 y_gmv = 0; + RK_S32 srch_lftw, srch_rgtw, srch_uph, srch_dwnh; + RK_S32 frm_sta = 0, frm_end = 0, pic_w = 0; + RK_S32 pic_wdt_align = ((regs->reg0196_enc_rsl.pic_wd8_m1 + 1) * 8 + 31) / 32 ; + + + regs->reg0220_me_rnge.cime_srch_dwnh = 15; + regs->reg0220_me_rnge.cime_srch_uph = 14; + regs->reg0220_me_rnge.cime_srch_rgtw = 12; + regs->reg0220_me_rnge.cime_srch_lftw = 12; + regs->reg0221_me_cfg.rme_srch_h = 3; + regs->reg0221_me_cfg.rme_srch_v = 3; + + regs->reg0221_me_cfg.srgn_max_num = 72; + regs->reg0221_me_cfg.cime_dist_thre = 1024; + regs->reg0221_me_cfg.rme_dis = 0; + regs->reg0221_me_cfg.fme_dis = 0; + regs->reg0220_me_rnge.dlt_frm_num = 0x1; + srch_lftw = regs->reg0220_me_rnge.cime_srch_lftw * 4; + srch_rgtw = regs->reg0220_me_rnge.cime_srch_rgtw * 4; + srch_uph = regs->reg0220_me_rnge.cime_srch_uph * 2; + srch_dwnh = regs->reg0220_me_rnge.cime_srch_dwnh * 2; + + if (syn->pp.sps_temporal_mvp_enabled_flag && + (ctx->frame_type != INTRA_FRAME)) { + if (ctx->last_frame_type == INTRA_FRAME) { + regs->reg0222_me_cach.colmv_load = 0; + } else { + regs->reg0222_me_cach.colmv_load = 1; + } + regs->reg0222_me_cach.colmv_stor = 1; + } + // calc cme_linebuf_w + { + if (x_gmv - srch_lftw < 0) { + frm_sta = (x_gmv - srch_lftw - 15) / 16; + } else { + frm_sta = (x_gmv - srch_lftw) / 16; + } + if (x_gmv + srch_rgtw < 0) { + frm_end = pic_wdt_align - 1 + (x_gmv + srch_rgtw) / 16; + } else { + frm_end = pic_wdt_align - 1 + (x_gmv + srch_rgtw + 15) / 16; + } + + if (frm_sta < 0) { + frm_sta = 0; + } else if (frm_sta > pic_wdt_align - 1) { + frm_sta = pic_wdt_align - 1; + } + frm_end = mpp_clip(frm_end, 0, pic_wdt_align - 1); + pic_w = (frm_end - frm_sta + 1) * 32; + regs->reg0222_me_cach.cme_linebuf_w = pic_w / 32; + } + + // calc cime_hgt_rama and cime_size_rama + { + RK_U32 rama_size = 1796; + RK_U32 ramb_h; + RK_U32 ctu_2_h = 4; + RK_U32 ctu_8_w = 1 ; + RK_U32 cur_srch_8_w, cur_srch_2_h, cur_srch_h; + + if ((y_gmv % 8 - srch_uph % 8) < 0) { + cur_srch_2_h = (8 + (y_gmv % 8 - srch_uph % 8) % 8 + srch_uph + srch_dwnh) / 2 + ctu_2_h; + } else { + cur_srch_2_h = ((y_gmv % 8 - srch_uph % 8) % 8 + srch_uph + srch_dwnh) / 2 + ctu_2_h; + } + regs->reg0222_me_cach.cime_size_rama = (cur_srch_2_h + 3) / 4 * 4; + + if ((x_gmv % 8 - srch_lftw % 8) < 0) { + cur_srch_8_w = (8 + (x_gmv % 8 - srch_lftw % 8) % 8 + srch_lftw + srch_rgtw + 7) / 8 + ctu_8_w; + } else { + cur_srch_8_w = ((x_gmv % 8 - srch_lftw % 8) % 8 + srch_lftw + srch_rgtw + 7) / 8 + ctu_8_w; + } + + cur_srch_h = ctu_2_h; + ramb_h = cur_srch_2_h; + while ((rama_size > ((cur_srch_h - ctu_2_h) * regs->reg0222_me_cach.cme_linebuf_w + (ramb_h * cur_srch_8_w))) + && (cur_srch_h < regs->reg0222_me_cach.cime_size_rama)) { + cur_srch_h = cur_srch_h + ctu_2_h; + if (ramb_h > ctu_2_h * 2) { + ramb_h = ramb_h - ctu_2_h; + } else { + ramb_h = ctu_2_h; + } + } + + if (cur_srch_2_h == ctu_2_h * 2) { + cur_srch_h = cur_srch_h + ctu_2_h; + ramb_h = ctu_2_h; + } + + if (rama_size < ((cur_srch_h - ctu_2_h) * regs->reg0222_me_cach.cme_linebuf_w + (ramb_h * cur_srch_8_w))) { + cur_srch_h = cur_srch_h - ctu_2_h; + } + + regs->reg0222_me_cach.cime_size_rama = ((cur_srch_h - ctu_2_h) * regs->reg0222_me_cach.cme_linebuf_w + ctu_2_h * cur_srch_8_w) / 4; + regs->reg0222_me_cach.cime_hgt_rama = cur_srch_h / 2; + regs->reg0222_me_cach.fme_prefsu_en = 1; + } + +} + +void vepu540c_h265_set_hw_address(H265eV540cHalContext *ctx, hevc_vepu540c_base *regs, HalEncTask *task) +{ + HalEncTask *enc_task = task; + HalBuf *recon_buf, *ref_buf; + MppBuffer md_info_buf = enc_task->md_info; + H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data; + + hal_h265e_enter(); + + regs->reg0160_adr_src0 = mpp_buffer_get_fd(enc_task->input); + regs->reg0161_adr_src1 = regs->reg0160_adr_src0; + regs->reg0162_adr_src2 = regs->reg0160_adr_src0; + + recon_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.recon_pic.slot_idx); + ref_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.ref_pic.slot_idx); + + if (!syn->sp.non_reference_flag) { + regs->reg0163_rfpw_h_addr = mpp_buffer_get_fd(recon_buf->buf[0]); + regs->reg0164_rfpw_b_addr = regs->reg0163_rfpw_h_addr; + mpp_dev_set_reg_offset(ctx->dev, 164, ctx->fbc_header_len); + } + regs->reg0165_rfpr_h_addr = mpp_buffer_get_fd(ref_buf->buf[0]); + regs->reg0166_rfpr_b_addr = regs->reg0165_rfpr_h_addr; + regs->reg0167_cmvw_addr = mpp_buffer_get_fd(recon_buf->buf[2]); + regs->reg0168_cmvr_addr = mpp_buffer_get_fd(ref_buf->buf[2]); + regs->reg0169_dspw_addr = mpp_buffer_get_fd(recon_buf->buf[1]); + regs->reg0170_dspr_addr = mpp_buffer_get_fd(ref_buf->buf[1]); + + mpp_dev_set_reg_offset(ctx->dev, 166, ctx->fbc_header_len); + + if (md_info_buf) { + regs->reg0192_enc_pic.mei_stor = 1; + regs->reg0171_meiw_addr = mpp_buffer_get_fd(md_info_buf); + } else { + regs->reg0192_enc_pic.mei_stor = 0; + regs->reg0171_meiw_addr = 0; + } + + regs->reg0172_bsbt_addr = mpp_buffer_get_fd(enc_task->output); + /* TODO: stream size relative with syntax */ + regs->reg0173_bsbb_addr = regs->reg0172_bsbt_addr; + regs->reg0175_bsbr_addr = regs->reg0172_bsbt_addr; + regs->reg0174_adr_bsbs = regs->reg0172_bsbt_addr; + + regs->reg0180_adr_rfpt_h = 0xffffffff; + regs->reg0181_adr_rfpb_h = 0; + regs->reg0182_adr_rfpt_b = 0xffffffff; + regs->reg0183_adr_rfpb_b = 0; + + + mpp_dev_set_reg_offset(ctx->dev, 174, mpp_packet_get_length(task->packet)); + mpp_dev_set_reg_offset(ctx->dev, 172, mpp_buffer_get_size(enc_task->output)); + + regs->reg0204_pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame); + regs->reg0204_pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame); +} + +MPP_RET hal_h265e_v540c_gen_regs(void *hal, HalEncTask *task) +{ + H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal; + HalEncTask *enc_task = task; + H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data; + H265eV540cRegSet *regs = ctx->regs; + RK_U32 pic_width_align8, pic_height_align8; + RK_S32 pic_wd32, pic_h32; + VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt; + hevc_vepu540c_control_cfg *reg_ctl = ®s->reg_ctl; + hevc_vepu540c_base *reg_base = ®s->reg_base; + hevc_vepu540c_rc_roi *reg_klut = ®s->reg_rc_roi; + + hal_h265e_enter(); + pic_width_align8 = (syn->pp.pic_width + 7) & (~7); + pic_height_align8 = (syn->pp.pic_height + 7) & (~7); + pic_wd32 = (syn->pp.pic_width + 31) / 32; + pic_h32 = (syn->pp.pic_height + 31) / 32; + + hal_h265e_dbg_simple("frame %d | type %d | start gen regs", + ctx->frame_cnt, ctx->frame_type); + + memset(regs, 0, sizeof(H265eV540cRegSet)); + + reg_ctl->reg0004_enc_strt.lkt_num = 0; + reg_ctl->reg0004_enc_strt.vepu_cmd = ctx->enc_mode; + reg_ctl->reg0005_enc_clr.safe_clr = 0x0; + reg_ctl->reg0005_enc_clr.force_clr = 0x0; + + reg_ctl->reg0008_int_en.enc_done_en = 1; + reg_ctl->reg0008_int_en.lkt_node_done_en = 1; + reg_ctl->reg0008_int_en.sclr_done_en = 1; + reg_ctl->reg0008_int_en.vslc_done_en = 1; + reg_ctl->reg0008_int_en.vbsf_oflw_en = 1; + reg_ctl->reg0008_int_en.vbuf_lens_en = 1; + reg_ctl->reg0008_int_en.enc_err_en = 1; + reg_ctl->reg0008_int_en.dvbm_fcfg_en = 1; + reg_ctl->reg0008_int_en.wdg_en = 1; + reg_ctl->reg0008_int_en.lkt_err_int_en = 0; + reg_ctl->reg0008_int_en.lkt_err_stop_en = 1; + reg_ctl->reg0008_int_en.lkt_force_stop_en = 1; + reg_ctl->reg0008_int_en.jslc_done_en = 1; + reg_ctl->reg0008_int_en.jbsf_oflw_en = 1; + reg_ctl->reg0008_int_en.jbuf_lens_en = 1; + reg_ctl->reg0008_int_en.dvbm_dcnt_en = 1; + + reg_ctl->reg0012_dtrns_map.jpeg_bus_edin = 0x0; + reg_ctl->reg0012_dtrns_map.src_bus_edin = 0x0; + reg_ctl->reg0012_dtrns_map.meiw_bus_edin = 0x0; + reg_ctl->reg0012_dtrns_map.bsw_bus_edin = 0x7; + reg_ctl->reg0012_dtrns_map.lktr_bus_edin = 0x0; + reg_ctl->reg0012_dtrns_map.roir_bus_edin = 0x0; + reg_ctl->reg0012_dtrns_map.lktw_bus_edin = 0x0; + reg_ctl->reg0012_dtrns_map.rec_nfbc_bus_edin = 0x0; + +// reg_ctl->reg0013_dtrns_cfg.dspr_otsd = (ctx->frame_type == INTER_P_FRAME); + reg_ctl->reg0013_dtrns_cfg.axi_brsp_cke = 0x0; + reg_ctl->reg0014_enc_wdg.vs_load_thd = 0x1fffff; + reg_ctl->reg0014_enc_wdg.rfp_load_thd = 0xff; + + reg_ctl->reg0021_func_en.cke = 1; + reg_ctl->reg0021_func_en.resetn_hw_en = 1; + reg_ctl->reg0021_func_en.enc_done_tmvp_en = 1; + + reg_base->reg0196_enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1; + reg_base->reg0197_src_fill.pic_wfill = (syn->pp.pic_width & 0x7) + ? (8 - (syn->pp.pic_width & 0x7)) : 0; + reg_base->reg0196_enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1; + reg_base->reg0197_src_fill.pic_hfill = (syn->pp.pic_height & 0x7) + ? (8 - (syn->pp.pic_height & 0x7)) : 0; + + reg_base->reg0192_enc_pic.enc_stnd = 1; //H265 + reg_base->reg0192_enc_pic.cur_frm_ref = !syn->sp.non_reference_flag; //current frame will be refered + reg_base->reg0192_enc_pic.bs_scp = 1; + reg_base->reg0192_enc_pic.log2_ctu_num = mpp_ceil_log2(pic_wd32 * pic_h32); + + reg_base->reg0203_src_proc.src_mirr = 0; + reg_base->reg0203_src_proc.src_rot = 0; + + reg_klut->klut_ofst.chrm_klut_ofst = (ctx->frame_type == INTRA_FRAME) ? 0 : 3; + + reg_base->reg0216_sli_splt.sli_splt_mode = syn->sp.sli_splt_mode; + reg_base->reg0216_sli_splt.sli_splt_cpst = syn->sp.sli_splt_cpst; + reg_base->reg0216_sli_splt.sli_splt = syn->sp.sli_splt; + reg_base->reg0216_sli_splt.sli_flsh = syn->sp.sli_flsh; + reg_base->reg0216_sli_splt.sli_max_num_m1 = syn->sp.sli_max_num_m1; + + reg_base->reg0218_sli_cnum.sli_splt_cnum_m1 = syn->sp.sli_splt_cnum_m1; + reg_base->reg0217_sli_byte.sli_splt_byte = syn->sp.sli_splt_byte; + + vepu540c_h265_set_me_regs(ctx, syn, reg_base); + + reg_base->reg0232_rdo_cfg.chrm_spcl = 1; + reg_base->reg0232_rdo_cfg.cu_inter_e = 0x06db; + reg_base->reg0232_rdo_cfg.cu_intra_e = 0xf; + + if (syn->pp.num_long_term_ref_pics_sps) { + reg_base->reg0232_rdo_cfg.ltm_col = 0; + reg_base->reg0232_rdo_cfg.ltm_idx0l0 = 1; + } else { + reg_base->reg0232_rdo_cfg.ltm_col = 0; + reg_base->reg0232_rdo_cfg.ltm_idx0l0 = 0; + } + + reg_base->reg0232_rdo_cfg.ccwa_e = 1; + reg_base->reg0232_rdo_cfg.scl_lst_sel = syn->pp.scaling_list_enabled_flag; + { + RK_U32 i_nal_type = 0; + + /* TODO: extend syn->frame_coding_type definition */ + if (ctx->frame_type == INTRA_FRAME) { + /* reset ref pictures */ + i_nal_type = NAL_IDR_W_RADL; + } else if (ctx->frame_type == INTER_P_FRAME ) { + i_nal_type = NAL_TRAIL_R; + } else { + i_nal_type = NAL_TRAIL_R; + } + reg_base->reg0236_synt_nal.nal_unit_type = i_nal_type; + } + + vepu540c_h265_set_hw_address(ctx, reg_base, task); + vepu540c_h265_set_pp_regs(regs, fmt, &ctx->cfg->prep); + vepu540c_h265_set_rc_regs(ctx, regs, task); + vepu540c_h265_set_slice_regs(syn, reg_base); + vepu540c_h265_set_ref_regs(syn, reg_base); + vepu540c_h265_set_patch_info(ctx->dev, syn, (Vepu541Fmt)fmt->format, enc_task); + + /* ROI configure */ + if (ctx->roi_data) + vepu540c_set_roi(®s->reg_rc_roi.roi_cfg, ctx->roi_data, + ctx->cfg->prep.width, ctx->cfg->prep.height); + /*paramet cfg*/ + vepu540c_h265_global_cfg_set(ctx, regs); + + ctx->frame_num++; + + hal_h265e_leave(); + return MPP_OK; +} + +MPP_RET hal_h265e_v540c_start(void *hal, HalEncTask *enc_task) +{ + MPP_RET ret = MPP_OK; + H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal; + RK_U32 *regs = (RK_U32*)ctx->regs; + H265eV540cRegSet *hw_regs = ctx->regs; + H265eV540cStatusElem *reg_out = (H265eV540cStatusElem *)ctx->reg_out[0]; + MppDevRegWrCfg cfg; + MppDevRegRdCfg cfg1; + RK_U32 i = 0; + hal_h265e_enter(); + + if (enc_task->flags.err) { + hal_h265e_err("enc_task->flags.err %08x, return e arly", + enc_task->flags.err); + return MPP_NOK; + } + + cfg.reg = (RK_U32*)&hw_regs->reg_ctl; + cfg.size = sizeof(hevc_vepu540c_control_cfg); + cfg.offset = VEPU540C_CTL_OFFSET; + + ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg); + if (ret) { + mpp_err_f("set register write failed %d\n", ret); + return ret; + } + + if (hal_h265e_debug & HAL_H265E_DBG_CTL_REGS) { + regs = (RK_U32*)&hw_regs->reg_ctl; + for (i = 0; i < sizeof(hevc_vepu540c_control_cfg) / 4; i++) { + hal_h265e_dbg_ctl("ctl reg[%04x]: 0%08x\n", i * 4, regs[i]); + } + } + + cfg.reg = &hw_regs->reg_base; + cfg.size = sizeof(hevc_vepu540c_base); + cfg.offset = VEPU540C_BASE_OFFSET; + + ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg); + if (ret) { + mpp_err_f("set register write failed %d\n", ret); + return ret; + } + + if (hal_h265e_debug & HAL_H265E_DBG_REGS) { + regs = (RK_U32*)(&hw_regs->reg_base); + for (i = 0; i < 32; i++) { + hal_h265e_dbg_regs("hw add cfg reg[%04x]: 0%08x\n", i * 4, regs[i]); + } + regs += 32; + for (i = 0; i < (sizeof(hevc_vepu540c_base) - 128) / 4; i++) { + hal_h265e_dbg_regs("set reg[%04x]: 0%08x\n", i * 4, regs[i]); + } + } + cfg.reg = &hw_regs->reg_rc_roi; + cfg.size = sizeof(hevc_vepu540c_rc_roi); + cfg.offset = VEPU540C_RCROI_OFFSET; + + ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg); + if (ret) { + mpp_err_f("set register write failed %d\n", ret); + return ret; + } + + if (hal_h265e_debug & HAL_H265E_DBG_RCKUT_REGS) { + regs = (RK_U32*)&hw_regs->reg_rc_roi; + for (i = 0; i < sizeof(hevc_vepu540c_rc_roi) / 4; i++) { + hal_h265e_dbg_rckut("set reg[%04x]: 0%08x\n", i * 4, regs[i]); + } + } + + cfg.reg = &hw_regs->reg_wgt; + cfg.size = sizeof(hevc_vepu540c_wgt); + cfg.offset = VEPU540C_WEG_OFFSET; + + ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg); + if (ret) { + mpp_err_f("set register write failed %d\n", ret); + return ret; + } + + if (hal_h265e_debug & HAL_H265E_DBG_WGT_REGS) { + regs = (RK_U32*)&hw_regs->reg_wgt; + for (i = 0; i < sizeof(hevc_vepu540c_wgt) / 4; i++) { + hal_h265e_dbg_wgt("set reg[%04x]: 0%08x\n", i * 4, regs[i]); + } + } + + cfg.reg = &hw_regs->reg_rdo; + cfg.size = sizeof(vepu540c_rdo_cfg); + cfg.offset = VEPU540C_RDOCFG_OFFSET; + + ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg); + if (ret) { + mpp_err_f("set register write failed %d\n", ret); + return ret; + } + + cfg1.reg = ®_out->hw_status; + cfg1.size = sizeof(RK_U32); + cfg1.offset = VEPU540C_REG_BASE_HW_STATUS; + + ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1); + if (ret) { + mpp_err_f("set register read failed %d\n", ret); + return ret; + } + + cfg1.reg = ®_out->st; + cfg1.size = sizeof(H265eV540cStatusElem) - 4; + cfg1.offset = VEPU540C_STATUS_OFFSET; + + ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1); + if (ret) { + mpp_err_f("set register read failed %d\n", ret); + return ret; + } + + ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL); + if (ret) { + mpp_err_f("send cmd failed %d\n", ret); + } + hal_h265e_leave(); + return ret; +} + +static MPP_RET vepu540c_h265_set_feedback(H265eV540cHalContext *ctx, HalEncTask *enc_task) +{ + EncRcTaskInfo *hal_rc_ret = (EncRcTaskInfo *)&enc_task->rc_task->info; + vepu540c_h265_fbk *fb = &ctx->feedback; + MppEncCfgSet *cfg = ctx->cfg; + RK_S32 mb64_num = ((cfg->prep.width + 63) / 64) * ((cfg->prep.height + 63) / 64); + RK_S32 mb8_num = (mb64_num << 6); + RK_S32 mb4_num = (mb8_num << 2); + H265eV540cStatusElem *elem = (H265eV540cStatusElem *)ctx->reg_out[0]; + RK_U32 hw_status = elem->hw_status; + + hal_h265e_enter(); + + fb->qp_sum += elem->st.qp_sum; + + fb->out_strm_size += elem->st.bs_lgth_l32; + + fb->sse_sum += (RK_S64)(elem->st.sse_h32 << 16) + + ((elem->st.st_sse_bsl.sse_l16 >> 16) & 0xffff) ; + + fb->hw_status = hw_status; + hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status); + if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH) + hal_h265e_err("RKV_ENC_INT_LINKTABLE_FINISH"); + + if (hw_status & RKV_ENC_INT_ONE_FRAME_FINISH) + hal_h265e_dbg_detail("RKV_ENC_INT_ONE_FRAME_FINISH"); + + if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH) + hal_h265e_err("RKV_ENC_INT_ONE_SLICE_FINISH"); + + if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH) + hal_h265e_err("RKV_ENC_INT_SAFE_CLEAR_FINISH"); + + if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW) + hal_h265e_err("RKV_ENC_INT_BIT_STREAM_OVERFLOW"); + + if (hw_status & RKV_ENC_INT_BUS_WRITE_FULL) + hal_h265e_err("RKV_ENC_INT_BUS_WRITE_FULL"); + + if (hw_status & RKV_ENC_INT_BUS_WRITE_ERROR) + hal_h265e_err("RKV_ENC_INT_BUS_WRITE_ERROR"); + + if (hw_status & RKV_ENC_INT_BUS_READ_ERROR) + hal_h265e_err("RKV_ENC_INT_BUS_READ_ERROR"); + + if (hw_status & RKV_ENC_INT_TIMEOUT_ERROR) + hal_h265e_err("RKV_ENC_INT_TIMEOUT_ERROR"); + + // fb->st_madi += elem->st.madi; + //fb->st_madp += elem->st.madp; + fb->st_mb_num += elem->st.st_bnum_b16.num_b16; + // fb->st_ctu_num += elem->st.st_bnum_cme.num_ctu; + + fb->st_lvl64_inter_num += elem->st.st_pnum_p64.pnum_p64; + fb->st_lvl32_inter_num += elem->st.st_pnum_p32.pnum_p32; + fb->st_lvl32_intra_num += elem->st.st_pnum_i32.pnum_i32; + fb->st_lvl16_inter_num += elem->st.st_pnum_p16.pnum_p16; + fb->st_lvl16_intra_num += elem->st.st_pnum_i16.pnum_i16; + fb->st_lvl8_inter_num += elem->st.st_pnum_p8.pnum_p8; + fb->st_lvl8_intra_num += elem->st.st_pnum_i8.pnum_i8; + fb->st_lvl4_intra_num += elem->st.st_pnum_i4.pnum_i4; + memcpy(&fb->st_cu_num_qp[0], &elem->st.st_b8_qp, 52 * sizeof(RK_U32)); + + hal_rc_ret->bit_real += fb->out_strm_size * 8; + + if (fb->st_mb_num) { + fb->st_madi = fb->st_madi / fb->st_mb_num; + } else { + fb->st_madi = 0; + } + if (fb->st_ctu_num) { + fb->st_madp = fb->st_madp / fb->st_ctu_num; + } else { + fb->st_madp = 0; + } + + if (mb4_num > 0) + hal_rc_ret->iblk4_prop = ((((fb->st_lvl4_intra_num + fb->st_lvl8_intra_num) << 2) + + (fb->st_lvl16_intra_num << 4) + + (fb->st_lvl32_intra_num << 6)) << 8) / mb4_num; + + if (mb64_num > 0) { + /* + hal_cfg[k].inter_lv8_prop = ((fb->st_lvl8_inter_num + (fb->st_lvl16_inter_num << 2) + + (fb->st_lvl32_inter_num << 4) + + (fb->st_lvl64_inter_num << 6)) << 8) / mb8_num;*/ + + hal_rc_ret->quality_real = fb->qp_sum / mb8_num; + // hal_cfg[k].sse = fb->sse_sum / mb64_num; + } + + hal_rc_ret->madi = fb->st_madi; + hal_rc_ret->madp = fb->st_madp; + hal_h265e_leave(); + return MPP_OK; +} + + +//#define DUMP_DATA +MPP_RET hal_h265e_v540c_wait(void *hal, HalEncTask *task) +{ + MPP_RET ret = MPP_OK; + H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal; + HalEncTask *enc_task = task; + H265eV540cStatusElem *elem = (H265eV540cStatusElem *)ctx->reg_out; + hal_h265e_enter(); + + if (enc_task->flags.err) { + hal_h265e_err("enc_task->flags.err %08x, return early", + enc_task->flags.err); + return MPP_NOK; + } + + ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL); + +#ifdef DUMP_DATA + static FILE *fp_fbd = NULL; + static FILE *fp_fbh = NULL; + static FILE *fp_dws = NULL; + HalBuf *recon_buf; + static RK_U32 frm_num = 0; + H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data; + recon_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.recon_pic.slot_idx); + char file_name[20] = ""; + size_t rec_size = mpp_buffer_get_size(recon_buf->buf[0]); + size_t dws_size = mpp_buffer_get_size(recon_buf->buf[1]); + + void *ptr = mpp_buffer_get_ptr(recon_buf->buf[0]); + void *dws_ptr = mpp_buffer_get_ptr(recon_buf->buf[1]); + + sprintf(&file_name[0], "fbd%d.bin", frm_num); + if (fp_fbd != NULL) { + fclose(fp_fbd); + fp_fbd = NULL; + } else { + fp_fbd = fopen(file_name, "wb+"); + } + if (fp_fbd) { + fwrite(ptr + ctx->fbc_header_len, 1, rec_size - ctx->fbc_header_len, fp_fbd); + fflush(fp_fbd); + } + + sprintf(&file_name[0], "fbh%d.bin", frm_num); + + if (fp_fbh != NULL) { + fclose(fp_fbh); + fp_fbh = NULL; + } else { + fp_fbh = fopen(file_name, "wb+"); + } + + if (fp_fbh) { + fwrite(ptr , 1, ctx->fbc_header_len, fp_fbh); + fflush(fp_fbh); + } + + + sprintf(&file_name[0], "dws%d.bin", frm_num); + + if (fp_dws != NULL) { + fclose(fp_dws); + fp_dws = NULL; + } else { + fp_dws = fopen(file_name, "wb+"); + } + + if (fp_dws) { + fwrite(dws_ptr , 1, dws_size, fp_dws); + fflush(fp_dws); + } + frm_num++; +#endif + if (ret) + mpp_err_f("poll cmd failed %d status %d \n", ret, elem->hw_status); + + hal_h265e_leave(); + return ret; +} + +MPP_RET hal_h265e_v540c_get_task(void *hal, HalEncTask *task) +{ + H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal; + MppFrame frame = task->frame; + EncFrmStatus *frm_status = &task->rc_task->frm; + + hal_h265e_enter(); + + if (vepu540c_h265_setup_hal_bufs(ctx)) { + hal_h265e_err("vepu541_h265_allocate_buffers failed, free buffers and return\n"); + task->flags.err |= HAL_ENC_TASK_ERR_ALLOC; + return MPP_ERR_MALLOC; + } + + ctx->last_frame_type = ctx->frame_type; + if (frm_status->is_intra) { + ctx->frame_type = INTRA_FRAME; + } else { + ctx->frame_type = INTER_P_FRAME; + } + if (!frm_status->reencode && mpp_frame_has_meta(task->frame)) { + MppMeta meta = mpp_frame_get_meta(frame); + + mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data); + } + memset(&ctx->feedback, 0, sizeof(vepu540c_h265_fbk)); + + hal_h265e_leave(); + return MPP_OK; +} + +MPP_RET hal_h265e_v540c_ret_task(void *hal, HalEncTask *task) +{ + H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal; + HalEncTask *enc_task = task; + vepu540c_h265_fbk *fb = &ctx->feedback; + hal_h265e_enter(); + + vepu540c_h265_set_feedback(ctx, enc_task); + enc_task->hw_length = fb->out_strm_size; + enc_task->length += fb->out_strm_size; + + hal_h265e_dbg_detail("output stream size %d\n", fb->out_strm_size); + + hal_h265e_leave(); + return MPP_OK; +} + +const MppEncHalApi hal_h265e_vepu540c = { + "hal_h265e_v540c", + MPP_VIDEO_CodingHEVC, + sizeof(H265eV540cHalContext), + 0, + hal_h265e_v540c_init, + hal_h265e_v540c_deinit, + hal_h265e_vepu540c_prepare, + hal_h265e_v540c_get_task, + hal_h265e_v540c_gen_regs, + hal_h265e_v540c_start, + hal_h265e_v540c_wait, + NULL, + NULL, + hal_h265e_v540c_ret_task, +}; diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu540c.h b/mpp/hal/rkenc/h265e/hal_h265e_vepu540c.h new file mode 100644 index 00000000..5613ce23 --- /dev/null +++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu540c.h @@ -0,0 +1,24 @@ +/* + * Copyright 2022 Rockchip Electronics Co. LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_H265E_VEPU540C_H__ +#define __HAL_H265E_VEPU540C_H__ + +#include "mpp_enc_hal.h" + +extern const MppEncHalApi hal_h265e_vepu540c; + +#endif /* __HAL_H265E_VEPU540C_H__ */ diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu540c_reg.h b/mpp/hal/rkenc/h265e/hal_h265e_vepu540c_reg.h new file mode 100644 index 00000000..9e1e7c96 --- /dev/null +++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu540c_reg.h @@ -0,0 +1,1159 @@ +/* + * Copyright 2021 Rockchip Electronics Co. LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_H265E_VEPU540C_REG_H__ +#define __HAL_H265E_VEPU540C_REG_H__ + +#include "rk_type.h" +#include "vepu540c_common.h" +/* class: control/link */ +/* 0x00000000 reg0 - 0x00000120 reg72 */ +typedef struct HevcVepu540cControlCfg_t { + /* 0x00000000 reg0 */ + struct { + RK_U32 sub_ver : 8; + RK_U32 h264_cap : 1; + RK_U32 hevc_cap : 1; + RK_U32 reserved : 2; + RK_U32 res_cap : 4; + RK_U32 osd_cap : 2; + RK_U32 filtr_cap : 2; + RK_U32 bfrm_cap : 1; + RK_U32 fbc_cap : 2; + RK_U32 reserved1 : 1; + RK_U32 ip_id : 8; + } reg0001_version; + + /* 0x4 - 0xc */ + RK_U32 reserved1_3[3]; + + /* 0x00000010 reg4 */ + struct { + RK_U32 lkt_num : 8; + RK_U32 vepu_cmd : 3; + RK_U32 reserved : 21; + } reg0004_enc_strt; + + /* 0x00000014 reg5 */ + struct { + RK_U32 safe_clr : 1; + RK_U32 force_clr : 1; + RK_U32 reserved : 30; + } reg0005_enc_clr; + + /* 0x18 */ + struct { + RK_U32 vswm_lcnt_soft : 14; + RK_U32 vswm_fcnt_soft : 8; + RK_U32 reserved : 2; + RK_U32 dvbm_ack_soft : 1; + RK_U32 dvbm_ack_sel : 1; + RK_U32 dvbm_inf_sel : 1; + RK_U32 reserved1 : 5; + } reg0006_vs_ldly; + + /* 0x1c */ + RK_U32 reserved007; + + /* 0x00000020 reg8 */ + struct { + RK_U32 enc_done_en : 1; + RK_U32 lkt_node_done_en : 1; + RK_U32 sclr_done_en : 1; + RK_U32 vslc_done_en : 1; + RK_U32 vbsf_oflw_en : 1; + RK_U32 vbuf_lens_en : 1; + RK_U32 enc_err_en : 1; + RK_U32 dvbm_fcfg_en : 1; + RK_U32 wdg_en : 1; + RK_U32 lkt_err_int_en : 1; + RK_U32 lkt_err_stop_en : 1; + RK_U32 lkt_force_stop_en : 1; + RK_U32 jslc_done_en : 1; + RK_U32 jbsf_oflw_en : 1; + RK_U32 jbuf_lens_en : 1; + RK_U32 dvbm_dcnt_en : 1; + RK_U32 reserved : 16; + } reg0008_int_en; + + /* 0x00000024 reg9 */ + struct { + RK_U32 enc_done_msk : 1; + RK_U32 lkt_node_done_msk : 1; + RK_U32 sclr_done_msk : 1; + RK_U32 vslc_done_msk : 1; + RK_U32 vbsf_oflw_msk : 1; + RK_U32 vbuf_lens_msk : 1; + RK_U32 enc_err_msk : 1; + RK_U32 dvbm_fcfg_msk : 1; + RK_U32 wdg_msk : 1; + RK_U32 lkt_err_int_msk : 1; + RK_U32 lkt_err_stop_msk : 1; + RK_U32 lkt_force_stop_msk : 1; + RK_U32 jslc_done_msk : 1; + RK_U32 jbsf_oflw_msk : 1; + RK_U32 jbuf_lens_msk : 1; + RK_U32 dvbm_dcnt_msk : 1; + RK_U32 reserved : 16; + } reg0009_int_msk; + + /* 0x00000028 reg10 */ + struct { + RK_U32 enc_done_clr : 1; + RK_U32 lkt_node_done_clr : 1; + RK_U32 sclr_done_clr : 1; + RK_U32 vslc_done_clr : 1; + RK_U32 vbsf_oflw_clr : 1; + RK_U32 vbuf_lens_clr : 1; + RK_U32 enc_err_clr : 1; + RK_U32 dvbm_fcfg_clr : 1; + RK_U32 wdg_clr : 1; + RK_U32 lkt_err_int_clr : 1; + RK_U32 lkt_err_stop_clr : 1; + RK_U32 lkt_force_stop_clr : 1; + RK_U32 jslc_done_clr : 1; + RK_U32 jbsf_oflw_clr : 1; + RK_U32 jbuf_lens_clr : 1; + RK_U32 dvbm_dcnt_clr : 1; + RK_U32 reserved : 16; + } reg0010_int_clr; + + /* 0x0000002c reg11 */ + struct { + RK_U32 enc_done_sta : 1; + RK_U32 lkt_node_done_sta : 1; + RK_U32 sclr_done_sta : 1; + RK_U32 vslc_done_sta : 1; + RK_U32 vbsf_oflw_sta : 1; + RK_U32 vbuf_lens_sta : 1; + RK_U32 enc_err_sta : 1; + RK_U32 dvbm_fcfg_sta : 1; + RK_U32 wdg_sta : 1; + RK_U32 lkt_err_int_sta : 1; + RK_U32 lkt_err_stop_sta : 1; + RK_U32 lkt_force_stop_sta : 1; + RK_U32 jslc_done_sta : 1; + RK_U32 jbsf_oflw_sta : 1; + RK_U32 jbuf_lens_sta : 1; + RK_U32 dvbm_dcnt_sta : 1; + RK_U32 reserved : 16; + } reg0011_int_sta; + + /* 0x00000030 reg12 */ + struct { + RK_U32 jpeg_bus_edin : 4; + RK_U32 src_bus_edin : 4; + RK_U32 meiw_bus_edin : 4; + RK_U32 bsw_bus_edin : 4; + RK_U32 lktr_bus_edin : 4; + RK_U32 roir_bus_edin : 4; + RK_U32 lktw_bus_edin : 4; + RK_U32 rec_nfbc_bus_edin : 4; + } reg0012_dtrns_map; + + /* 0x00000034 reg13 */ + struct { + RK_U32 reserved : 16; + RK_U32 axi_brsp_cke : 10; + RK_U32 reserved1 : 6; + } reg0013_dtrns_cfg; + + /* 0x00000038 reg14 */ + struct { + RK_U32 vs_load_thd : 24; + RK_U32 rfp_load_thd : 8; + } reg0014_enc_wdg; + + /* 0x0000003c reg15 */ + struct { + RK_U32 hurry_en : 1; + RK_U32 hurry_low : 3; + RK_U32 hurry_mid : 3; + RK_U32 hurry_high : 3; + RK_U32 reserved : 22; + } reg0015_qos_cfg; + + /* 0x00000040 reg16 */ + struct { + RK_U32 qos_period : 16; + RK_U32 reserved : 16; + } reg0016_qos_perd; + + /* 0x00000044 reg17 */ + RK_U32 reg0017_hurry_thd_low; + + /* 0x00000048 reg18 */ + RK_U32 reg0018_hurry_thd_mid; + + /* 0x0000004c reg19 */ + RK_U32 reg0019_hurry_thd_high; + + /* 0x00000050 reg20 */ + struct { + RK_U32 idle_en_core : 1; + RK_U32 idle_en_axi : 1; + RK_U32 idle_en_ahb : 1; + RK_U32 reserved : 29; + } reg0020_enc_idle_en; + + /* 0x00000054 reg21 */ + struct { + RK_U32 cke : 1; + RK_U32 resetn_hw_en : 1; + RK_U32 enc_done_tmvp_en : 1; + RK_U32 sram_ckg_en : 1; + RK_U32 link_err_stop : 1; + RK_U32 reserved : 27; + } reg0021_func_en; + + /* 0x00000058 reg22 */ + struct { + RK_U32 recon32_ckg : 1; + RK_U32 iqit32_ckg : 1; + RK_U32 q32_ckg : 1; + RK_U32 t32_ckg : 1; + RK_U32 cabac32_ckg : 1; + RK_U32 recon16_ckg : 1; + RK_U32 iqit16_ckg : 1; + RK_U32 q16_ckg : 1; + RK_U32 t16_ckg : 1; + RK_U32 cabac16_ckg : 1; + RK_U32 recon8_ckg : 1; + RK_U32 iqit8_ckg : 1; + RK_U32 q8_ckg : 1; + RK_U32 t8_ckg : 1; + RK_U32 cabac8_ckg : 1; + RK_U32 recon4_ckg : 1; + RK_U32 iqit4_ckg : 1; + RK_U32 q4_ckg : 1; + RK_U32 t4_ckg : 1; + RK_U32 cabac4_ckg : 1; + RK_U32 intra32_ckg : 1; + RK_U32 intra16_ckg : 1; + RK_U32 intra8_ckg : 1; + RK_U32 intra4_ckg : 1; + RK_U32 inter_pred_ckg : 1; + RK_U32 reserved : 7; + } reg0022_rdo_ckg; + + /* 0x0000005c reg23 */ + struct { + RK_U32 core_id : 2; + RK_U32 reserved : 30; + } reg0023_enc_id; + + + /* 0x00000060 reg24 */ + struct { + RK_U32 dvbm_en : 1; + RK_U32 src_badr_sel : 1; + RK_U32 vinf_frm_match : 1; + RK_U32 reserved : 1; + RK_U32 vrsp_half_cycle : 4; + RK_U32 reserved1 : 24; + } reg0024_dvbm_cfg; + + /* 0x00000064 - 0x6c*/ + RK_U32 reg025_027[3]; + + /* 0x00000070*/ + struct { + RK_U32 reserved : 4; + RK_U32 lkt_addr : 28; + } reg0028_lkt_base_addr; + + /* 0x74 - 0xfc */ + RK_U32 reserved29_63[35]; + + struct { + RK_U32 node_core_id : 2; + RK_U32 node_int : 1; + RK_U32 reserved : 1; + RK_U32 task_id : 12; + RK_U32 reserved1 : 16; + } reg0064_lkt_node_cfg; + + /* 0x00000104 reg65 */ + struct { + RK_U32 pcfg_rd_en : 1; + RK_U32 reserved : 3; + RK_U32 lkt_addr_pcfg : 28; + } reg0065_lkt_addr_pcfg; + + /* 0x00000108 reg66 */ + struct { + RK_U32 rc_cfg_rd_en : 1; + RK_U32 reserved : 3; + RK_U32 lkt_addr_rc_cfg : 28; + } reg0066_lkt_addr_rc_cfg; + + /* 0x0000010c reg67 */ + struct { + RK_U32 par_cfg_rd_en : 1; + RK_U32 reserved : 3; + RK_U32 lkt_addr_par_cfg : 28; + } reg0067_lkt_addr_par_cfg; + + /* 0x00000110 reg68 */ + struct { + RK_U32 sqi_cfg_rd_en : 1; + RK_U32 reserved : 3; + RK_U32 lkt_addr_sqi_cfg : 28; + } reg0068_lkt_addr_sqi_cfg; + + /* 0x00000114 reg69 */ + struct { + RK_U32 scal_cfg_rd_en : 1; + RK_U32 reserved : 3; + RK_U32 lkt_addr_scal_cfg : 28; + } reg0069_lkt_addr_scal_cfg; + + /* 0x00000118 reg70 */ + struct { + RK_U32 pp_cfg_rd_en : 1; + RK_U32 reserved : 3; + RK_U32 lkt_addr_pp_cfg : 28; + } reg0070_lkt_addr_osd_cfg; + + /* 0x0000011c reg71 */ + struct { + RK_U32 st_out_en : 1; + RK_U32 reserved : 3; + RK_U32 lkt_addr_st : 28; + } reg0071_lkt_addr_st; + + /* 0x00000120 reg72 */ + struct { + RK_U32 nxt_node_vld : 1; + RK_U32 reserved : 3; + RK_U32 lkt_addr_nxt : 28; + } reg0072_lkt_addr_nxt; +} hevc_vepu540c_control_cfg; + +/* class: buffer/video syntax */ +/* 0x00000280 reg160 - 0x000003f4 reg253*/ +typedef struct HevcVepu540cBase_t { + vepu540c_online online_addr; + /* 0x00000280 reg160 */ + RK_U32 reg0160_adr_src0; + + /* 0x00000284 reg161 */ + RK_U32 reg0161_adr_src1; + + /* 0x00000288 reg162 */ + RK_U32 reg0162_adr_src2; + + /* 0x0000028c reg163 */ + RK_U32 reg0163_rfpw_h_addr; + + /* 0x00000290 reg164 */ + RK_U32 reg0164_rfpw_b_addr; + + /* 0x00000294 reg165 */ + RK_U32 reg0165_rfpr_h_addr; + + /* 0x00000298 reg166 */ + RK_U32 reg0166_rfpr_b_addr; + + /* 0x0000029c reg167 */ + RK_U32 reg0167_cmvw_addr; + + /* 0x000002a0 reg168 */ + RK_U32 reg0168_cmvr_addr; + + /* 0x000002a4 reg169 */ + RK_U32 reg0169_dspw_addr; + + /* 0x000002a8 reg170 */ + RK_U32 reg0170_dspr_addr; + + /* 0x000002ac reg171 */ + RK_U32 reg0171_meiw_addr; + + /* 0x000002b0 reg172 */ + RK_U32 reg0172_bsbt_addr; + + /* 0x000002b4 reg173 */ + RK_U32 reg0173_bsbb_addr; + + /* 0x000002b8 reg174 */ + RK_U32 reg0174_adr_bsbs; + + /* 0x000002bc reg175 */ + RK_U32 reg0175_bsbr_addr; + + /* 0x000002c0 reg176 */ + RK_U32 reg0176_lpfw_addr; + + /* 0x000002c4 reg177 */ + RK_U32 reg0177_lpfr_addr; + + /* 0x000002c8 reg178 */ + RK_U32 reg0178_adr_ebuft; + + /* 0x000002cc reg179 */ + RK_U32 reg0179_adr_ebufb; + + /* 0x000002d0 reg180 */ + RK_U32 reg0180_adr_rfpt_h; + + /* 0x000002d4 reg181 */ + RK_U32 reg0181_adr_rfpb_h; + + /* 0x000002d8 reg182 */ + RK_U32 reg0182_adr_rfpt_b; + + /* 0x000002dc reg183 */ + RK_U32 reg0183_adr_rfpb_b; + + /* 0x000002e0 reg184 */ + RK_U32 reg0184_adr_smr_rd; + + /* 0x000002e4 reg185 */ + RK_U32 reg0185_adr_smr_wr; + + /* 0x000002e8 reg186 */ + RK_U32 reg0186_adr_roir; + + /* 0x2ec - 0x2fc */ + RK_U32 reserved187_191[5]; + + /* 0x00000300 reg192 */ + struct { + RK_U32 enc_stnd : 2; + RK_U32 cur_frm_ref : 1; + RK_U32 mei_stor : 1; + RK_U32 bs_scp : 1; + RK_U32 reserved : 3; + RK_U32 pic_qp : 6; + RK_U32 num_pic_tot_cur : 5; + RK_U32 log2_ctu_num : 5; + RK_U32 reserved1 : 6; + RK_U32 slen_fifo : 1; + RK_U32 rec_fbc_dis : 1; + } reg0192_enc_pic; + + + /* 0x304 */ + RK_U32 reserved_193; + + /* 0x00000308 reg194 */ + struct { + RK_U32 frame_id : 8; + RK_U32 reserved : 8; + RK_U32 ch_id : 2; + RK_U32 vrsp_rtn_en : 1; + RK_U32 reserved1 : 13; + } reg0194_dvbm_id; + + /* 0x0000030c reg195 */ + RK_U32 bsp_size; + + /* 0x00000310 reg196 */ + struct { + RK_U32 pic_wd8_m1 : 11; + RK_U32 reserved : 5; + RK_U32 pic_hd8_m1 : 11; + RK_U32 reserved1 : 5; + } reg0196_enc_rsl; + + /* 0x00000314 reg197 */ + struct { + RK_U32 pic_wfill : 6; + RK_U32 reserved : 10; + RK_U32 pic_hfill : 6; + RK_U32 reserved1 : 10; + } reg0197_src_fill; + + /* 0x00000318 reg198 */ + struct { + RK_U32 alpha_swap : 1; + RK_U32 rbuv_swap : 1; + RK_U32 src_cfmt : 4; + RK_U32 src_rcne : 1; + RK_U32 out_fmt : 1; + RK_U32 src_range_trns_en : 1; + RK_U32 src_range_trns_sel : 1; + RK_U32 chroma_ds_mode : 1; + RK_U32 reserved : 21; + } reg0198_src_fmt; + + /* 0x0000031c reg199 */ + struct { + RK_U32 csc_wgt_b2y : 9; + RK_U32 csc_wgt_g2y : 9; + RK_U32 csc_wgt_r2y : 9; + RK_U32 reserved : 5; + } reg0199_src_udfy; + + /* 0x00000320 reg200 */ + struct { + RK_U32 csc_wgt_b2u : 9; + RK_U32 csc_wgt_g2u : 9; + RK_U32 csc_wgt_r2u : 9; + RK_U32 reserved : 5; + } reg0200_src_udfu; + + /* 0x00000324 reg201 */ + struct { + RK_U32 csc_wgt_b2v : 9; + RK_U32 csc_wgt_g2v : 9; + RK_U32 csc_wgt_r2v : 9; + RK_U32 reserved : 5; + } reg0201_src_udfv; + + /* 0x00000328 reg202 */ + struct { + RK_U32 csc_ofst_v : 8; + RK_U32 csc_ofst_u : 8; + RK_U32 csc_ofst_y : 5; + RK_U32 reserved : 11; + } reg0202_src_udfo; + + /* 0x0000032c reg203 */ + struct { + RK_U32 reserved : 26; + RK_U32 src_mirr : 1; + RK_U32 src_rot : 2; + RK_U32 reserved1 : 3; + } reg0203_src_proc; + + /* 0x00000330 reg204 */ + struct { + RK_U32 pic_ofst_x : 14; + RK_U32 reserved : 2; + RK_U32 pic_ofst_y : 14; + RK_U32 reserved1 : 2; + } reg0204_pic_ofst; + + /* 0x00000334 reg205 */ + struct { + RK_U32 src_strd0 : 17; + RK_U32 reserved : 15; + } reg0205_src_strd0; + + /* 0x00000338 reg206 */ + struct { + RK_U32 src_strd1 : 16; + RK_U32 reserved : 16; + } reg0206_src_strd1; + + /* 0x0000033c reg207 */ + struct { + RK_U32 pp_corner_filter_strength : 2; + RK_U32 reserved : 2; + RK_U32 pp_edge_filter_strength : 2; + RK_U32 reserved1 : 2; + RK_U32 pp_internal_filter_strength : 2; + RK_U32 reserved2 : 22; + } reg0207_src_flt_cfg; + + /* 0x340 - 0x34c */ + RK_U32 reserved208_211[4]; + + /* 0x00000350 reg212 */ + struct { + RK_U32 rc_en : 1; + RK_U32 aq_en : 1; + RK_U32 aq_mode : 1; + RK_U32 reserved : 9; + RK_U32 rc_ctu_num : 20; + } reg212_rc_cfg; + + /* 0x00000354 reg213 */ + struct { + RK_U32 reserved : 16; + RK_U32 rc_qp_range : 4; + RK_U32 rc_max_qp : 6; + RK_U32 rc_min_qp : 6; + } reg213_rc_qp; + + /* 0x00000358 reg214 */ + struct { + RK_U32 ctu_ebit : 20; + RK_U32 reserved : 12; + } reg214_rc_tgt; + + /* 0x35c */ + RK_U32 reserved_215; + + /* 0x00000360 reg216 */ + struct { + RK_U32 sli_splt : 1; + RK_U32 sli_splt_mode : 1; + RK_U32 sli_splt_cpst : 1; + RK_U32 reserved : 12; + RK_U32 sli_flsh : 1; + RK_U32 sli_max_num_m1 : 15; + RK_U32 reserved1 : 1; + } reg0216_sli_splt; + + /* 0x00000364 reg217 */ + struct { + RK_U32 sli_splt_byte : 20; + RK_U32 reserved : 12; + } reg0217_sli_byte; + + /* 0x00000368 reg218 */ + struct { + RK_U32 sli_splt_cnum_m1 : 20; + RK_U32 reserved : 12; + } reg0218_sli_cnum; + + /* 0x0000036c reg219 */ + struct { + RK_U32 uvc_partition0_len : 12; + RK_U32 uvc_partition_len : 12; + RK_U32 uvc_skip_len : 6; + RK_U32 reserved : 2; + } reg0218_uvc_cfg; + + /* 0x00000370 reg220 */ + struct { + RK_U32 cime_srch_dwnh : 4; + RK_U32 cime_srch_uph : 4; + RK_U32 cime_srch_rgtw : 4; + RK_U32 cime_srch_lftw : 4; + RK_U32 dlt_frm_num : 16; + } reg0220_me_rnge; + + /* 0x00000374 reg221 */ + struct { + RK_U32 srgn_max_num : 7; + RK_U32 cime_dist_thre : 13; + RK_U32 rme_srch_h : 2; + RK_U32 rme_srch_v : 2; + RK_U32 rme_dis : 3; + RK_U32 reserved1 : 1; + RK_U32 fme_dis : 3; + RK_U32 reserved2 : 1; + } reg0221_me_cfg; + + /* 0x00000378 reg222 */ + struct { + RK_U32 cime_size_rama : 10; + RK_U32 reserved : 1; + RK_U32 cime_hgt_rama : 5; + RK_U32 reserved1 : 2; + RK_U32 cme_linebuf_w : 10; + RK_U32 fme_prefsu_en : 2; + RK_U32 colmv_stor : 1; + RK_U32 colmv_load : 1; + } reg0222_me_cach; + + + /* 0x37c - 0x39c */ + RK_U32 reserved223_231[9]; + + /* 0x000003a0 reg232 */ + struct { + RK_U32 ltm_col : 1; + RK_U32 ltm_idx0l0 : 1; + RK_U32 chrm_spcl : 1; + RK_U32 cu_inter_e : 12; + RK_U32 reserved : 4; + RK_U32 cu_intra_e : 4; + RK_U32 ccwa_e : 1; + RK_U32 scl_lst_sel : 2; + RK_U32 lambda_qp_use_avg_cu16_flag : 1; + RK_U32 yuvskip_calc_en : 1; + RK_U32 atf_e : 1; + RK_U32 atr_e : 1; + RK_U32 reserved1 : 2; + } reg0232_rdo_cfg; + + /* 0x000003a4 reg233 */ + struct { + RK_U32 rdo_mark_mode : 9; + RK_U32 reserved : 23; + } reg0233_iprd_csts; + + /* 0x3a8 - 0x3ac */ + RK_U32 reserved234_235[2]; + + /* 0x000003b0 reg236 */ + + struct { + RK_U32 nal_unit_type : 6; + RK_U32 reserved : 26; + } reg0236_synt_nal; + + /* 0x000003b4 reg237 */ + struct { + RK_U32 smpl_adpt_ofst_e : 1; + RK_U32 num_st_ref_pic : 7; + RK_U32 lt_ref_pic_prsnt : 1; + RK_U32 num_lt_ref_pic : 6; + RK_U32 tmpl_mvp_e : 1; + RK_U32 log2_max_poc_lsb : 4; + RK_U32 strg_intra_smth : 1; + RK_U32 reserved : 11; + } reg0237_synt_sps; + + /* 0x000003b8 reg238 */ + struct { + RK_U32 dpdnt_sli_seg_en : 1; + RK_U32 out_flg_prsnt_flg : 1; + RK_U32 num_extr_sli_hdr : 3; + RK_U32 sgn_dat_hid_en : 1; + RK_U32 cbc_init_prsnt_flg : 1; + RK_U32 pic_init_qp : 6; + RK_U32 cu_qp_dlt_en : 1; + RK_U32 chrm_qp_ofst_prsn : 1; + RK_U32 lp_fltr_acrs_sli : 1; + RK_U32 dblk_fltr_ovrd_en : 1; + RK_U32 lst_mdfy_prsnt_flg : 1; + RK_U32 sli_seg_hdr_extn : 1; + RK_U32 cu_qp_dlt_depth : 2; + RK_U32 lpf_fltr_acrs_til : 1; + RK_U32 reserved : 10; + } reg0238_synt_pps; + + /* 0x000003bc reg239 */ + struct { + RK_U32 cbc_init_flg : 1; + RK_U32 mvd_l1_zero_flg : 1; + RK_U32 mrg_up_flg : 1; + RK_U32 mrg_lft_flg : 1; + RK_U32 reserved : 1; + RK_U32 ref_pic_lst_mdf_l0 : 1; + RK_U32 num_refidx_l1_act : 2; + RK_U32 num_refidx_l0_act : 2; + RK_U32 num_refidx_act_ovrd : 1; + RK_U32 sli_sao_chrm_flg : 1; + RK_U32 sli_sao_luma_flg : 1; + RK_U32 sli_tmprl_mvp_e : 1; + RK_U32 pic_out_flg : 1; + RK_U32 sli_type : 2; + RK_U32 sli_rsrv_flg : 7; + RK_U32 dpdnt_sli_seg_flg : 1; + RK_U32 sli_pps_id : 6; + RK_U32 no_out_pri_pic : 1; + } reg0239_synt_sli0; + + /* 0x000003c0 reg240 */ + struct { + RK_U32 sp_tc_ofst_div2 : 4; + RK_U32 sp_beta_ofst_div2 : 4; + RK_U32 sli_lp_fltr_acrs_sli : 1; + RK_U32 sp_dblk_fltr_dis : 1; + RK_U32 dblk_fltr_ovrd_flg : 1; + RK_U32 sli_cb_qp_ofst : 5; + RK_U32 sli_qp : 6; + RK_U32 max_mrg_cnd : 2; + RK_U32 reserved : 1; + RK_U32 col_ref_idx : 1; + RK_U32 col_frm_l0_flg : 1; + RK_U32 lst_entry_l0 : 4; + RK_U32 reserved1 : 1; + } reg0240_synt_sli1; + + /* 0x000003c4 reg241 */ + struct { + RK_U32 sli_poc_lsb : 16; + RK_U32 sli_hdr_ext_len : 9; + RK_U32 reserved : 7; + } reg0241_synt_sli2; + + /* 0x000003c8 reg242 */ + + struct { + RK_U32 st_ref_pic_flg : 1; + RK_U32 poc_lsb_lt0 : 16; + RK_U32 lt_idx_sps : 5; + RK_U32 num_lt_pic : 2; + RK_U32 st_ref_pic_idx : 6; + RK_U32 num_lt_sps : 2; + } reg0242_synt_refm0; + + /* 0x000003cc reg243 */ + struct { + RK_U32 used_by_s0_flg : 4; + RK_U32 num_pos_pic : 1; + RK_U32 num_negative_pics : 5; + RK_U32 dlt_poc_msb_cycl0 : 16; + RK_U32 dlt_poc_msb_prsnt0 : 1; + RK_U32 dlt_poc_msb_prsnt1 : 1; + RK_U32 dlt_poc_msb_prsnt2 : 1; + RK_U32 used_by_lt_flg0 : 1; + RK_U32 used_by_lt_flg1 : 1; + RK_U32 used_by_lt_flg2 : 1; + } reg0243_synt_refm1; + + /* 0x000003d0 reg244 */ + struct { + RK_U32 dlt_poc_s0_m10 : 16; + RK_U32 dlt_poc_s0_m11 : 16; + } reg0244_synt_refm2; + /* 0x000003d4 reg245 */ + struct { + RK_U32 dlt_poc_s0_m12 : 16; + RK_U32 dlt_poc_s0_m13 : 16; + } reg0245_synt_refm3; + + /* 0x000003d8 reg246 */ + struct { + RK_U32 poc_lsb_lt1 : 16; + RK_U32 poc_lsb_lt2 : 16; + } reg0246_synt_long_refm0; + + /* 0x000003dc reg247 */ + struct { + RK_U32 dlt_poc_msb_cycl1 : 16; + RK_U32 dlt_poc_msb_cycl2 : 16; + } reg0247_synt_long_refm1; + + struct { + RK_U32 sao_lambda_multi : 3; + RK_U32 reserved : 29; + } reg0248_sao_cfg; + + /* 0x3e4 - 0x3ec */ + RK_U32 reserved249_251[3]; + + /* 0x000003f0 reg252 */ + struct { + RK_U32 tile_w_m1 : 8; + RK_U32 reserved : 8; + RK_U32 tile_h_m1 : 8; + RK_U32 reserved1 : 7; + RK_U32 tile_en : 1; + } reg0252_tile_cfg; + /* 0x000003f4 reg253 */ + struct { + RK_U32 tile_x : 8; + RK_U32 reserved : 8; + RK_U32 tile_y : 8; + RK_U32 reserved1 : 8; + } reg0253_tile_pos; + + /* 0x3f8 - 0x3fc */ + RK_U32 reserved254_255[2]; + + /* 0x00000400 reg256 - 0x00000480 reg288 */ + Vepu540cJpegReg jpegReg; + +} hevc_vepu540c_base; + +/* class: rc/roi/aq/klut */ +/* 0x00001000 reg1024 - 0x000010e0 reg1080 */ +typedef struct HevcVepu540cRcRoi_t { + /* 0x00001000 reg1024 */ + struct { + RK_U32 qp_adj0 : 5; + RK_U32 qp_adj1 : 5; + RK_U32 qp_adj2 : 5; + RK_U32 qp_adj3 : 5; + RK_U32 qp_adj4 : 5; + RK_U32 reserved : 7; + } rc_adj0; + + /* 0x00001004 reg1025 */ + struct { + RK_U32 qp_adj5 : 5; + RK_U32 qp_adj6 : 5; + RK_U32 qp_adj7 : 5; + RK_U32 qp_adj8 : 5; + RK_U32 reserved : 12; + } rc_adj1; + + /* 0x00001008 reg1026 - 0x00001028 reg1034 */ + RK_U32 rc_dthd_0_8[9]; + + /* 0x102c */ + RK_U32 reserved_1035; + + /* 0x00001030 reg1036 */ + struct { + RK_U32 qpmin_area0 : 6; + RK_U32 qpmax_area0 : 6; + RK_U32 qpmin_area1 : 6; + RK_U32 qpmax_area1 : 6; + RK_U32 qpmin_area2 : 6; + RK_U32 reserved : 2; + } roi_qthd0; + + /* 0x00001034 reg1037 */ + struct { + RK_U32 qpmax_area2 : 6; + RK_U32 qpmin_area3 : 6; + RK_U32 qpmax_area3 : 6; + RK_U32 qpmin_area4 : 6; + RK_U32 qpmax_area4 : 6; + RK_U32 reserved : 2; + } roi_qthd1; + + /* 0x00001038 reg1038 */ + struct { + RK_U32 qpmin_area5 : 6; + RK_U32 qpmax_area5 : 6; + RK_U32 qpmin_area6 : 6; + RK_U32 qpmax_area6 : 6; + RK_U32 qpmin_area7 : 6; + RK_U32 reserved : 2; + } roi_qthd2; + + /* 0x0000103c reg1039 */ + struct { + RK_U32 qpmax_area7 : 6; + RK_U32 reserved : 24; + RK_U32 qpmap_mode : 2; + } roi_qthd3; + + /* 0x00001040 reg1040 */ + RK_U32 reserved_1040; + + /* 0x00001044 reg1041 */ + struct { + RK_U32 aq_tthd0 : 8; + RK_U32 aq_tthd1 : 8; + RK_U32 aq_tthd2 : 8; + RK_U32 aq_tthd3 : 8; + } aq_tthd0; + + /* 0x00001048 reg1042 */ + struct { + RK_U32 aq_tthd4 : 8; + RK_U32 aq_tthd5 : 8; + RK_U32 aq_tthd6 : 8; + RK_U32 aq_tthd7 : 8; + } aq_tthd1; + + /* 0x0000104c reg1043 */ + struct { + RK_U32 aq_tthd8 : 8; + RK_U32 aq_tthd9 : 8; + RK_U32 aq_tthd10 : 8; + RK_U32 aq_tthd11 : 8; + } aq_tthd2; + + /* 0x00001050 reg1044 */ + struct { + RK_U32 aq_tthd12 : 8; + RK_U32 aq_tthd13 : 8; + RK_U32 aq_tthd14 : 8; + RK_U32 aq_tthd15 : 8; + } aq_tthd3; + + /* 0x00001054 reg1045 */ + struct { + RK_U32 aq_stp_s0 : 6; + RK_U32 reserved : 2; + RK_U32 aq_stp_0t1 : 6; + RK_U32 reserved1 : 2; + RK_U32 aq_stp_1t2 : 6; + RK_U32 reserved2 : 2; + RK_U32 aq_stp_2t3 : 6; + RK_U32 reserved3 : 2; + } aq_stp0; + + /* 0x00001058 reg1046 */ + struct { + RK_U32 aq_stp_3t4 : 6; + RK_U32 reserved : 2; + RK_U32 aq_stp_4t5 : 6; + RK_U32 reserved1 : 2; + RK_U32 aq_stp_5t6 : 6; + RK_U32 reserved2 : 2; + RK_U32 aq_stp_6t7 : 6; + RK_U32 reserved3 : 2; + } aq_stp1; + + /* 0x0000105c reg1047 */ + struct { + RK_U32 aq_stp_8t9 : 6; + RK_U32 reserved : 2; + RK_U32 aq_stp_9t10 : 6; + RK_U32 reserved1 : 2; + RK_U32 aq_stp_10t11 : 6; + RK_U32 reserved2 : 2; + RK_U32 aq_stp_11t12 : 6; + RK_U32 reserved3 : 2; + } aq_stp2; + + /* 0x00001060 reg1048 */ + struct { + RK_U32 aq_stp_12t13 : 6; + RK_U32 reserved : 2; + RK_U32 aq_stp_13t14 : 6; + RK_U32 reserved1 : 2; + RK_U32 aq_stp_14t15 : 6; + RK_U32 reserved2 : 2; + RK_U32 aq_stp_b15 : 6; + RK_U32 reserved3 : 2; + } aq_stp3; + + /* 0x00001064 reg1049 */ + struct { + RK_U32 madi_th0 : 8; + RK_U32 madi_th1 : 8; + RK_U32 madi_th2 : 8; + RK_U32 reserved : 8; + } madi_st_thd; + + /* 0x00001068 reg1050 */ + struct { + RK_U32 madp_th0 : 12; + RK_U32 reserved : 4; + RK_U32 madp_th1 : 12; + RK_U32 reserved1 : 4; + } madp_st_thd0; + + /* 0x0000106c reg1051 */ + struct { + RK_U32 madp_th2 : 12; + RK_U32 reserved : 20; + } madp_st_thd1; + + /* 0x1078 - 0x107c */ + RK_U32 reserved1052_1054[3]; + + /* 0x0000107c reg1055 */ + struct { + RK_U32 chrm_klut_ofst : 4; + RK_U32 reserved : 4; + RK_U32 inter_chrm_dist_multi : 6; + RK_U32 reserved1 : 18; + } klut_ofst; + + /*0x00001080 reg1056 - 0x0000110c reg1091 */ + Vepu540cRoiCfg roi_cfg; +} hevc_vepu540c_rc_roi; + +/* class: iprd/iprd_wgt/rdo_wgta/prei_dif*/ +/* 0x00001700 reg1472 - 0x00001cd4 reg1845 */ +typedef struct HevcVepu540cWgt_t { + /* 0x00001700 - 0x0000172c reg1472 */ + RK_U32 reserved1472_1483[12]; + + /* 0x00001730 reg1484 */ + struct { + RK_U32 qnt_bias_i : 10; + RK_U32 qnt_bias_p : 10; + RK_U32 reserved : 12; + } reg1484_qnt_bias_comb; + + /* 0x1734 - 0x175c */ + RK_U32 reserved1485_1495[11]; + + /* 0x00001760 reg1496 */ + struct { + RK_U32 cime_pmv_num : 1; + RK_U32 cime_fuse : 1; + RK_U32 itp_mode : 1; + RK_U32 reserved : 1; + RK_U32 move_lambda : 4; + RK_U32 rime_lvl_mrg : 2; + RK_U32 rime_prelvl_en : 2; + RK_U32 rime_prersu_en : 3; + RK_U32 reserved1 : 17; + } me_sqi_cfg; + + /* 0x00001764 reg1497 */ + struct { + RK_U32 cime_mvd_th0 : 9; + RK_U32 reserved : 1; + RK_U32 cime_mvd_th1 : 9; + RK_U32 reserved1 : 1; + RK_U32 cime_mvd_th2 : 9; + RK_U32 reserved2 : 3; + } cime_mvd_th; + + /* 0x00001768 reg1498 */ + struct { + RK_U32 cime_madp_th : 12; + RK_U32 reserved : 20; + } cime_madp_th; + + /* 0x0000176c reg1499 */ + struct { + RK_U32 cime_multi0 : 8; + RK_U32 cime_multi1 : 8; + RK_U32 cime_multi2 : 8; + RK_U32 cime_multi3 : 8; + } cime_multi; + + /* 0x00001770 reg1500 */ + struct { + RK_U32 rime_mvd_th0 : 3; + RK_U32 reserved : 1; + RK_U32 rime_mvd_th1 : 3; + RK_U32 reserved1 : 9; + RK_U32 fme_madp_th : 12; + RK_U32 reserved2 : 4; + } rime_mvd_th; + + /* 0x00001774 reg1501 */ + struct { + RK_U32 rime_madp_th0 : 12; + RK_U32 reserved : 4; + RK_U32 rime_madp_th1 : 12; + RK_U32 reserved1 : 4; + } rime_madp_th; + + /* 0x00001778 reg1502 */ + struct { + RK_U32 rime_multi0 : 10; + RK_U32 rime_multi1 : 10; + RK_U32 rime_multi2 : 10; + RK_U32 reserved : 2; + } rime_multi; + + /* 0x0000177c reg1503 */ + struct { + RK_U32 cmv_th0 : 8; + RK_U32 cmv_th1 : 8; + RK_U32 cmv_th2 : 8; + RK_U32 reserved : 8; + } cmv_st_th; + + /* 0x1780 - 0x17fc */ + RK_U32 reserved1504_1535[32]; + + /* 0x00001800 reg1536 */ + struct { + RK_U32 lambda_satd_offset : 5; + RK_U32 reserved : 27; + } iprd_lamb_satd_ofst; + + /* 0x1804 - 0x18fc */ + RK_U32 reserved1537_1599[63];; + + /* wgt_qp48_grpa */ + /* 0x00001900 reg1600 */ + RK_U32 rdo_wgta_qp_grpa_0_51[52]; + + /* 0x19d0 - 0x1ffc */ + RK_U32 reserved1652_2047[396]; +} hevc_vepu540c_wgt; + +typedef struct H265eV540cRegSet_t { + hevc_vepu540c_control_cfg reg_ctl; + hevc_vepu540c_base reg_base; + hevc_vepu540c_rc_roi reg_rc_roi; + hevc_vepu540c_wgt reg_wgt; + vepu540c_rdo_cfg reg_rdo; + vepu540c_scl_cfg reg_scl; + vepu540c_jpeg_tab jpeg_table; + vepu540c_dbg reg_dbg; +} H265eV540cRegSet; + +typedef struct H265eV540cStatusElem_t { + RK_U32 hw_status; + vepu540c_status st; +} H265eV540cStatusElem; + +#endif