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[h265d_hal]: Fix h265d cycle reg pos issue

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Change-Id: I21b26aa182dfd42e912b08ef6f742513699cef29
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>
This commit is contained in:
sayon.chen
2020-07-29 17:30:36 +08:00
committed by Herman Chen
parent 41dd3ea054
commit 95e7a230d2
2 changed files with 7 additions and 9 deletions
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12
mpp/hal/rkdec/h265d/hal_h265d_reg.c
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@@ -1680,6 +1680,7 @@ MPP_RET hal_h265d_gen_regs(void *hal, HalTaskInfo *syn)
RK_S32 aglin_offset = 0;
RK_S32 valid_ref = -1;
MppBuffer framebuf = NULL;
RK_U32 sw_ref_valid = 0;
if (syn->dec.flags.parse_err ||
syn->dec.flags.ref_err) {
@@ -1810,7 +1811,6 @@ MPP_RET hal_h265d_gen_regs(void *hal, HalTaskInfo *syn)
///find s->rps_model[i] position, and set register
hw_regs->sw_ref_valid = 0;
hw_regs->cabac_error_en = 0xfdfffffd;
hw_regs->rkv_reg_ends.extern_error_en = 0x30000000;
@@ -1829,16 +1829,16 @@ MPP_RET hal_h265d_gen_regs(void *hal, HalTaskInfo *syn)
} else {
hw_regs->sw_refer_base[i] = valid_ref;
}
hw_regs->sw_ref_valid |= (1 << i);
sw_ref_valid |= (1 << i);
} else {
hw_regs->sw_refer_base[i] = hw_regs->sw_decout_base;
}
}
hw_regs->sw_refer_base[0] |= ((hw_regs->sw_ref_valid & 0xf) << 10);
hw_regs->sw_refer_base[1] |= (((hw_regs->sw_ref_valid >> 4) & 0xf) << 10);
hw_regs->sw_refer_base[2] |= (((hw_regs->sw_ref_valid >> 8) & 0xf) << 10);
hw_regs->sw_refer_base[3] |= (((hw_regs->sw_ref_valid >> 12) & 0x7) << 10);
hw_regs->sw_refer_base[0] |= ((sw_ref_valid & 0xf) << 10);
hw_regs->sw_refer_base[1] |= (((sw_ref_valid >> 4) & 0xf) << 10);
hw_regs->sw_refer_base[2] |= (((sw_ref_valid >> 8) & 0xf) << 10);
hw_regs->sw_refer_base[3] |= (((sw_ref_valid >> 12) & 0x7) << 10);
return ret;
}

4
mpp/hal/rkdec/h265d/hal_h265d_reg.h
View File

@@ -48,7 +48,6 @@
extern RK_U32 h265h_debug;
typedef struct RKV_HEVC_REG_END {
RK_U32 reg_not_use0[RKVDEC_REG_PERF_CYCLE_INDEX - HEVC_DECODER_REG_NUM];
RK_U32 performance_cycle; //65
RK_U32 axi_ddr_rdata;
RK_U32 axi_ddr_wdata;
@@ -156,8 +155,7 @@ typedef struct {
RK_U32 reversed1 : 6;
} sao_ctu_position;
RK_U32 sw_ref_valid; //this is not same with hardware
RK_U32 sw_refframe_index[15]; //48
RK_U32 reg_not_use0[RKVDEC_REG_PERF_CYCLE_INDEX - HEVC_DECODER_REG_NUM];
union {
rkv_reg_end rkv_reg_ends;
v345_reg_end v345_reg_ends;