package/mpp
1
0
Fork 0
mirror of https://github.com/nyanmisaka/mpp.git synced 2025-10-29 11:42:05 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

[astyle]: formating code

Browse Source 
git-svn-id: https://10.10.10.66:8443/svn/MediaProcessPlatform/trunk/mpp@191 6e48237b-75ef-9749-8fc9-41990f28c85a
This commit is contained in:
ChenHengming
2008-01-25 14:48:06 +00:00
parent a94dc97f40
commit 95448ffabb
7 changed files with 333 additions and 377 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
mpp/codec/dec/h264/h264d_api.c
View File

@@ -32,20 +32,20 @@ MPP_RET h264d_init (void **decoder, MppParserInitCfg *init)
return MPP_OK;
return MPP_OK;
}
MPP_RET h264d_deinit (void *decoder)
{
return MPP_OK;
return MPP_OK;
}
MPP_RET h264d_reset (void *decoder)
{
return MPP_OK;
return MPP_OK;
}
@@ -53,7 +53,7 @@ MPP_RET h264d_flush (void *decoder)
{
return MPP_OK;
return MPP_OK;
}
@@ -61,24 +61,24 @@ MPP_RET h264d_control(void *decoder, RK_S32 cmd_type, void *param)
{
return MPP_OK;
return MPP_OK;
}
MPP_RET h264d_parser (void *decoder, MppPacket pkt, MppSyntax *syn)
{
return MPP_OK;
return MPP_OK;
}
const MppDecParser api_h264d_parser = {
"h264d",
MPP_VIDEO_CodingAVC,
0,
0,
h264d_init,
h264d_deinit,
h264d_parser,
h264d_reset,
h264d_flush,
h264d_control,
"h264d",
MPP_VIDEO_CodingAVC,
0,
0,
h264d_init,
h264d_deinit,
h264d_parser,
h264d_reset,
h264d_flush,
h264d_control,
};

4
mpp/codec/inc/h264d_api.h
View File

@@ -19,7 +19,7 @@
#include "mpp_dec.h"
#ifdef __cplusplus
#ifdef __cplusplus
extern "C" {
#endif
@@ -32,7 +32,7 @@ MPP_RET h264d_flush (void *decoder);
MPP_RET h264d_control(void *decoder, RK_S32 cmd_type, void *param);
MPP_RET h264d_parser (void *decoder, MppPacket pkt, MppSyntax *syn);
#ifdef __cplusplus
#ifdef __cplusplus
}
#endif

618
mpp/hal/inc/hal_h264d_api.h
View File

@@ -21,354 +21,308 @@
#include "mpp_hal.h"
typedef struct h264_mmu_t
{
RK_U32 mmu_dte_addr;
struct
{
RK_U32 pageing_enabled : 1;
RK_U32 page_fault_active : 1;
RK_U32 stail_active : 1;
RK_U32 mmu_idle : 1;
RK_U32 replay_buffer_empty1 : 1;
RK_U32 page_fault_is_write : 1;
RK_U32 page_fault_bus_id : 5;
RK_U32 reserve : 8;
//RK_U32 field0000 : 1;
}mmu_status;
struct
{
RK_U32 mmu_cmd : 3;
RK_U32 field0000 : 1;
}mmu_cmd;
typedef struct h264_mmu_t {
RK_U32 mmu_dte_addr;
struct {
RK_U32 pageing_enabled : 1;
RK_U32 page_fault_active : 1;
RK_U32 stail_active : 1;
RK_U32 mmu_idle : 1;
RK_U32 replay_buffer_empty1 : 1;
RK_U32 page_fault_is_write : 1;
RK_U32 page_fault_bus_id : 5;
RK_U32 reserve : 8;
//RK_U32 field0000 : 1;
} mmu_status;
struct {
RK_U32 mmu_cmd : 3;
RK_U32 field0000 : 1;
} mmu_cmd;
RK_U32 page_fault_addr;
RK_U32 mmu_zap_one_line;
struct int_rawstat
{
RK_U32 page_fault : 1;
RK_U32 read_bus_error : 1;
}raw_stat;
struct int_clear
{
RK_U32 page_fault : 1;
RK_U32 read_bus_error : 1;
}clear;
struct int_mask
{
RK_U32 page_fault : 1;
RK_U32 read_bus_error : 1;
}mask;
struct int_status
{
RK_U32 page_fault : 1;
RK_U32 read_bus_error : 1;
}status;
RK_U32 mmu_auto_gating : 1;
}H264_MMU_t;
RK_U32 page_fault_addr;
RK_U32 mmu_zap_one_line;
struct int_rawstat {
RK_U32 page_fault : 1;
RK_U32 read_bus_error : 1;
} raw_stat;
struct int_clear {
RK_U32 page_fault : 1;
RK_U32 read_bus_error : 1;
} clear;
struct int_mask {
RK_U32 page_fault : 1;
RK_U32 read_bus_error : 1;
} mask;
struct int_status {
RK_U32 page_fault : 1;
RK_U32 read_bus_error : 1;
} status;
RK_U32 mmu_auto_gating : 1;
} H264_MMU_t;
typedef struct h264_cache_t
{
struct st_version
{
RK_U32 version_minor : 8;
RK_U32 version_major : 8;
RK_U32 product_id : 16;
}version;
struct st_size
{
RK_U32 line_size : 8;
RK_U32 associativity : 8;
RK_U32 cache_size : 8;
RK_U32 external_bus_width : 8;
}size;
struct st_status
{
RK_U32 cmd_busy : 1;
RK_U32 data_busy : 1;
}status;
struct st_command
{
RK_U32 command : 4;
RK_U32 sw_addrb_sel : 2;
}command;
RK_U32 clear_page;
RK_U32 max_reads : 5;
struct st_enable
{
RK_U32 permit_cacheable_access : 1;
RK_U32 permit_cach_read_allocate : 1;
RK_U32 sw_readbuffer_counter_reject_en : 1;
RK_U32 sw_cache_clk_disgate : 1;
RK_U32 sw_cache_linsize : 1;
}enable;
RK_U32 perfcnt_src0;
RK_U32 perfcnt_val0;
RK_U32 perfcnt_src1;
RK_U32 perfcnt_val1;
}H264_CACHE_t;
typedef struct h264_cache_t {
struct st_version {
RK_U32 version_minor : 8;
RK_U32 version_major : 8;
RK_U32 product_id : 16;
} version;
struct st_size {
RK_U32 line_size : 8;
RK_U32 associativity : 8;
RK_U32 cache_size : 8;
RK_U32 external_bus_width : 8;
} size;
struct st_status {
RK_U32 cmd_busy : 1;
RK_U32 data_busy : 1;
} status;
struct st_command {
RK_U32 command : 4;
RK_U32 sw_addrb_sel : 2;
} command;
RK_U32 clear_page;
RK_U32 max_reads : 5;
struct st_enable {
RK_U32 permit_cacheable_access : 1;
RK_U32 permit_cach_read_allocate : 1;
RK_U32 sw_readbuffer_counter_reject_en : 1;
RK_U32 sw_cache_clk_disgate : 1;
RK_U32 sw_cache_linsize : 1;
} enable;
RK_U32 perfcnt_src0;
RK_U32 perfcnt_val0;
RK_U32 perfcnt_src1;
RK_U32 perfcnt_val1;
} H264_CACHE_t;
typedef struct h264_regs_t
{
struct
{
RK_U32 minor_ver : 8;
RK_U32 level : 1;
RK_U32 dec_support : 3;
RK_U32 profile : 1;
RK_U32 reserve0 : 1;
RK_U32 codec_flag : 1;
RK_U32 reserve1 : 1;
RK_U32 prod_num : 16;
}swreg0_id;
struct
{
RK_U32 sw_dec_e : 1;//0
RK_U32 sw_dec_clkgate_e : 1; // 1
RK_U32 reserve0 : 1;// 2
RK_U32 sw_timeout_mode : 1; // 3
RK_U32 sw_dec_irq_dis : 1;//4 // 4
RK_U32 sw_dec_timeout_e : 1; //5
RK_U32 sw_buf_empty_en : 1; // 6
RK_U32 sw_stmerror_waitdecfifo_empty : 1; // 7
RK_U32 sw_dec_irq : 1; // 8
RK_U32 sw_dec_irq_raw : 1; // 9
RK_U32 reserve2 : 2;
RK_U32 sw_dec_rdy_sta : 1; //12
RK_U32 sw_dec_bus_sta : 1; //13
RK_U32 sw_dec_error_sta : 1; // 14
RK_U32 sw_dec_timeout_sta : 1; //15
RK_U32 sw_dec_empty_sta : 1; // 16
RK_U32 sw_colmv_ref_error_sta : 1; // 17
RK_U32 sw_cabu_end_sta : 1; // 18
RK_U32 sw_h264orvp9_error_mode : 1; //19
RK_U32 sw_softrst_en_p : 1; //20
RK_U32 sw_force_softreset_valid : 1; //21
RK_U32 sw_softreset_rdy : 1; // 22
}swreg1_int;
struct
{
RK_U32 sw_in_endian : 1;
RK_U32 sw_in_swap32_e : 1;
RK_U32 sw_in_swap64_e : 1;
RK_U32 sw_str_endian : 1;
RK_U32 sw_str_swap32_e : 1;
RK_U32 sw_str_swap64_e : 1;
RK_U32 sw_out_endian : 1;
RK_U32 sw_out_swap32_e : 1;
RK_U32 sw_out_cbcr_swap : 1;
RK_U32 reserve0 : 1;
RK_U32 sw_rlc_mode_direct_write : 1;
RK_U32 sw_rlc_mode : 1;
RK_U32 sw_strm_start_bit : 7;
RK_U32 reserve1 : 1;
RK_U32 sw_dec_mode : 2;
RK_U32 reserve2 : 2;
RK_U32 sw_h264_rps_mode : 1;
RK_U32 sw_h264_stream_mode : 1;
RK_U32 sw_h264_stream_lastpacket : 1;
RK_U32 sw_h264_firstslice_flag : 1;
RK_U32 sw_h264_frame_orslice : 1;
RK_U32 sw_buspr_slot_disable : 1;
}swreg2_sysctrl;
struct
{
RK_U32 sw_y_hor_virstride : 9;
RK_U32 reserve : 2;
RK_U32 sw_slice_num_highbit : 1;
RK_U32 sw_uv_hor_virstride : 9;
RK_U32 sw_slice_num_lowbits : 11;
}swreg3_picpar;
struct
{
RK_U32 reverse0 : 4;
RK_U32 sw_strm_rlc_base : 28;
}swreg4_strm_rlc_base;
struct
{
RK_U32 sw_stream_len : 27;
}swreg5_stream_rlc_len;
struct
{
RK_U32 reverse0 : 4;
RK_U32 sw_cabactbl_base : 28;
}swreg6_cabactbl_prob_base;
struct
{
RK_U32 reverse0 : 4;
RK_U32 sw_decout_base : 28;
}swreg7_decout_base;
struct
{
RK_U32 sw_y_virstride : 20;
}swreg8_y_virstride;
struct
{
RK_U32 sw_yuv_virstride : 21;
}swreg9_yuv_virstride;
struct
{
RK_U32 sw_ref_field : 1;
RK_U32 sw_ref_topfield_used : 1;
RK_U32 sw_ref_botfield_used : 1;
RK_U32 sw_ref_colmv_use_flag : 1;
RK_U32 sw_refer_base : 28;
}swreg10_24_refer0_14_base[15];
RK_U32 swreg25_39_refer0_14_poc[15];
struct
{
RK_U32 sw_cur_poc : 32;
}swreg40_cur_poc;
struct
{
RK_U32 reserve : 3;
RK_U32 sw_rlcwrite_base : 29;
}swreg41_rlcwrite_base;
struct
{
RK_U32 reserve : 4;
RK_U32 sw_pps_base : 28;
}swreg42_pps_base;
struct swreg_sw_rps_base
{
RK_U32 reserve : 4;
RK_U32 sw_rps_base : 28;
}swreg43_rps_base;
struct swreg_strmd_error_e
{
RK_U32 sw_strmd_error_e : 28;
RK_U32 reserve : 4;
}swreg44_strmd_error_en;
struct
{
RK_U32 sw_strmd_error_status : 28;
RK_U32 sw_colmv_error_ref_picidx : 4;
}swreg45_strmd_error_status;
struct
{
RK_U32 sw_strmd_error_ctu_xoffset : 8;
RK_U32 sw_strmd_error_ctu_yoffset : 8;
RK_U32 sw_streamfifo_space2full : 7;
RK_U32 reserve : 1;
RK_U32 sw_vp9_error_ctu0_en : 1;
}swreg46_strmd_error_ctu;
struct
{
RK_U32 sw_saowr_xoffet : 9;
RK_U32 reserve : 7;
RK_U32 sw_saowr_yoffset : 10;
}swreg47_sao_ctu_position;
struct
{
RK_U32 sw_ref_field : 1;
RK_U32 sw_ref_topfield_used : 1;
RK_U32 sw_ref_botfield_used : 1;
RK_U32 sw_ref_colmv_use_flag : 1;
RK_U32 sw_refer_base : 28;
}swreg48_refer15_base;
RK_U32 swreg49_63_refer15_29_poc[15];
struct
{
RK_U32 sw_performance_cycle : 32;
}swreg64_performance_cycle;
struct
{
RK_U32 sw_axi_ddr_rdata : 32;
}swreg65_axi_ddr_rdata;
struct
{
RK_U32 sw_axi_ddr_rdata : 32;
}swreg66_axi_ddr_wdata;
struct
{
RK_U32 sw_busifd_resetn : 1;
RK_U32 sw_cabac_resetn : 1;
RK_U32 sw_dec_ctrl_resetn : 1;
RK_U32 sw_transd_resetn : 1;
RK_U32 sw_intra_resetn : 1;
RK_U32 sw_inter_resetn : 1;
RK_U32 sw_recon_resetn : 1;
RK_U32 sw_filer_resetn : 1;
}swreg67_fpgadebug_reset;
struct
{
RK_U32 perf_cnt0_sel : 6;
RK_U32 reserve0 : 2;
RK_U32 perf_cnt1_sel : 6;
RK_U32 reserve1 : 2;
RK_U32 perf_cnt2_sel : 6;
}swreg68_performance_sel;
struct
{
RK_U32 perf_cnt0 : 32;
}swreg69_performance_cnt0;
struct
{
RK_U32 perf_cnt1 : 32;
}swreg70_performance_cnt1;
struct
{
RK_U32 perf_cnt2 : 32;
}swreg71_performance_cnt2;
RK_U32 swreg72_refer30_poc;
RK_U32 swreg73_refer31_poc;
struct
{
RK_U32 sw_h264_cur_poc1 : 32;
}swreg74_h264_cur_poc1;
struct
{
RK_U32 reserve : 4;
RK_U32 sw_errorinfo_base : 28;
}swreg75_h264_errorinfo_base;
struct
{
RK_U32 sw_slicedec_num : 14;
RK_U32 reserve : 1;
RK_U32 sw_strmd_detect_error_flag : 1;
RK_U32 sw_error_packet_num : 14;
}swreg76_h264_errorinfo_num;
struct
{
RK_U32 sw_h264_error_en_highbits : 30;
RK_U32 reserve : 2;
}swreg77_h264_error_e;
RK_U32 compare_len;
}H264_REGS_t;
typedef struct h264_regs_t {
struct {
RK_U32 minor_ver : 8;
RK_U32 level : 1;
RK_U32 dec_support : 3;
RK_U32 profile : 1;
RK_U32 reserve0 : 1;
RK_U32 codec_flag : 1;
RK_U32 reserve1 : 1;
RK_U32 prod_num : 16;
} swreg0_id;
struct {
RK_U32 sw_dec_e : 1;//0
RK_U32 sw_dec_clkgate_e : 1; // 1
RK_U32 reserve0 : 1;// 2
RK_U32 sw_timeout_mode : 1; // 3
RK_U32 sw_dec_irq_dis : 1;//4 // 4
RK_U32 sw_dec_timeout_e : 1; //5
RK_U32 sw_buf_empty_en : 1; // 6
RK_U32 sw_stmerror_waitdecfifo_empty : 1; // 7
RK_U32 sw_dec_irq : 1; // 8
RK_U32 sw_dec_irq_raw : 1; // 9
RK_U32 reserve2 : 2;
RK_U32 sw_dec_rdy_sta : 1; //12
RK_U32 sw_dec_bus_sta : 1; //13
RK_U32 sw_dec_error_sta : 1; // 14
RK_U32 sw_dec_timeout_sta : 1; //15
RK_U32 sw_dec_empty_sta : 1; // 16
RK_U32 sw_colmv_ref_error_sta : 1; // 17
RK_U32 sw_cabu_end_sta : 1; // 18
RK_U32 sw_h264orvp9_error_mode : 1; //19
RK_U32 sw_softrst_en_p : 1; //20
RK_U32 sw_force_softreset_valid : 1; //21
RK_U32 sw_softreset_rdy : 1; // 22
} swreg1_int;
struct {
RK_U32 sw_in_endian : 1;
RK_U32 sw_in_swap32_e : 1;
RK_U32 sw_in_swap64_e : 1;
RK_U32 sw_str_endian : 1;
RK_U32 sw_str_swap32_e : 1;
RK_U32 sw_str_swap64_e : 1;
RK_U32 sw_out_endian : 1;
RK_U32 sw_out_swap32_e : 1;
RK_U32 sw_out_cbcr_swap : 1;
RK_U32 reserve0 : 1;
RK_U32 sw_rlc_mode_direct_write : 1;
RK_U32 sw_rlc_mode : 1;
RK_U32 sw_strm_start_bit : 7;
RK_U32 reserve1 : 1;
RK_U32 sw_dec_mode : 2;
RK_U32 reserve2 : 2;
RK_U32 sw_h264_rps_mode : 1;
RK_U32 sw_h264_stream_mode : 1;
RK_U32 sw_h264_stream_lastpacket : 1;
RK_U32 sw_h264_firstslice_flag : 1;
RK_U32 sw_h264_frame_orslice : 1;
RK_U32 sw_buspr_slot_disable : 1;
} swreg2_sysctrl;
struct {
RK_U32 sw_y_hor_virstride : 9;
RK_U32 reserve : 2;
RK_U32 sw_slice_num_highbit : 1;
RK_U32 sw_uv_hor_virstride : 9;
RK_U32 sw_slice_num_lowbits : 11;
} swreg3_picpar;
struct {
RK_U32 reverse0 : 4;
RK_U32 sw_strm_rlc_base : 28;
} swreg4_strm_rlc_base;
struct {
RK_U32 sw_stream_len : 27;
} swreg5_stream_rlc_len;
struct {
RK_U32 reverse0 : 4;
RK_U32 sw_cabactbl_base : 28;
} swreg6_cabactbl_prob_base;
struct {
RK_U32 reverse0 : 4;
RK_U32 sw_decout_base : 28;
} swreg7_decout_base;
struct {
RK_U32 sw_y_virstride : 20;
} swreg8_y_virstride;
struct {
RK_U32 sw_yuv_virstride : 21;
} swreg9_yuv_virstride;
struct {
RK_U32 sw_ref_field : 1;
RK_U32 sw_ref_topfield_used : 1;
RK_U32 sw_ref_botfield_used : 1;
RK_U32 sw_ref_colmv_use_flag : 1;
RK_U32 sw_refer_base : 28;
} swreg10_24_refer0_14_base[15];
RK_U32 swreg25_39_refer0_14_poc[15];
struct {
RK_U32 sw_cur_poc : 32;
} swreg40_cur_poc;
struct {
RK_U32 reserve : 3;
RK_U32 sw_rlcwrite_base : 29;
} swreg41_rlcwrite_base;
struct {
RK_U32 reserve : 4;
RK_U32 sw_pps_base : 28;
} swreg42_pps_base;
struct swreg_sw_rps_base {
RK_U32 reserve : 4;
RK_U32 sw_rps_base : 28;
} swreg43_rps_base;
struct swreg_strmd_error_e {
RK_U32 sw_strmd_error_e : 28;
RK_U32 reserve : 4;
} swreg44_strmd_error_en;
struct {
RK_U32 sw_strmd_error_status : 28;
RK_U32 sw_colmv_error_ref_picidx : 4;
} swreg45_strmd_error_status;
struct {
RK_U32 sw_strmd_error_ctu_xoffset : 8;
RK_U32 sw_strmd_error_ctu_yoffset : 8;
RK_U32 sw_streamfifo_space2full : 7;
RK_U32 reserve : 1;
RK_U32 sw_vp9_error_ctu0_en : 1;
} swreg46_strmd_error_ctu;
struct {
RK_U32 sw_saowr_xoffet : 9;
RK_U32 reserve : 7;
RK_U32 sw_saowr_yoffset : 10;
} swreg47_sao_ctu_position;
struct {
RK_U32 sw_ref_field : 1;
RK_U32 sw_ref_topfield_used : 1;
RK_U32 sw_ref_botfield_used : 1;
RK_U32 sw_ref_colmv_use_flag : 1;
RK_U32 sw_refer_base : 28;
} swreg48_refer15_base;
RK_U32 swreg49_63_refer15_29_poc[15];
struct {
RK_U32 sw_performance_cycle : 32;
} swreg64_performance_cycle;
struct {
RK_U32 sw_axi_ddr_rdata : 32;
} swreg65_axi_ddr_rdata;
struct {
RK_U32 sw_axi_ddr_rdata : 32;
} swreg66_axi_ddr_wdata;
struct {
RK_U32 sw_busifd_resetn : 1;
RK_U32 sw_cabac_resetn : 1;
RK_U32 sw_dec_ctrl_resetn : 1;
RK_U32 sw_transd_resetn : 1;
RK_U32 sw_intra_resetn : 1;
RK_U32 sw_inter_resetn : 1;
RK_U32 sw_recon_resetn : 1;
RK_U32 sw_filer_resetn : 1;
} swreg67_fpgadebug_reset;
struct {
RK_U32 perf_cnt0_sel : 6;
RK_U32 reserve0 : 2;
RK_U32 perf_cnt1_sel : 6;
RK_U32 reserve1 : 2;
RK_U32 perf_cnt2_sel : 6;
} swreg68_performance_sel;
struct {
RK_U32 perf_cnt0 : 32;
} swreg69_performance_cnt0;
struct {
RK_U32 perf_cnt1 : 32;
} swreg70_performance_cnt1;
struct {
RK_U32 perf_cnt2 : 32;
} swreg71_performance_cnt2;
RK_U32 swreg72_refer30_poc;
RK_U32 swreg73_refer31_poc;
struct {
RK_U32 sw_h264_cur_poc1 : 32;
} swreg74_h264_cur_poc1;
struct {
RK_U32 reserve : 4;
RK_U32 sw_errorinfo_base : 28;
} swreg75_h264_errorinfo_base;
struct {
RK_U32 sw_slicedec_num : 14;
RK_U32 reserve : 1;
RK_U32 sw_strmd_detect_error_flag : 1;
RK_U32 sw_error_packet_num : 14;
} swreg76_h264_errorinfo_num;
struct {
RK_U32 sw_h264_error_en_highbits : 30;
RK_U32 reserve : 2;
} swreg77_h264_error_e;
RK_U32 compare_len;
} H264_REGS_t;
//typedef struct hal_h264d_logctx_t
//{
// struct rkv_log_flag_t *log_flag;
// struct rkv_log_ctx_t *spspps;
// struct rkv_log_ctx_t *rps;
// struct rkv_log_ctx_t *scanlist;
// struct rkv_log_ctx_t *sodb;
// struct rkv_log_ctx_t *reg;
// struct rkv_log_ctx_t *driver; // fwrite
// struct rkv_log_ctx_t *runlog; // fprintf
// struct rkv_log_flag_t *log_flag;
// struct rkv_log_ctx_t *spspps;
// struct rkv_log_ctx_t *rps;
// struct rkv_log_ctx_t *scanlist;
// struct rkv_log_ctx_t *sodb;
// struct rkv_log_ctx_t *reg;
// struct rkv_log_ctx_t *driver; // fwrite
// struct rkv_log_ctx_t *runlog; // fprintf
//
//}HAL_H264dLogCtx_t;
//typedef struct hal_h264d_initctx_t
//{
// HAL_H264dLogCtx_t *logctx;
// HAL_H264dLogCtx_t *logctx;
//}HAL_H264dInitCtx_t;
//
//
//typedef struct hal_h264d_inctx_t
//{
// struct h264d_syntax_t *syn;
// struct h264d_syntax_t *syn;
//
//}HAL_H264dInCtx_t;
//
//typedef struct hal_h264d_outctx_t
//{
// H264_REGS_t *reg;
// H264_MMU_t *mmu;
// H264_CACHE_t *cache;
// H264_REGS_t *reg;
// H264_MMU_t *mmu;
// H264_CACHE_t *cache;
//
//}HAL_H264dOutCtx_t;
@@ -378,14 +332,14 @@ extern const MppHalApi api_h264d_hal;
extern "C" {
#endif
MPP_RET hal_h264d_init (void **hal, MppHalCfg *cfg);
MPP_RET hal_h264d_deinit (void *hal);
MPP_RET hal_h264d_gen_regs(void *hal, MppSyntax *syn);
MPP_RET hal_h264d_start (void *hal, MppHalDecTask task);
MPP_RET hal_h264d_wait (void *hal, MppHalDecTask task);
MPP_RET hal_h264d_reset (void *hal);
MPP_RET hal_h264d_flush (void *hal);
MPP_RET hal_h264d_control (void *hal, RK_S32 cmd_type, void *param);
MPP_RET hal_h264d_init (void **hal, MppHalCfg *cfg);
MPP_RET hal_h264d_deinit (void *hal);
MPP_RET hal_h264d_gen_regs(void *hal, MppSyntax *syn);
MPP_RET hal_h264d_start (void *hal, MppHalDecTask task);
MPP_RET hal_h264d_wait (void *hal, MppHalDecTask task);
MPP_RET hal_h264d_reset (void *hal);
MPP_RET hal_h264d_flush (void *hal);
MPP_RET hal_h264d_control (void *hal, RK_S32 cmd_type, void *param);

34
mpp/hal/rkdec/h264d/hal_h264d_api.c
View File

@@ -21,54 +21,54 @@
MPP_RET hal_h264d_init (void **hal, MppHalCfg *cfg)
{
return MPP_OK;
return MPP_OK;
}
MPP_RET hal_h264d_deinit (void *hal)
{
return MPP_OK;
return MPP_OK;
}
MPP_RET hal_h264d_gen_regs(void *hal, MppSyntax *syn)
{
return MPP_OK;
return MPP_OK;
}
MPP_RET hal_h264d_start (void *hal, MppHalDecTask task)
{
return MPP_OK;
return MPP_OK;
}
MPP_RET hal_h264d_wait (void *hal, MppHalDecTask task)
{
return MPP_OK;
return MPP_OK;
}
MPP_RET hal_h264d_reset (void *hal)
{
return MPP_OK;
return MPP_OK;
}
MPP_RET hal_h264d_flush (void *hal)
{
return MPP_OK;
return MPP_OK;
}
MPP_RET hal_h264d_control (void *hal, RK_S32 cmd_type, void *param)
{
return MPP_OK;
return MPP_OK;
}
const MppHalApi api_h264d_hal = {
0,
hal_h264d_init,
hal_h264d_deinit,
hal_h264d_gen_regs,
hal_h264d_start,
hal_h264d_wait,
hal_h264d_reset,
hal_h264d_flush,
hal_h264d_control,
0,
hal_h264d_init,
hal_h264d_deinit,
hal_h264d_gen_regs,
hal_h264d_start,
hal_h264d_wait,
hal_h264d_reset,
hal_h264d_flush,
hal_h264d_control,
};

9
mpp/mpi_impl.h
View File

@@ -25,11 +25,12 @@
#define mpi_dbg(flag, fmt, ...) _mpp_dbg(mpi_debug, flag, fmt, ## __VA_ARGS__)
#define mpi_dbg_f(flag, fmt, ...) _mpp_dbg_f(mpi_debug, flag, fmt, ## __VA_ARGS__)
#define MPI_FUNCTION_ENTER() mpi_dbg(MPI_DBG_FUNCTION, "%s enter\n", __FUNCTION__)
#define MPI_FUNCTION_LEAVE() mpi_dbg(MPI_DBG_FUNCTION, "%s leave\n", __FUNCTION__)
#define MPI_FUNCTION_LEAVE_OK() mpi_dbg(MPI_DBG_FUNCTION, "%s success\n", __FUNCTION__)
#define MPI_FUNCTION_LEAVE_FAIL() mpi_dbg(MPI_DBG_FUNCTION, "%s failed\n", __FUNCTION__)
#define MPI_FUNCTION_ENTER() mpi_dbg_f(MPI_DBG_FUNCTION, "enter\n")
#define MPI_FUNCTION_LEAVE() mpi_dbg_f(MPI_DBG_FUNCTION, "leave\n")
#define MPI_FUNCTION_LEAVE_OK() mpi_dbg_f(MPI_DBG_FUNCTION, "success\n")
#define MPI_FUNCTION_LEAVE_FAIL() mpi_dbg_f(MPI_DBG_FUNCTION, "failed\n")
typedef struct MpiImpl_t MpiImpl;

4
mpp/mpp_buffer.cpp
View File

@@ -166,7 +166,7 @@ MPP_RET mpp_buffer_group_get(const char *tag, MppBufferMode mode,
mode >= MPP_BUFFER_MODE_BUTT ||
type >= MPP_BUFFER_TYPE_BUTT) {
mpp_err_f("input invalid group %p mode %d type %d\n",
group, mode, type);
group, mode, type);
return MPP_ERR_UNKNOW;
}
@@ -187,7 +187,7 @@ MPP_RET mpp_buffer_group_limit_config(MppBufferGroup group, size_t size, RK_S32
{
if (NULL == group || 0 == size || count <= 0) {
mpp_err_f("input invalid group %p size %d count %d\n",
group, size, count);
group, size, count);
return MPP_NOK;
}

9
mpp/mpp_buffer_impl.h
View File

@@ -24,11 +24,12 @@
#define MPP_BUF_DBG_FUNCTION (0x00000001)
#define mpp_buf_dbg(flag, fmt, ...) _mpp_dbg(mpp_buffer_debug, flag, fmt, ## __VA_ARGS__)
#define mpp_buf_dbg_f(flag, fmt, ...) _mpp_dbg(mpp_buffer_debug, flag, fmt, ## __VA_ARGS__)
#define MPP_BUF_FUNCTION_ENTER() mpp_buf_dbg(MPP_BUF_DBG_FUNCTION, "%s enter\n", __FUNCTION__)
#define MPP_BUF_FUNCTION_LEAVE() mpp_buf_dbg(MPP_BUF_DBG_FUNCTION, "%s leave\n", __FUNCTION__)
#define MPP_BUF_FUNCTION_LEAVE_OK() mpp_buf_dbg(MPP_BUF_DBG_FUNCTION, "%s success\n", __FUNCTION__)
#define MPP_BUF_FUNCTION_LEAVE_FAIL() mpp_buf_dbg(MPP_BUF_DBG_FUNCTION, "%s failed\n", __FUNCTION__)
#define MPP_BUF_FUNCTION_ENTER() mpp_buf_dbg_f(MPP_BUF_DBG_FUNCTION, "enter\n")
#define MPP_BUF_FUNCTION_LEAVE() mpp_buf_dbg_f(MPP_BUF_DBG_FUNCTION, "leave\n")
#define MPP_BUF_FUNCTION_LEAVE_OK() mpp_buf_dbg_f(MPP_BUF_DBG_FUNCTION, "success\n")
#define MPP_BUF_FUNCTION_LEAVE_FAIL() mpp_buf_dbg_f(MPP_BUF_DBG_FUNCTION, "failed\n")
typedef struct MppBufferImpl_t MppBufferImpl;
typedef struct MppBufferGroupImpl_t MppBufferGroupImpl;