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[astyle]: formating code

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git-svn-id: https://10.10.10.66:8443/svn/MediaProcessPlatform/trunk/mpp@191 6e48237b-75ef-9749-8fc9-41990f28c85a
This commit is contained in:
ChenHengming
2008-01-25 14:48:06 +00:00
parent a94dc97f40
commit 95448ffabb
7 changed files with 333 additions and 377 deletions
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246
mpp/hal/inc/hal_h264d_api.h
View File

@@ -21,11 +21,9 @@
#include "mpp_hal.h" #include "mpp_hal.h"
typedef struct h264_mmu_t typedef struct h264_mmu_t {
{
RK_U32 mmu_dte_addr; RK_U32 mmu_dte_addr;
struct struct {
{
RK_U32 pageing_enabled : 1; RK_U32 pageing_enabled : 1;
RK_U32 page_fault_active : 1; RK_U32 page_fault_active : 1;
RK_U32 stail_active : 1; RK_U32 stail_active : 1;
@@ -35,83 +33,70 @@ typedef struct h264_mmu_t
RK_U32 page_fault_bus_id : 5; RK_U32 page_fault_bus_id : 5;
RK_U32 reserve : 8; RK_U32 reserve : 8;
//RK_U32 field0000 : 1; //RK_U32 field0000 : 1;
}mmu_status; } mmu_status;
struct struct {
{
RK_U32 mmu_cmd : 3; RK_U32 mmu_cmd : 3;
RK_U32 field0000 : 1; RK_U32 field0000 : 1;
}mmu_cmd; } mmu_cmd;
RK_U32 page_fault_addr; RK_U32 page_fault_addr;
RK_U32 mmu_zap_one_line; RK_U32 mmu_zap_one_line;
struct int_rawstat struct int_rawstat {
{
RK_U32 page_fault : 1; RK_U32 page_fault : 1;
RK_U32 read_bus_error : 1; RK_U32 read_bus_error : 1;
}raw_stat; } raw_stat;
struct int_clear struct int_clear {
{
RK_U32 page_fault : 1; RK_U32 page_fault : 1;
RK_U32 read_bus_error : 1; RK_U32 read_bus_error : 1;
}clear; } clear;
struct int_mask struct int_mask {
{
RK_U32 page_fault : 1; RK_U32 page_fault : 1;
RK_U32 read_bus_error : 1; RK_U32 read_bus_error : 1;
}mask; } mask;
struct int_status struct int_status {
{
RK_U32 page_fault : 1; RK_U32 page_fault : 1;
RK_U32 read_bus_error : 1; RK_U32 read_bus_error : 1;
}status; } status;
RK_U32 mmu_auto_gating : 1; RK_U32 mmu_auto_gating : 1;
}H264_MMU_t; } H264_MMU_t;
typedef struct h264_cache_t typedef struct h264_cache_t {
{ struct st_version {
struct st_version
{
RK_U32 version_minor : 8; RK_U32 version_minor : 8;
RK_U32 version_major : 8; RK_U32 version_major : 8;
RK_U32 product_id : 16; RK_U32 product_id : 16;
}version; } version;
struct st_size struct st_size {
{
RK_U32 line_size : 8; RK_U32 line_size : 8;
RK_U32 associativity : 8; RK_U32 associativity : 8;
RK_U32 cache_size : 8; RK_U32 cache_size : 8;
RK_U32 external_bus_width : 8; RK_U32 external_bus_width : 8;
}size; } size;
struct st_status struct st_status {
{
RK_U32 cmd_busy : 1; RK_U32 cmd_busy : 1;
RK_U32 data_busy : 1; RK_U32 data_busy : 1;
}status; } status;
struct st_command struct st_command {
{
RK_U32 command : 4; RK_U32 command : 4;
RK_U32 sw_addrb_sel : 2; RK_U32 sw_addrb_sel : 2;
}command; } command;
RK_U32 clear_page; RK_U32 clear_page;
RK_U32 max_reads : 5; RK_U32 max_reads : 5;
struct st_enable struct st_enable {
{
RK_U32 permit_cacheable_access : 1; RK_U32 permit_cacheable_access : 1;
RK_U32 permit_cach_read_allocate : 1; RK_U32 permit_cach_read_allocate : 1;
RK_U32 sw_readbuffer_counter_reject_en : 1; RK_U32 sw_readbuffer_counter_reject_en : 1;
RK_U32 sw_cache_clk_disgate : 1; RK_U32 sw_cache_clk_disgate : 1;
RK_U32 sw_cache_linsize : 1; RK_U32 sw_cache_linsize : 1;
}enable; } enable;
RK_U32 perfcnt_src0; RK_U32 perfcnt_src0;
RK_U32 perfcnt_val0; RK_U32 perfcnt_val0;
RK_U32 perfcnt_src1; RK_U32 perfcnt_src1;
RK_U32 perfcnt_val1; RK_U32 perfcnt_val1;
}H264_CACHE_t; } H264_CACHE_t;
typedef struct h264_regs_t typedef struct h264_regs_t {
{ struct {
struct
{
RK_U32 minor_ver : 8; RK_U32 minor_ver : 8;
RK_U32 level : 1; RK_U32 level : 1;
RK_U32 dec_support : 3; RK_U32 dec_support : 3;
@@ -120,9 +105,8 @@ typedef struct h264_regs_t
RK_U32 codec_flag : 1; RK_U32 codec_flag : 1;
RK_U32 reserve1 : 1; RK_U32 reserve1 : 1;
RK_U32 prod_num : 16; RK_U32 prod_num : 16;
}swreg0_id; } swreg0_id;
struct struct {
{
RK_U32 sw_dec_e : 1;//0 RK_U32 sw_dec_e : 1;//0
RK_U32 sw_dec_clkgate_e : 1; // 1 RK_U32 sw_dec_clkgate_e : 1; // 1
RK_U32 reserve0 : 1;// 2 RK_U32 reserve0 : 1;// 2
@@ -145,9 +129,8 @@ typedef struct h264_regs_t
RK_U32 sw_softrst_en_p : 1; //20 RK_U32 sw_softrst_en_p : 1; //20
RK_U32 sw_force_softreset_valid : 1; //21 RK_U32 sw_force_softreset_valid : 1; //21
RK_U32 sw_softreset_rdy : 1; // 22 RK_U32 sw_softreset_rdy : 1; // 22
}swreg1_int; } swreg1_int;
struct struct {
{
RK_U32 sw_in_endian : 1; RK_U32 sw_in_endian : 1;
RK_U32 sw_in_swap32_e : 1; RK_U32 sw_in_swap32_e : 1;
RK_U32 sw_in_swap64_e : 1; RK_U32 sw_in_swap64_e : 1;
@@ -170,117 +153,96 @@ typedef struct h264_regs_t
RK_U32 sw_h264_firstslice_flag : 1; RK_U32 sw_h264_firstslice_flag : 1;
RK_U32 sw_h264_frame_orslice : 1; RK_U32 sw_h264_frame_orslice : 1;
RK_U32 sw_buspr_slot_disable : 1; RK_U32 sw_buspr_slot_disable : 1;
}swreg2_sysctrl; } swreg2_sysctrl;
struct struct {
{
RK_U32 sw_y_hor_virstride : 9; RK_U32 sw_y_hor_virstride : 9;
RK_U32 reserve : 2; RK_U32 reserve : 2;
RK_U32 sw_slice_num_highbit : 1; RK_U32 sw_slice_num_highbit : 1;
RK_U32 sw_uv_hor_virstride : 9; RK_U32 sw_uv_hor_virstride : 9;
RK_U32 sw_slice_num_lowbits : 11; RK_U32 sw_slice_num_lowbits : 11;
}swreg3_picpar; } swreg3_picpar;
struct struct {
{
RK_U32 reverse0 : 4; RK_U32 reverse0 : 4;
RK_U32 sw_strm_rlc_base : 28; RK_U32 sw_strm_rlc_base : 28;
}swreg4_strm_rlc_base; } swreg4_strm_rlc_base;
struct struct {
{
RK_U32 sw_stream_len : 27; RK_U32 sw_stream_len : 27;
}swreg5_stream_rlc_len; } swreg5_stream_rlc_len;
struct struct {
{
RK_U32 reverse0 : 4; RK_U32 reverse0 : 4;
RK_U32 sw_cabactbl_base : 28; RK_U32 sw_cabactbl_base : 28;
}swreg6_cabactbl_prob_base; } swreg6_cabactbl_prob_base;
struct struct {
{
RK_U32 reverse0 : 4; RK_U32 reverse0 : 4;
RK_U32 sw_decout_base : 28; RK_U32 sw_decout_base : 28;
}swreg7_decout_base; } swreg7_decout_base;
struct struct {
{
RK_U32 sw_y_virstride : 20; RK_U32 sw_y_virstride : 20;
}swreg8_y_virstride; } swreg8_y_virstride;
struct struct {
{
RK_U32 sw_yuv_virstride : 21; RK_U32 sw_yuv_virstride : 21;
}swreg9_yuv_virstride; } swreg9_yuv_virstride;
struct struct {
{
RK_U32 sw_ref_field : 1; RK_U32 sw_ref_field : 1;
RK_U32 sw_ref_topfield_used : 1; RK_U32 sw_ref_topfield_used : 1;
RK_U32 sw_ref_botfield_used : 1; RK_U32 sw_ref_botfield_used : 1;
RK_U32 sw_ref_colmv_use_flag : 1; RK_U32 sw_ref_colmv_use_flag : 1;
RK_U32 sw_refer_base : 28; RK_U32 sw_refer_base : 28;
}swreg10_24_refer0_14_base[15]; } swreg10_24_refer0_14_base[15];
RK_U32 swreg25_39_refer0_14_poc[15]; RK_U32 swreg25_39_refer0_14_poc[15];
struct struct {
{
RK_U32 sw_cur_poc : 32; RK_U32 sw_cur_poc : 32;
}swreg40_cur_poc; } swreg40_cur_poc;
struct struct {
{
RK_U32 reserve : 3; RK_U32 reserve : 3;
RK_U32 sw_rlcwrite_base : 29; RK_U32 sw_rlcwrite_base : 29;
}swreg41_rlcwrite_base; } swreg41_rlcwrite_base;
struct struct {
{
RK_U32 reserve : 4; RK_U32 reserve : 4;
RK_U32 sw_pps_base : 28; RK_U32 sw_pps_base : 28;
}swreg42_pps_base; } swreg42_pps_base;
struct swreg_sw_rps_base struct swreg_sw_rps_base {
{
RK_U32 reserve : 4; RK_U32 reserve : 4;
RK_U32 sw_rps_base : 28; RK_U32 sw_rps_base : 28;
}swreg43_rps_base; } swreg43_rps_base;
struct swreg_strmd_error_e struct swreg_strmd_error_e {
{
RK_U32 sw_strmd_error_e : 28; RK_U32 sw_strmd_error_e : 28;
RK_U32 reserve : 4; RK_U32 reserve : 4;
}swreg44_strmd_error_en; } swreg44_strmd_error_en;
struct struct {
{
RK_U32 sw_strmd_error_status : 28; RK_U32 sw_strmd_error_status : 28;
RK_U32 sw_colmv_error_ref_picidx : 4; RK_U32 sw_colmv_error_ref_picidx : 4;
}swreg45_strmd_error_status; } swreg45_strmd_error_status;
struct struct {
{
RK_U32 sw_strmd_error_ctu_xoffset : 8; RK_U32 sw_strmd_error_ctu_xoffset : 8;
RK_U32 sw_strmd_error_ctu_yoffset : 8; RK_U32 sw_strmd_error_ctu_yoffset : 8;
RK_U32 sw_streamfifo_space2full : 7; RK_U32 sw_streamfifo_space2full : 7;
RK_U32 reserve : 1; RK_U32 reserve : 1;
RK_U32 sw_vp9_error_ctu0_en : 1; RK_U32 sw_vp9_error_ctu0_en : 1;
}swreg46_strmd_error_ctu; } swreg46_strmd_error_ctu;
struct struct {
{
RK_U32 sw_saowr_xoffet : 9; RK_U32 sw_saowr_xoffet : 9;
RK_U32 reserve : 7; RK_U32 reserve : 7;
RK_U32 sw_saowr_yoffset : 10; RK_U32 sw_saowr_yoffset : 10;
}swreg47_sao_ctu_position; } swreg47_sao_ctu_position;
struct struct {
{
RK_U32 sw_ref_field : 1; RK_U32 sw_ref_field : 1;
RK_U32 sw_ref_topfield_used : 1; RK_U32 sw_ref_topfield_used : 1;
RK_U32 sw_ref_botfield_used : 1; RK_U32 sw_ref_botfield_used : 1;
RK_U32 sw_ref_colmv_use_flag : 1; RK_U32 sw_ref_colmv_use_flag : 1;
RK_U32 sw_refer_base : 28; RK_U32 sw_refer_base : 28;
}swreg48_refer15_base; } swreg48_refer15_base;
RK_U32 swreg49_63_refer15_29_poc[15]; RK_U32 swreg49_63_refer15_29_poc[15];
struct struct {
{
RK_U32 sw_performance_cycle : 32; RK_U32 sw_performance_cycle : 32;
}swreg64_performance_cycle; } swreg64_performance_cycle;
struct struct {
{
RK_U32 sw_axi_ddr_rdata : 32; RK_U32 sw_axi_ddr_rdata : 32;
}swreg65_axi_ddr_rdata; } swreg65_axi_ddr_rdata;
struct struct {
{
RK_U32 sw_axi_ddr_rdata : 32; RK_U32 sw_axi_ddr_rdata : 32;
}swreg66_axi_ddr_wdata; } swreg66_axi_ddr_wdata;
struct struct {
{
RK_U32 sw_busifd_resetn : 1; RK_U32 sw_busifd_resetn : 1;
RK_U32 sw_cabac_resetn : 1; RK_U32 sw_cabac_resetn : 1;
RK_U32 sw_dec_ctrl_resetn : 1; RK_U32 sw_dec_ctrl_resetn : 1;
@@ -289,52 +251,44 @@ typedef struct h264_regs_t
RK_U32 sw_inter_resetn : 1; RK_U32 sw_inter_resetn : 1;
RK_U32 sw_recon_resetn : 1; RK_U32 sw_recon_resetn : 1;
RK_U32 sw_filer_resetn : 1; RK_U32 sw_filer_resetn : 1;
}swreg67_fpgadebug_reset; } swreg67_fpgadebug_reset;
struct struct {
{
RK_U32 perf_cnt0_sel : 6; RK_U32 perf_cnt0_sel : 6;
RK_U32 reserve0 : 2; RK_U32 reserve0 : 2;
RK_U32 perf_cnt1_sel : 6; RK_U32 perf_cnt1_sel : 6;
RK_U32 reserve1 : 2; RK_U32 reserve1 : 2;
RK_U32 perf_cnt2_sel : 6; RK_U32 perf_cnt2_sel : 6;
}swreg68_performance_sel; } swreg68_performance_sel;
struct struct {
{
RK_U32 perf_cnt0 : 32; RK_U32 perf_cnt0 : 32;
}swreg69_performance_cnt0; } swreg69_performance_cnt0;
struct struct {
{
RK_U32 perf_cnt1 : 32; RK_U32 perf_cnt1 : 32;
}swreg70_performance_cnt1; } swreg70_performance_cnt1;
struct struct {
{
RK_U32 perf_cnt2 : 32; RK_U32 perf_cnt2 : 32;
}swreg71_performance_cnt2; } swreg71_performance_cnt2;
RK_U32 swreg72_refer30_poc; RK_U32 swreg72_refer30_poc;
RK_U32 swreg73_refer31_poc; RK_U32 swreg73_refer31_poc;
struct struct {
{
RK_U32 sw_h264_cur_poc1 : 32; RK_U32 sw_h264_cur_poc1 : 32;
}swreg74_h264_cur_poc1; } swreg74_h264_cur_poc1;
struct struct {
{
RK_U32 reserve : 4; RK_U32 reserve : 4;
RK_U32 sw_errorinfo_base : 28; RK_U32 sw_errorinfo_base : 28;
}swreg75_h264_errorinfo_base; } swreg75_h264_errorinfo_base;
struct struct {
{
RK_U32 sw_slicedec_num : 14; RK_U32 sw_slicedec_num : 14;
RK_U32 reserve : 1; RK_U32 reserve : 1;
RK_U32 sw_strmd_detect_error_flag : 1; RK_U32 sw_strmd_detect_error_flag : 1;
RK_U32 sw_error_packet_num : 14; RK_U32 sw_error_packet_num : 14;
}swreg76_h264_errorinfo_num; } swreg76_h264_errorinfo_num;
struct struct {
{
RK_U32 sw_h264_error_en_highbits : 30; RK_U32 sw_h264_error_en_highbits : 30;
RK_U32 reserve : 2; RK_U32 reserve : 2;
}swreg77_h264_error_e; } swreg77_h264_error_e;
RK_U32 compare_len; RK_U32 compare_len;
}H264_REGS_t; } H264_REGS_t;
@@ -378,14 +332,14 @@ extern const MppHalApi api_h264d_hal;
extern "C" { extern "C" {
#endif #endif
MPP_RET hal_h264d_init (void **hal, MppHalCfg *cfg); MPP_RET hal_h264d_init (void **hal, MppHalCfg *cfg);
MPP_RET hal_h264d_deinit (void *hal); MPP_RET hal_h264d_deinit (void *hal);
MPP_RET hal_h264d_gen_regs(void *hal, MppSyntax *syn); MPP_RET hal_h264d_gen_regs(void *hal, MppSyntax *syn);
MPP_RET hal_h264d_start (void *hal, MppHalDecTask task); MPP_RET hal_h264d_start (void *hal, MppHalDecTask task);
MPP_RET hal_h264d_wait (void *hal, MppHalDecTask task); MPP_RET hal_h264d_wait (void *hal, MppHalDecTask task);
MPP_RET hal_h264d_reset (void *hal); MPP_RET hal_h264d_reset (void *hal);
MPP_RET hal_h264d_flush (void *hal); MPP_RET hal_h264d_flush (void *hal);
MPP_RET hal_h264d_control (void *hal, RK_S32 cmd_type, void *param); MPP_RET hal_h264d_control (void *hal, RK_S32 cmd_type, void *param);

9
mpp/mpi_impl.h
View File

@@ -25,11 +25,12 @@
#define mpi_dbg(flag, fmt, ...) _mpp_dbg(mpi_debug, flag, fmt, ## __VA_ARGS__) #define mpi_dbg(flag, fmt, ...) _mpp_dbg(mpi_debug, flag, fmt, ## __VA_ARGS__)
#define mpi_dbg_f(flag, fmt, ...) _mpp_dbg_f(mpi_debug, flag, fmt, ## __VA_ARGS__)
#define MPI_FUNCTION_ENTER() mpi_dbg(MPI_DBG_FUNCTION, "%s enter\n", __FUNCTION__) #define MPI_FUNCTION_ENTER() mpi_dbg_f(MPI_DBG_FUNCTION, "enter\n")
#define MPI_FUNCTION_LEAVE() mpi_dbg(MPI_DBG_FUNCTION, "%s leave\n", __FUNCTION__) #define MPI_FUNCTION_LEAVE() mpi_dbg_f(MPI_DBG_FUNCTION, "leave\n")
#define MPI_FUNCTION_LEAVE_OK() mpi_dbg(MPI_DBG_FUNCTION, "%s success\n", __FUNCTION__) #define MPI_FUNCTION_LEAVE_OK() mpi_dbg_f(MPI_DBG_FUNCTION, "success\n")
#define MPI_FUNCTION_LEAVE_FAIL() mpi_dbg(MPI_DBG_FUNCTION, "%s failed\n", __FUNCTION__) #define MPI_FUNCTION_LEAVE_FAIL() mpi_dbg_f(MPI_DBG_FUNCTION, "failed\n")
typedef struct MpiImpl_t MpiImpl; typedef struct MpiImpl_t MpiImpl;

9
mpp/mpp_buffer_impl.h
View File

@@ -24,11 +24,12 @@
#define MPP_BUF_DBG_FUNCTION (0x00000001) #define MPP_BUF_DBG_FUNCTION (0x00000001)
#define mpp_buf_dbg(flag, fmt, ...) _mpp_dbg(mpp_buffer_debug, flag, fmt, ## __VA_ARGS__) #define mpp_buf_dbg(flag, fmt, ...) _mpp_dbg(mpp_buffer_debug, flag, fmt, ## __VA_ARGS__)
#define mpp_buf_dbg_f(flag, fmt, ...) _mpp_dbg(mpp_buffer_debug, flag, fmt, ## __VA_ARGS__)
#define MPP_BUF_FUNCTION_ENTER() mpp_buf_dbg(MPP_BUF_DBG_FUNCTION, "%s enter\n", __FUNCTION__) #define MPP_BUF_FUNCTION_ENTER() mpp_buf_dbg_f(MPP_BUF_DBG_FUNCTION, "enter\n")
#define MPP_BUF_FUNCTION_LEAVE() mpp_buf_dbg(MPP_BUF_DBG_FUNCTION, "%s leave\n", __FUNCTION__) #define MPP_BUF_FUNCTION_LEAVE() mpp_buf_dbg_f(MPP_BUF_DBG_FUNCTION, "leave\n")
#define MPP_BUF_FUNCTION_LEAVE_OK() mpp_buf_dbg(MPP_BUF_DBG_FUNCTION, "%s success\n", __FUNCTION__) #define MPP_BUF_FUNCTION_LEAVE_OK() mpp_buf_dbg_f(MPP_BUF_DBG_FUNCTION, "success\n")
#define MPP_BUF_FUNCTION_LEAVE_FAIL() mpp_buf_dbg(MPP_BUF_DBG_FUNCTION, "%s failed\n", __FUNCTION__) #define MPP_BUF_FUNCTION_LEAVE_FAIL() mpp_buf_dbg_f(MPP_BUF_DBG_FUNCTION, "failed\n")
typedef struct MppBufferImpl_t MppBufferImpl; typedef struct MppBufferImpl_t MppBufferImpl;
typedef struct MppBufferGroupImpl_t MppBufferGroupImpl; typedef struct MppBufferGroupImpl_t MppBufferGroupImpl;