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[hal_vepu580]: Add hw config implemnet

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Signed-off-by: toby.zhang <toby.zhang@rock-chips.com>
Change-Id: I40f9d781fb2fe88a35329141d788e2d6fa38ab9b
This commit is contained in:
toby.zhang
2022-07-04 18:18:13 +08:00
committed by Herman Chen
parent 61fbfb82cd
commit 8fd9a478ba
2 changed files with 269 additions and 0 deletions
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48
mpp/hal/rkenc/h264e/hal_h264e_vepu580.c
View File

@@ -120,6 +120,13 @@ static RK_U32 h264e_klut_weight[30] = {
static RK_U32 dump_l1_reg = 0;
static RK_U32 dump_l2_reg = 0;
static RK_U32 h264_mode_bias[16] = {
0, 2, 4, 6,
8, 10, 12, 14,
16, 18, 20, 24,
28, 32, 64, 128
};
static RK_S32 h264_aq_tthd_default[16] = {
0, 0, 0, 0,
3, 3, 5, 5,
@@ -983,6 +990,46 @@ static void setup_vepu580_rdo_pred(HalVepu580RegSet *regs, H264eSps *sps,
hal_h264e_dbg_func("leave\n");
}
static void setup_vepu580_rdo_bias_cfg(Vepu580RdoCfg *regs, MppEncHwCfg *hw)
{
RK_U8 bias = h264_mode_bias[hw->mode_bias[1]];
regs->rdo_intra_atf_wgt0.atf_rdo_intra_wgt00 = bias > 24 ? bias : 24;
regs->rdo_intra_atf_wgt0.atf_rdo_intra_wgt01 = bias > 22 ? bias : 22;
regs->rdo_intra_atf_wgt0.atf_rdo_intra_wgt02 = bias > 21 ? bias : 21;
regs->rdo_intra_atf_wgt1.atf_rdo_intra_wgt10 = bias > 22 ? bias : 22;
regs->rdo_intra_atf_wgt1.atf_rdo_intra_wgt11 = bias > 21 ? bias : 21;
regs->rdo_intra_atf_wgt1.atf_rdo_intra_wgt12 = bias > 20 ? bias : 20;
regs->rdo_intra_atf_wgt2.atf_rdo_intra_wgt20 = bias > 20 ? bias : 20;
regs->rdo_intra_atf_wgt2.atf_rdo_intra_wgt21 = bias > 19 ? bias : 19;
regs->rdo_intra_atf_wgt2.atf_rdo_intra_wgt22 = bias > 18 ? bias : 18;
regs->rdo_intra_atf_wgt3.atf_rdo_intra_wgt30 = bias;
regs->rdo_intra_atf_wgt3.atf_rdo_intra_wgt31 = bias;
regs->rdo_intra_atf_wgt3.atf_rdo_intra_wgt32 = bias;
if (hw->skip_bias_en) {
bias = hw->skip_bias;
regs->rdo_skip_cime_thd0.atf_rdo_skip_cime_thd0 = hw->skip_sad < 10 ? hw->skip_sad : 10;
regs->rdo_skip_cime_thd0.atf_rdo_skip_cime_thd1 = hw->skip_sad < 8 ? hw->skip_sad : 8;
regs->rdo_skip_cime_thd1.atf_rdo_skip_cime_thd2 = hw->skip_sad < 15 ? hw->skip_sad : 15;
regs->rdo_skip_cime_thd1.atf_rdo_skip_cime_thd3 = hw->skip_sad;
regs->rdo_skip_atf_wgt0.atf_rdo_skip_atf_wgt00 = bias > 20 ? bias : 20;
regs->rdo_skip_atf_wgt0.atf_rdo_skip_atf_wgt10 = bias;
regs->rdo_skip_atf_wgt0.atf_rdo_skip_atf_wgt11 = bias;
regs->rdo_skip_atf_wgt0.atf_rdo_skip_atf_wgt12 = bias;
regs->rdo_skip_atf_wgt1.atf_rdo_skip_atf_wgt20 = bias;
regs->rdo_skip_atf_wgt1.atf_rdo_skip_atf_wgt21 = bias;
regs->rdo_skip_atf_wgt1.atf_rdo_skip_atf_wgt22 = bias;
regs->rdo_skip_atf_wgt2.atf_rdo_skip_atf_wgt30 = bias;
regs->rdo_skip_atf_wgt2.atf_rdo_skip_atf_wgt31 = bias;
regs->rdo_skip_atf_wgt2.atf_rdo_skip_atf_wgt32 = bias;
regs->rdo_skip_atf_wgt3.atf_rdo_skip_atf_wgt40 = bias;
regs->rdo_skip_atf_wgt3.atf_rdo_skip_atf_wgt41 = bias;
regs->rdo_skip_atf_wgt3.atf_rdo_skip_atf_wgt42 = bias;
}
}
static void setup_vepu580_rdo_cfg(Vepu580RdoCfg *regs)
{
hal_h264e_dbg_func("enter\n");
@@ -1853,6 +1900,7 @@ static MPP_RET hal_h264e_vepu580_gen_regs(void *hal, HalEncTask *task)
setup_vepu580_codec(regs, sps, pps, slice);
setup_vepu580_rdo_pred(regs, sps, pps, slice);
setup_vepu580_rdo_cfg(&regs->reg_rdo);
setup_vepu580_rdo_bias_cfg(&regs->reg_rdo, &cfg->hw);
setup_vepu580_scl_cfg(&regs->reg_scl);
setup_vepu580_rc_base(regs, sps, slice, &cfg->hw, rc_task);
setup_vepu580_io_buf(regs, ctx->offsets, task);

221
mpp/hal/rkenc/h265e/hal_h265e_vepu580.c
View File

@@ -139,6 +139,13 @@ static RK_U32 aq_thd_default[16] = {
15, 20, 25, 35
};
static RK_U32 h265e_mode_bias[16] = {
0, 2, 4, 6,
8, 10, 12, 14,
16, 18, 20, 24,
28, 32, 64, 128
};
static RK_S32 aq_qp_dealt_default[16] = {
-8, -7, -6, -5,
-4, -3, -2, -1,
@@ -623,6 +630,219 @@ static void vepu580_h265_sobel_cfg(hevc_vepu580_wgt *reg)
reg->i32_sobel_e_09.intra_l32_sobel_e1_qp4_high = 0;
}
static void vepu580_h265_rdo_bias_cfg (vepu580_rdo_cfg *reg, MppEncHwCfg *hw)
{
RdoAtfCfg* p_rdo_atf;
RdoAtfSkipCfg* p_rdo_atf_skip;
RK_U8 bias = h265e_mode_bias[hw->mode_bias[4]];
p_rdo_atf = &reg->rdo_b64_inter_atf;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
if (hw->skip_bias_en) {
bias = h265e_mode_bias[hw->skip_bias];
p_rdo_atf_skip = &reg->rdo_b64_skip_atf;
p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = hw->skip_sad < 24 ? hw->skip_sad : 24;
p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = hw->skip_sad < 4 ? hw->skip_sad : 4;
p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = hw->skip_sad < 6 ? hw->skip_sad : 6;
p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = hw->skip_sad;
p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = bias > 24 ? bias : 24;
p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = bias < 4 ? bias : 4;
p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = bias < 6 ? bias : 6;
p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = bias < 8 ? bias : 8;
p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10 = bias < 10 ? bias : 10;
p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11 = bias < 10 ? bias : 10;
p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12 = bias < 10 ? bias : 10;
p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20 = bias < 14 ? bias : 14;
p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21 = bias < 14 ? bias : 14;
p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22 = bias < 15 ? bias : 15;
p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30 = bias < 15 ? bias : 15;
p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31 = bias < 15 ? bias : 15;
p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42 = bias;
}
bias = h265e_mode_bias[hw->mode_bias[0]];
p_rdo_atf = &reg->rdo_b32_intra_atf;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias > 26 ? bias : 26;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias > 25 ? bias : 25;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias > 25 ? bias : 25;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias > 25 ? bias : 25;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias > 24 ? bias : 24;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias > 23 ? bias : 23;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias > 21 ? bias : 21;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias > 19 ? bias : 19;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias > 18 ? bias : 18;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
bias = h265e_mode_bias[hw->mode_bias[5]];
p_rdo_atf = &reg->rdo_b32_inter_atf;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
if (hw->skip_bias_en) {
bias = h265e_mode_bias[hw->skip_bias];
p_rdo_atf_skip = &reg->rdo_b32_skip_atf;
p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = hw->skip_sad < 24 ? hw->skip_sad : 24;
p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = hw->skip_sad < 4 ? hw->skip_sad : 4;
p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = hw->skip_sad < 6 ? hw->skip_sad : 6;
p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = hw->skip_sad;
p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias > 18 ? bias : 18;
p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10 = bias < 11 ? bias : 11;
p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11 = bias < 11 ? bias : 11;
p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12 = bias < 11 ? bias : 11;
p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20 = bias < 13 ? bias : 13;
p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21 = bias < 13 ? bias : 13;
p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22 = bias < 13 ? bias : 13;
p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30 = bias < 15 ? bias : 15;
p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31 = bias < 15 ? bias : 15;
p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32 = bias < 15 ? bias : 15;
p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42 = bias;
}
bias = h265e_mode_bias[hw->mode_bias[1]];
p_rdo_atf = &reg->rdo_b16_intra_atf;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias > 26 ? bias : 26;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias > 25 ? bias : 25;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias > 25 ? bias : 25;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias > 25 ? bias : 25;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias > 24 ? bias : 24;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias > 23 ? bias : 23;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias > 21 ? bias : 21;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias > 19 ? bias : 19;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias > 18 ? bias : 18;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
bias = h265e_mode_bias[hw->mode_bias[6]];
p_rdo_atf = &reg->rdo_b16_inter_atf;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
if (hw->skip_bias_en) {
bias = h265e_mode_bias[hw->skip_bias];
p_rdo_atf_skip = &reg->rdo_b16_skip_atf;
p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = hw->skip_sad < 24 ? hw->skip_sad : 24;
p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = hw->skip_sad < 24 ? hw->skip_sad : 24;
p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = hw->skip_sad < 48 ? hw->skip_sad : 48;
p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = hw->skip_sad;
p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42 = bias;
}
bias = h265e_mode_bias[hw->mode_bias[2]];
p_rdo_atf = &reg->rdo_b8_intra_atf;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias > 26 ? bias : 26;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias > 25 ? bias : 25;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias > 25 ? bias : 25;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias > 25 ? bias : 25;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias > 24 ? bias : 24;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias > 23 ? bias : 23;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias > 21 ? bias : 21;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias > 19 ? bias : 19;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias > 18 ? bias : 18;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
bias = h265e_mode_bias[hw->mode_bias[7]];
p_rdo_atf = &reg->rdo_b8_inter_atf;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias;
p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias;
p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias;
p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
if (hw->skip_bias_en) {
bias = h265e_mode_bias[hw->skip_bias];
p_rdo_atf_skip = &reg->rdo_b8_skip_atf;
p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = hw->skip_sad < 24 ? hw->skip_sad : 24;
p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = hw->skip_sad < 24 ? hw->skip_sad : 24;
p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = hw->skip_sad < 48 ? hw->skip_sad : 48;
p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = hw->skip_sad;
p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41 = bias;
p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42 = bias;
}
}
static void vepu580_h265_rdo_cfg (vepu580_rdo_cfg *reg)
{
RdoAtfCfg* p_rdo_atf;
@@ -1059,6 +1279,7 @@ static void vepu580_h265_global_cfg_set(H265eV580HalContext *ctx, H265eV580RegSe
vepu580_rdo_cfg *reg_rdo = &regs->reg_rdo;
vepu580_h265_sobel_cfg(reg_wgt);
vepu580_h265_rdo_cfg(reg_rdo);
vepu580_h265_rdo_bias_cfg(reg_rdo, hw);
vepu580_h265_scl_cfg(reg_rdo);
memcpy(&reg_wgt->iprd_wgt_qp_hevc_0_51[0], lamd_satd_qp, sizeof(lamd_satd_qp));