From 8e00c203d7242f2dc7ad6f6cdfc3399f55bcd681 Mon Sep 17 00:00:00 2001 From: "sayon.chen" Date: Wed, 13 May 2020 15:07:40 +0800 Subject: [PATCH] [mpp_enc_cfg]: Add h265e default cfg Change-Id: I7f4b05be7bcfdbb93cf3b40f74941e14190ce3b4 Signed-off-by: sayon.chen --- inc/rk_venc_cmd.h | 4 ++-- mpp/base/mpp_enc_cfg.cpp | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/inc/rk_venc_cmd.h b/inc/rk_venc_cmd.h index 317c554a..83b1b980 100644 --- a/inc/rk_venc_cmd.h +++ b/inc/rk_venc_cmd.h @@ -841,8 +841,8 @@ typedef struct MppEncH265TransCfg_t { RK_U32 transquant_bypass_enabled_flag; RK_U32 transform_skip_enabled_flag; RK_U32 defalut_ScalingList_enable; /* default: 0 */ - RK_U32 cb_qp_offset; - RK_U32 cr_qp_offset; + RK_S32 cb_qp_offset; + RK_S32 cr_qp_offset; } MppEncH265TransCfg; typedef struct MppEncH265MergeCfg_t { diff --git a/mpp/base/mpp_enc_cfg.cpp b/mpp/base/mpp_enc_cfg.cpp index f1cf93d2..7f6c0311 100644 --- a/mpp/base/mpp_enc_cfg.cpp +++ b/mpp/base/mpp_enc_cfg.cpp @@ -191,6 +191,24 @@ static const char *cfg_func_names[] = { ENTRY(h264, qp_max_i, S32, RK_S32, MPP_ENC_H264_CFG_CHANGE_QP_LIMIT, codec.h264, qp_max) \ ENTRY(h264, qp_min_i, S32, RK_S32, MPP_ENC_H264_CFG_CHANGE_QP_LIMIT, codec.h264, qp_min) \ ENTRY(h264, qp_step, S32, RK_S32, MPP_ENC_H264_CFG_CHANGE_QP_LIMIT, codec.h264, qp_max_step) \ + /* h265 config*/ \ + ENTRY(h265, profile, S32, RK_S32, MPP_ENC_H265_CFG_PROFILE_LEVEL_TILER_CHANGE, codec.h265, profile) \ + ENTRY(h265, level, S32, RK_S32, MPP_ENC_H265_CFG_PROFILE_LEVEL_TILER_CHANGE, codec.h265, level) \ + ENTRY(h265, scaling_list, U32, RK_U32, MPP_ENC_H265_CFG_TRANS_CHANGE, codec.h265, trans_cfg.defalut_ScalingList_enable) \ + ENTRY(h265, cb_qp_offset, S32, RK_S32, MPP_ENC_H265_CFG_TRANS_CHANGE, codec.h265, trans_cfg.cb_qp_offset) \ + ENTRY(h265, cr_qp_offset, S32, RK_S32, MPP_ENC_H265_CFG_TRANS_CHANGE, codec.h265, trans_cfg.cr_qp_offset) \ + ENTRY(h265, dblk_disable, U32, RK_U32, MPP_ENC_H265_CFG_DBLK_CHANGE, codec.h265, dblk_cfg.slice_deblocking_filter_disabled_flag) \ + ENTRY(h265, dblk_alpha, S32, RK_S32, MPP_ENC_H265_CFG_DBLK_CHANGE, codec.h265, dblk_cfg.slice_beta_offset_div2) \ + ENTRY(h265, dblk_beta, S32, RK_S32, MPP_ENC_H265_CFG_DBLK_CHANGE, codec.h265, dblk_cfg.slice_tc_offset_div2) \ + ENTRY(h265, qp_init, S32, RK_S32, MPP_ENC_H265_CFG_RC_QP_CHANGE, codec.h265, qp_init) \ + ENTRY(h265, qp_max, S32, RK_S32, MPP_ENC_H265_CFG_RC_QP_CHANGE, codec.h265, max_qp) \ + ENTRY(h265, qp_min, S32, RK_S32, MPP_ENC_H265_CFG_RC_QP_CHANGE, codec.h265, min_qp) \ + ENTRY(h265, qp_max_i, S32, RK_S32, MPP_ENC_H265_CFG_RC_QP_CHANGE, codec.h265, max_i_qp) \ + ENTRY(h265, qp_min_i, S32, RK_S32, MPP_ENC_H265_CFG_RC_QP_CHANGE, codec.h265, min_i_qp) \ + ENTRY(h265, qp_step, S32, RK_S32, MPP_ENC_H265_CFG_RC_QP_CHANGE, codec.h265, qp_max_step) \ + ENTRY(h265, qp_delta_ip, S32, RK_S32, MPP_ENC_H265_CFG_RC_QP_CHANGE, codec.h265, ip_qp_delta) \ + /* jpeg config */ \ + ENTRY(jpeg, quant, S32, RK_S32, MPP_ENC_JPEG_CFG_CHANGE_QP, codec.jpeg, quant) \ /* split config */ \ ENTRY(split, split_mode, U32, RK_U32, MPP_ENC_SPLIT_CFG_CHANGE_MODE, split, split_mode) \ ENTRY(split, split_arg, U32, RK_U32, MPP_ENC_SPLIT_CFG_CHANGE_ARG, split, split_arg)