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[mpp_soc]: Add avs+ decoder to rk3588

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Change-Id: Ia93c70a16c17d1202ae4b133f157c140d8c8668c
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
This commit is contained in:
Herman Chen
2022-03-03 16:38:49 +08:00
parent 6b24ea59d6
commit 881f05c7cf
2 changed files with 39 additions and 24 deletions
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2
osal/inc/mpp_soc.h
View File

@@ -81,7 +81,7 @@ typedef struct {
const RK_U32 vcodec_type; const RK_U32 vcodec_type;
/* Max 4 decoder cap */ /* Max 4 decoder cap */
const MppDecHwCap *dec_caps[5]; const MppDecHwCap *dec_caps[6];
/* Max 4 encoder cap */ /* Max 4 encoder cap */
const MppEncHwCap *enc_caps[4]; const MppEncHwCap *enc_caps[4];
} MppSocInfo; } MppSocInfo;

61
osal/mpp_soc.cpp
View File

@@ -52,6 +52,7 @@
#define CAP_CODING_VDPU (HAVE_MPEG2|HAVE_H263|HAVE_MPEG4|HAVE_AVC|HAVE_MJPEG|HAVE_VP8) #define CAP_CODING_VDPU (HAVE_MPEG2|HAVE_H263|HAVE_MPEG4|HAVE_AVC|HAVE_MJPEG|HAVE_VP8)
#define CAP_CODING_JPEGD_PP (HAVE_MJPEG) #define CAP_CODING_JPEGD_PP (HAVE_MJPEG)
#define CAP_CODING_AVSD (HAVE_AVS) #define CAP_CODING_AVSD (HAVE_AVS)
#define CAP_CODING_AVSPD (HAVE_AVSP)
#define CAP_CODING_AV1D (HAVE_AV1) #define CAP_CODING_AV1D (HAVE_AV1)
#define CAP_CODING_HEVC (HAVE_HEVC) #define CAP_CODING_HEVC (HAVE_HEVC)
#define CAP_CODING_VDPU341 (HAVE_AVC|HAVE_HEVC|HAVE_VP9) #define CAP_CODING_VDPU341 (HAVE_AVC|HAVE_HEVC|HAVE_VP9)
@@ -274,6 +275,20 @@ static const MppDecHwCap avsd = {
.reserved = 0, .reserved = 0,
}; };
static const MppDecHwCap avspd = {
.cap_coding = CAP_CODING_AVSPD,
.type = VPU_CLIENT_AVSPLUS_DEC,
.cap_fbc = 0,
.cap_4k = 0,
.cap_8k = 0,
.cap_colmv_buf = 0,
.cap_hw_h265_rps = 0,
.cap_hw_vp9_prob = 0,
.cap_jpg_pp_out = 0,
.cap_10bit = 0,
.reserved = 0,
};
static const MppDecHwCap rkjpegd = { static const MppDecHwCap rkjpegd = {
.cap_coding = HAVE_MJPEG, .cap_coding = HAVE_MJPEG,
.type = VPU_CLIENT_JPEG_DEC, .type = VPU_CLIENT_JPEG_DEC,
@@ -418,21 +433,21 @@ static const MppSocInfo mpp_soc_infos[] = {
"rk3036", "rk3036",
ROCKCHIP_SOC_RK3036, ROCKCHIP_SOC_RK3036,
HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_HEVC_DEC, HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_HEVC_DEC,
{ &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, }, { &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
{ NULL, NULL, NULL, NULL, }, { NULL, NULL, NULL, NULL, },
}, },
{ /* rk3066 has vpu1 only */ { /* rk3066 has vpu1 only */
"rk3066", "rk3066",
ROCKCHIP_SOC_RK3066, ROCKCHIP_SOC_RK3066,
HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1, HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1,
{ &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, }, { &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, NULL, },
{ &vepu1, NULL, NULL, NULL, }, { &vepu1, NULL, NULL, NULL, },
}, },
{ /* rk3188 has vpu1 only */ { /* rk3188 has vpu1 only */
"rk3188", "rk3188",
ROCKCHIP_SOC_RK3188, ROCKCHIP_SOC_RK3188,
HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1, HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1,
{ &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, }, { &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, NULL, },
{ &vepu1, NULL, NULL, NULL, }, { &vepu1, NULL, NULL, NULL, },
}, },
{ /* { /*
@@ -443,7 +458,7 @@ static const MppSocInfo mpp_soc_infos[] = {
"rk3288", "rk3288",
ROCKCHIP_SOC_RK3288, ROCKCHIP_SOC_RK3288,
HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC, HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC,
{ &rk_hevc, &vdpu1_2160p, &vdpu1_jpeg_pp, NULL, NULL, }, { &rk_hevc, &vdpu1_2160p, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
{ &vepu1, NULL, NULL, NULL, }, { &vepu1, NULL, NULL, NULL, },
}, },
{ /* { /*
@@ -454,7 +469,7 @@ static const MppSocInfo mpp_soc_infos[] = {
"rk3126", "rk3126",
ROCKCHIP_SOC_RK312X, ROCKCHIP_SOC_RK312X,
HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC, HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC,
{ &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, }, { &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
{ &vepu1, NULL, NULL, NULL, }, { &vepu1, NULL, NULL, NULL, },
}, },
{ /* { /*
@@ -466,7 +481,7 @@ static const MppSocInfo mpp_soc_infos[] = {
"rk3128h", "rk3128h",
ROCKCHIP_SOC_RK3128H, ROCKCHIP_SOC_RK3128H,
HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC,
{ &vdpu341_lite_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, }, { &vdpu341_lite_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
{ &vepu2_no_jpeg, NULL, NULL, NULL, }, { &vepu2_no_jpeg, NULL, NULL, NULL, },
}, },
{ /* { /*
@@ -477,7 +492,7 @@ static const MppSocInfo mpp_soc_infos[] = {
"rk3128", "rk3128",
ROCKCHIP_SOC_RK312X, ROCKCHIP_SOC_RK312X,
HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC, HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC,
{ &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, }, { &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
{ &vepu1, NULL, NULL, NULL, }, { &vepu1, NULL, NULL, NULL, },
}, },
{ /* { /*
@@ -488,7 +503,7 @@ static const MppSocInfo mpp_soc_infos[] = {
"rk3368", "rk3368",
ROCKCHIP_SOC_RK3368, ROCKCHIP_SOC_RK3368,
HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC, HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC,
{ &rk_hevc, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, }, { &rk_hevc, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
{ &vepu1, NULL, NULL, NULL, }, { &vepu1, NULL, NULL, NULL, },
}, },
{ /* { /*
@@ -499,7 +514,7 @@ static const MppSocInfo mpp_soc_infos[] = {
"rk3399", "rk3399",
ROCKCHIP_SOC_RK3399, ROCKCHIP_SOC_RK3399,
HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC,
{ &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, }, { &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
{ &vepu2, NULL, NULL, NULL, }, { &vepu2, NULL, NULL, NULL, },
}, },
{ /* { /*
@@ -513,7 +528,7 @@ static const MppSocInfo mpp_soc_infos[] = {
"rk3228h", "rk3228h",
ROCKCHIP_SOC_RK3228H, ROCKCHIP_SOC_RK3228H,
HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_AVSDEC | HAVE_VEPU22, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_AVSDEC | HAVE_VEPU22,
{ &vdpu341_lite, &vdpu2, &vdpu2_jpeg_pp, &avsd, NULL, }, { &vdpu341_lite, &vdpu2, &vdpu2_jpeg_pp, &avsd, NULL, NULL, },
{ &vepu2_no_jpeg, &vepu22, NULL, NULL, }, { &vepu2_no_jpeg, &vepu22, NULL, NULL, },
}, },
{ /* { /*
@@ -525,7 +540,7 @@ static const MppSocInfo mpp_soc_infos[] = {
"rk3328", "rk3328",
ROCKCHIP_SOC_RK3328, ROCKCHIP_SOC_RK3328,
HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_VEPU22, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_VEPU22,
{ &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, }, { &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
{ &vepu2, &vepu22, NULL, NULL, }, { &vepu2, &vepu22, NULL, NULL, },
}, },
{ /* { /*
@@ -537,7 +552,7 @@ static const MppSocInfo mpp_soc_infos[] = {
"rk3228", "rk3228",
ROCKCHIP_SOC_RK3228, ROCKCHIP_SOC_RK3228,
HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC,
{ &vdpu341_lite, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, }, { &vdpu341_lite, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
{ &vepu2_no_jpeg, NULL, NULL, NULL, }, { &vepu2_no_jpeg, NULL, NULL, NULL, },
}, },
{ /* { /*
@@ -548,7 +563,7 @@ static const MppSocInfo mpp_soc_infos[] = {
"rk3229", "rk3229",
ROCKCHIP_SOC_RK3229, ROCKCHIP_SOC_RK3229,
HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC,
{ &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, }, { &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
{ &vepu2, NULL, NULL, NULL, }, { &vepu2, NULL, NULL, NULL, },
}, },
{ /* { /*
@@ -560,7 +575,7 @@ static const MppSocInfo mpp_soc_infos[] = {
"rv1108", "rv1108",
ROCKCHIP_SOC_RV1108, ROCKCHIP_SOC_RV1108,
HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC, HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC,
{ &vdpu2_jpeg, &vdpu341_h264, NULL, NULL, NULL, }, { &vdpu2_jpeg, &vdpu341_h264, NULL, NULL, NULL, NULL, },
{ &vepu2_jpeg, &vepu540p, NULL, NULL, }, { &vepu2_jpeg, &vepu540p, NULL, NULL, },
}, },
{ /* { /*
@@ -572,7 +587,7 @@ static const MppSocInfo mpp_soc_infos[] = {
"rv1109", "rv1109",
ROCKCHIP_SOC_RV1109, ROCKCHIP_SOC_RV1109,
HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC, HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC,
{ &vdpu2_jpeg, &vdpu341_lite, NULL, NULL, NULL, }, { &vdpu2_jpeg, &vdpu341_lite, NULL, NULL, NULL, NULL, },
{ &vepu2_jpeg, &vepu541, NULL, NULL, }, { &vepu2_jpeg, &vepu541, NULL, NULL, },
}, },
{ /* { /*
@@ -584,7 +599,7 @@ static const MppSocInfo mpp_soc_infos[] = {
"rv1126", "rv1126",
ROCKCHIP_SOC_RV1126, ROCKCHIP_SOC_RV1126,
HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC, HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC,
{ &vdpu2_jpeg, &vdpu341_lite, NULL, NULL, NULL, }, { &vdpu2_jpeg, &vdpu341_lite, NULL, NULL, NULL, NULL, },
{ &vepu2_jpeg, &vepu541, NULL, NULL, }, { &vepu2_jpeg, &vepu541, NULL, NULL, },
}, },
{ /* { /*
@@ -595,7 +610,7 @@ static const MppSocInfo mpp_soc_infos[] = {
"rk3326", "rk3326",
ROCKCHIP_SOC_RK3326, ROCKCHIP_SOC_RK3326,
HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_HEVC_DEC, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_HEVC_DEC,
{ &rk_hevc_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, }, { &rk_hevc_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
{ &vepu2, NULL, NULL, NULL, }, { &vepu2, NULL, NULL, NULL, },
}, },
{ /* { /*
@@ -606,7 +621,7 @@ static const MppSocInfo mpp_soc_infos[] = {
"px30", "px30",
ROCKCHIP_SOC_RK3326, ROCKCHIP_SOC_RK3326,
HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_HEVC_DEC, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_HEVC_DEC,
{ &rk_hevc_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, }, { &rk_hevc_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
{ &vepu2, NULL, NULL, NULL, }, { &vepu2, NULL, NULL, NULL, },
}, },
{ /* { /*
@@ -615,7 +630,7 @@ static const MppSocInfo mpp_soc_infos[] = {
"rk1808", "rk1808",
ROCKCHIP_SOC_RK1808, ROCKCHIP_SOC_RK1808,
HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2,
{ &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, }, { &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, NULL, },
{ &vepu2, NULL, NULL, NULL, }, { &vepu2, NULL, NULL, NULL, },
}, },
{ /* { /*
@@ -628,7 +643,7 @@ static const MppSocInfo mpp_soc_infos[] = {
"rk3566", "rk3566",
ROCKCHIP_SOC_RK3566, ROCKCHIP_SOC_RK3566,
HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC,
{ &vdpu34x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp, NULL, }, { &vdpu34x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, },
{ &vepu540, &vepu2, NULL, NULL, }, { &vepu540, &vepu2, NULL, NULL, },
}, },
{ /* { /*
@@ -641,7 +656,7 @@ static const MppSocInfo mpp_soc_infos[] = {
"rk3568", "rk3568",
ROCKCHIP_SOC_RK3568, ROCKCHIP_SOC_RK3568,
HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC,
{ &vdpu34x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp, NULL, }, { &vdpu34x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, },
{ &vepu540, &vepu2, NULL, NULL, }, { &vepu540, &vepu2, NULL, NULL, },
}, },
{ /* { /*
@@ -653,8 +668,8 @@ static const MppSocInfo mpp_soc_infos[] = {
*/ */
"rk3588", "rk3588",
ROCKCHIP_SOC_RK3588, ROCKCHIP_SOC_RK3588,
HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC | HAVE_AV1DEC, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC | HAVE_AV1DEC | HAVE_AVSDEC,
{ &vdpu38x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp, &av1d}, { &vdpu38x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp, &av1d, &avspd},
{ &vepu58x, &vepu2, &vepu2_jpeg, NULL, }, { &vepu58x, &vepu2, &vepu2_jpeg, NULL, },
}, },
}; };