diff --git a/mpp/codec/dec/vp9/vp9d_parser.c b/mpp/codec/dec/vp9/vp9d_parser.c
index 60528360..04835848 100644
--- a/mpp/codec/dec/vp9/vp9d_parser.c
+++ b/mpp/codec/dec/vp9/vp9d_parser.c
@@ -407,7 +407,10 @@ static RK_S32 vp9_alloc_frame(Vp9CodecContext *ctx, VP9Frame *frame)
 
         mpp_frame_set_fbc_hdr_stride(frame->f, fbc_hdr_stride);
     } else {
-        mpp_slots_set_prop(s->slots, SLOTS_HOR_ALIGN, mpp_align_256_odd);
+        if (mpp_get_soc_type() == ROCKCHIP_SOC_RK3576)
+            mpp_slots_set_prop(s->slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
+        else
+            mpp_slots_set_prop(s->slots, SLOTS_HOR_ALIGN, mpp_align_256_odd);
         mpp_slots_set_prop(s->slots, SLOTS_VER_ALIGN, mpp_align_64);
         if (MPP_FRAME_FMT_IS_TILE(s->cfg->base.out_fmt))
             mpp_frame_set_fmt(frame->f, ctx->pix_fmt | ((s->cfg->base.out_fmt & (MPP_FRAME_TILE_FLAG))));
diff --git a/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.c b/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.c
index fcf897f2..b3484ec7 100644
--- a/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.c
+++ b/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.c
@@ -75,12 +75,6 @@ static RK_U32 avs2d_ver_align(RK_U32 val)
     return MPP_ALIGN(val, 16);
 }
 
-static RK_U32 avs2d_hor_align(RK_U32 val)
-{
-
-    return MPP_ALIGN(val, 16);
-}
-
 static RK_U32 avs2d_len_align(RK_U32 val)
 {
     return (2 * MPP_ALIGN(val, 16));
@@ -515,7 +509,7 @@ MPP_RET hal_avs2d_vdpu383_init(void *hal, MppHalCfg *cfg)
         reg_ctx->sclst_offset = reg_ctx->reg_buf[0].offset_sclst;
     }
 
-    mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, avs2d_hor_align);
+    mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
     mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, avs2d_ver_align);
     mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, avs2d_len_align);
 
diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu383.c b/mpp/hal/rkdec/h264d/hal_h264d_vdpu383.c
index 40fa984c..bc2e6fd2 100644
--- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu383.c
+++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu383.c
@@ -120,11 +120,6 @@ static RK_U32 rkv_hor_align(RK_U32 val)
     return MPP_ALIGN(val, 16);
 }
 
-static RK_U32 rkv_hor_align_256_odds(RK_U32 val)
-{
-    return (MPP_ALIGN(val, 256) | 256);
-}
-
 static RK_U32 rkv_len_align(RK_U32 val)
 {
     return (2 * MPP_ALIGN(val, 16));
@@ -1052,7 +1047,7 @@ MPP_RET vdpu383_h264d_control(void *hal, MpiCmd cmd_type, void *param)
         if (MPP_FRAME_FMT_IS_FBC(fmt)) {
             vdpu383_afbc_align_calc(p_hal->frame_slots, (MppFrame)param, 16);
         } else if (imgwidth > 1920 || imgheight > 1088) {
-            mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, rkv_hor_align_256_odds);
+            mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
         }
     } break;
     case MPP_DEC_SET_OUTPUT_FORMAT: {
diff --git a/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c b/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c
index e24bc555..ad80cd70 100644
--- a/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c
+++ b/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c
@@ -1411,6 +1411,8 @@ static MPP_RET hal_h265d_vdpu383_control(void *hal, MpiCmd cmd_type, void *param
     case MPP_DEC_SET_FRAME_INFO: {
         MppFrame frame = (MppFrame)param;
         MppFrameFormat fmt = mpp_frame_get_fmt(frame);
+        RK_U32 imgwidth = mpp_frame_get_width((MppFrame)param);
+        RK_U32 imgheight = mpp_frame_get_height((MppFrame)param);
 
         if (fmt == MPP_FMT_YUV422SP) {
             mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, rkv_len_align_422);
@@ -1419,6 +1421,8 @@ static MPP_RET hal_h265d_vdpu383_control(void *hal, MpiCmd cmd_type, void *param
         }
         if (MPP_FRAME_FMT_IS_FBC(fmt)) {
             vdpu383_afbc_align_calc(p_hal->slots, frame, 16);
+        } else if (imgwidth > 1920 || imgheight > 1088) {
+            mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
         }
         break;
     }
diff --git a/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.c b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.c
index 37f640fb..76e7ae6a 100644
--- a/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.c
+++ b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.c
@@ -336,7 +336,7 @@ static MPP_RET hal_vp9d_vdpu383_init(void *hal, MppHalCfg *cfg)
 
     hw_ctx->mv_base_addr = -1;
     hw_ctx->pre_mv_base_addr = -1;
-    mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, vp9_hor_align);
+    mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
     mpp_slots_set_prop(p_hal->slots, SLOTS_VER_ALIGN, vp9_ver_align);
 
     if (p_hal->group == NULL) {
@@ -860,8 +860,8 @@ static MPP_RET hal_vp9d_vdpu383_gen_regs(void *hal, HalTaskInfo *task)
             /* error stride */
             vp9_hw_regs->vp9d_paras.reg80_error_ref_hor_virstride = w / 64;
         } else {
-            sw_y_hor_virstride = (vp9_hor_align((pic_param->width * bit_depth) >> 3) >> 4);
-            sw_uv_hor_virstride = (vp9_hor_align((pic_param->width * bit_depth) >> 3) >> 4);
+            sw_y_hor_virstride = (mpp_align_128_odd_plus_64((pic_param->width * bit_depth) >> 3) >> 4);
+            sw_uv_hor_virstride = (mpp_align_128_odd_plus_64((pic_param->width * bit_depth) >> 3) >> 4);
             sw_y_virstride = pic_h[0] * sw_y_hor_virstride;
             sw_uv_virstride = sw_y_virstride / 2;
 
@@ -948,7 +948,7 @@ static MPP_RET hal_vp9d_vdpu383_gen_regs(void *hal, HalTaskInfo *task)
         if (fbc_en) {
             y_hor_virstride = uv_hor_virstride = MPP_ALIGN(ref_frame_width_y, 64) / 64;
         } else {
-            y_hor_virstride = uv_hor_virstride = (vp9_hor_align((ref_frame_width_y * bit_depth) >> 3) >> 4);
+            y_hor_virstride = uv_hor_virstride = (mpp_align_128_odd_plus_64((ref_frame_width_y * bit_depth) >> 3) >> 4);
         }
         y_virstride = y_hor_virstride * pic_h[0];
 
@@ -1289,7 +1289,7 @@ static MPP_RET hal_vp9d_vdpu383_control(void *hal, MpiCmd cmd_type, void *param)
         if (MPP_FRAME_FMT_IS_FBC(fmt)) {
             vdpu383_afbc_align_calc(p_hal->slots, (MppFrame)param, 0);
         } else {
-            mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, vp9_hor_align);
+            mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
         }
     } break;
     default : {
diff --git a/mpp/hal/vpu/av1d/hal_av1d_vdpu383.c b/mpp/hal/vpu/av1d/hal_av1d_vdpu383.c
index 80558ea7..b4a9f2c7 100644
--- a/mpp/hal/vpu/av1d/hal_av1d_vdpu383.c
+++ b/mpp/hal/vpu/av1d/hal_av1d_vdpu383.c
@@ -2569,6 +2569,8 @@ MPP_RET vdpu383_av1d_control(void *hal, MpiCmd cmd_type, void *param)
         }
         if (MPP_FRAME_FMT_IS_FBC(fmt)) {
             vdpu383_afbc_align_calc(p_hal->slots, (MppFrame)param, 16);
+        } else if (imgwidth > 1920 || imgheight > 1088) {
+            mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
         }
         break;
     }
diff --git a/osal/inc/mpp_common.h b/osal/inc/mpp_common.h
index 60a0b20f..fec223db 100644
--- a/osal/inc/mpp_common.h
+++ b/osal/inc/mpp_common.h
@@ -224,6 +224,7 @@ RK_U32 mpp_align_16(RK_U32 val);
 RK_U32 mpp_align_64(RK_U32 val);
 RK_U32 mpp_align_128(RK_U32 val);
 RK_U32 mpp_align_256_odd(RK_U32 val);
+RK_U32 mpp_align_128_odd_plus_64(RK_U32 val);
 
 #ifdef __cplusplus
 }
diff --git a/osal/mpp_common.cpp b/osal/mpp_common.cpp
index ae612ee6..7baa8322 100644
--- a/osal/mpp_common.cpp
+++ b/osal/mpp_common.cpp
@@ -126,3 +126,8 @@ RK_U32 mpp_align_256_odd(RK_U32 val)
 {
     return MPP_ALIGN(val, 256) | 256;
 }
+
+RK_U32 mpp_align_128_odd_plus_64(RK_U32 val)
+{
+    return ((MPP_ALIGN(val, 128) | 128) + 64);
+}