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[mpp]: add /dev/mpp_service support

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Add a new ioctl mode for kernel-4.19 or later.
Tips:
    1. There will be only one device /dev/mpp_service in kernel.
       User should use client type to distinguish different device.
    2. Each codec use the same function as before.
    3. Ioctl magic changes from VPU_IOC to MPP_IOC.
    4. Update structure for ioctl argument.
	Original structure:
	    data_ptr | size
	In this mode has many sortcommings:
	a) Need many ioctl cmd for different requirements.
	b) Data_ptr not to differ library for 32 or 64 system.
	c) Contain only one info ioctl once.

    New data structure:
        cmd_type | flags | size | offset | data_ptr
    a) Cmd_type works like previous ioctl cmd.
    b) Flags is extend to mark current data for any purpose.
    c) Size is the same as before.
    d) Data_ptr use 32 bits build in 32 system while 64 bits in 64 system.

kernel-4.19 related commit:
ib94ac0df876dfcc786b25ed3de6a68d861d2ef1e
cda9d27c62017309519bcbf8fe91057dfdc21076

Change-Id: I13d54a2e4823b7378265f100540916a22f62b9d4
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
This commit is contained in:
Ding Wei
2019-11-12 09:15:17 +08:00
committed by Herman Chen
parent a9d6b3a994
commit 7d05e33de8
39 changed files with 375 additions and 152 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
inc/vpu.h
View File

@@ -41,7 +41,6 @@ extern "C"
#define VPU_REG_NUM_ENC (96)
typedef enum {
VPU_ENC = 0x0,
VPU_DEC = 0x1,
VPU_PP = 0x2,
@@ -50,9 +49,8 @@ typedef enum {
VPU_DEC_RKV = 0x5,
VPU_ENC_RKV = 0x6,
VPU_DEC_AVS = 0x7,
VPU_ENC_H265E = 0x8,
VPU_ENC_VEPU22 = 0x8,
VPU_TYPE_BUTT ,
} VPU_CLIENT_TYPE;
/* Hardware decoder configuration description */

4
mpp/hal/common/h264/hal_h264e_api.c
View File

@@ -57,7 +57,7 @@ MPP_RET hal_h264e_init(void *hal, MppHalCfg *cfg)
api->flush = hal_h264e_rkv_flush;
api->control = hal_h264e_rkv_control;
hw_cfg->hw_type = H264E_RKV;
} else if (vcodec_type & HAVE_VPU2) {
} else if (vcodec_type & HAVE_VEPU2) {
api->init = hal_h264e_vepu2_init;
api->deinit = hal_h264e_vepu2_deinit;
api->reg_gen = hal_h264e_vepu2_gen_regs;
@@ -67,7 +67,7 @@ MPP_RET hal_h264e_init(void *hal, MppHalCfg *cfg)
api->flush = hal_h264e_vepu2_flush;
api->control = hal_h264e_vepu2_control;
hw_cfg->hw_type = H264E_VPU;
} else if (vcodec_type & HAVE_VPU1) {
} else if (vcodec_type & HAVE_VEPU1) {
api->init = hal_h264e_vepu1_init;
api->deinit = hal_h264e_vepu1_deinit;
api->reg_gen = hal_h264e_vepu1_gen_regs;

9
mpp/hal/common/h265/hal_h265e_api.c
View File

@@ -47,14 +47,7 @@ MPP_RET hal_h265e_init(void *hal, MppHalCfg *cfg)
memset(ctx, 0, sizeof(HalH265eCtx));
p_api = &ctx->hal_api;
// NOTE: rk3036 and rk3228 do NOT have jpeg encoder
if (NULL == mpp_get_vcodec_dev_name(MPP_CTX_ENC, MPP_VIDEO_CodingHEVC)) {
mpp_err("SOC %s do NOT support h265 encoding\n", mpp_get_soc_name());
ret = MPP_ERR_INIT;
goto FAIL;
}
if (!(mpp_get_vcodec_type() & HAVE_H265ENC)) {
if (!(mpp_get_vcodec_type() & HAVE_VEPU22)) {
mpp_err("cannot find hardware.\n");
ret = MPP_ERR_INIT;
goto FAIL;

2
mpp/hal/rkdec/avsd/hal_avsd_api.c
View File

@@ -120,7 +120,7 @@ MPP_RET hal_avsd_init(void *decoder, MppHalCfg *cfg)
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingAVS, /* coding */
.platform = 0, /* platform */
.platform = HAVE_AVSDEC, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&p_hal->dev_ctx, &dev_cfg);

10
mpp/hal/rkdec/h264d/hal_h264d_api.c
View File

@@ -101,16 +101,16 @@ MPP_RET hal_h264d_init(void *hal, MppHalCfg *cfg)
RK_U32 vcodec_type = 0;
mpp_env_get_u32("use_mpp_mode", &mode, 0);
vcodec_type = mpp_get_vcodec_type();
mpp_assert(vcodec_type & (HAVE_RKVDEC | HAVE_VPU1 | HAVE_VPU2));
mpp_assert(vcodec_type & (HAVE_RKVDEC | HAVE_VDPU1 | HAVE_VDPU2));
if ((mode <= RKVDEC_MODE) && (vcodec_type & HAVE_RKVDEC)) {
hard_mode = RKVDEC_MODE;
hard_platform = HAVE_RKVDEC;
} else if (vcodec_type & HAVE_VPU1) {
} else if (vcodec_type & HAVE_VDPU1) {
hard_mode = VDPU1_MODE;
hard_platform = HAVE_VPU1;
} else if (vcodec_type & HAVE_VPU2) {
hard_platform = HAVE_VDPU1;
} else if (vcodec_type & HAVE_VDPU2) {
hard_mode = VDPU2_MODE;
hard_platform = HAVE_VPU2;
hard_platform = HAVE_VDPU2;
}
H264D_DBG(H264D_DBG_HARD_MODE, "set_mode=%d, hw_spt=%08x, use_mode=%d\n",
mode, vcodec_type, hard_mode);

7
mpp/hal/rkdec/h265d/hal_h265d_reg.c
View File

@@ -404,6 +404,8 @@ MPP_RET hal_h265d_init(void *hal, MppHalCfg *cfg)
{
RK_S32 ret = 0;
RK_U32 vcodec_type = 0;
RK_U32 platform = 0;
h265d_reg_context_t *reg_cxt = (h265d_reg_context_t *)hal;
if (NULL == reg_cxt) {
@@ -430,12 +432,13 @@ MPP_RET hal_h265d_init(void *hal, MppHalCfg *cfg)
return MPP_ERR_MALLOC;
}
reg_cxt->packet_slots = cfg->packet_slots;
vcodec_type = mpp_get_vcodec_type();
platform = (vcodec_type & HAVE_HEVC_DEC) ? HAVE_HEVC_DEC : HAVE_RKVDEC;
///<- mpp_device_init
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingHEVC, /* coding */
.platform = 0, /* platform */
.platform = platform, /* platform */
.pp_enable = 0, /* pp_enable */
};

2
mpp/hal/rkdec/vp9d/hal_vp9d_api.c
View File

@@ -279,7 +279,7 @@ MPP_RET hal_vp9d_init(void *hal, MppHalCfg *cfg)
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingVP9, /* coding */
.platform = 0, /* platform */
.platform = HAVE_RKVDEC, /* platform */
.pp_enable = 0, /* pp_enable */
};

2
mpp/hal/rkenc/h264e/hal_h264e_rkv.c
View File

@@ -338,7 +338,7 @@ MPP_RET hal_h264e_rkv_init(void *hal, MppHalCfg *cfg)
MppDevCfg dev_cfg = {
.type = MPP_CTX_ENC, /* type */
.coding = MPP_VIDEO_CodingAVC, /* coding */
.platform = 0, /* platform */
.platform = HAVE_RKVENC, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);

4
mpp/hal/vpu/h263d/hal_h263d_api.c
View File

@@ -94,9 +94,9 @@ static MPP_RET hal_h263d_init(void *hal, MppHalCfg *cfg)
p_hal->pkt_slots = cfg->packet_slots;
hw_flag = mpp_get_vcodec_type();
if (hw_flag & HAVE_VPU2)
if (hw_flag & HAVE_VDPU2)
hard_mode = VDPU2_MODE;
if (hw_flag & HAVE_VPU1)
if (hw_flag & HAVE_VDPU1)
hard_mode = VDPU1_MODE;
switch (hard_mode) {

2
mpp/hal/vpu/h263d/hal_h263d_vdpu1.c
View File

@@ -136,7 +136,7 @@ MPP_RET hal_vpu1_h263d_init(void *hal, MppHalCfg *cfg)
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingH263, /* coding */
.platform = 0, /* platform */
.platform = HAVE_VDPU1, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);

2
mpp/hal/vpu/h263d/hal_h263d_vdpu2.c
View File

@@ -136,7 +136,7 @@ MPP_RET hal_vpu2_h263d_init(void *hal, MppHalCfg *cfg)
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingH263, /* coding */
.platform = 0, /* platform */
.platform = HAVE_VDPU2, /* platform */
.pp_enable = 0, /* pp_enable */
};

2
mpp/hal/vpu/h264e/hal_h264e_vepu1.c
View File

@@ -55,7 +55,7 @@ MPP_RET hal_h264e_vepu1_init(void *hal, MppHalCfg *cfg)
MppDevCfg dev_cfg = {
.type = MPP_CTX_ENC, /* type */
.coding = MPP_VIDEO_CodingAVC, /* coding */
.platform = 0, /* platform */
.platform = HAVE_VEPU1, /* platform */
.pp_enable = 0, /* pp_enable */
};

2
mpp/hal/vpu/h264e/hal_h264e_vepu2.c
View File

@@ -55,7 +55,7 @@ MPP_RET hal_h264e_vepu2_init(void *hal, MppHalCfg *cfg)
MppDevCfg dev_cfg = {
.type = MPP_CTX_ENC, /* type */
.coding = MPP_VIDEO_CodingAVC, /* coding */
.platform = 0, /* platform */
.platform = HAVE_VEPU2, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);

2
mpp/hal/vpu/h265e/hal_h265e_vepu22.c
View File

@@ -1837,7 +1837,7 @@ MPP_RET hal_h265e_vepu22_init(void *hal, MppHalCfg *cfg)
MppDevCfg dev_cfg = {
.type = MPP_CTX_ENC, /* type */
.coding = MPP_VIDEO_CodingHEVC, /* coding */
.platform = 0, /* platform */
.platform = HAVE_VEPU22, /* platform */
.pp_enable = 0, /* pp_enable */
};

4
mpp/hal/vpu/jpegd/hal_jpegd_api.c
View File

@@ -81,9 +81,9 @@ static MPP_RET hal_jpegd_init (void *hal, MppHalCfg *cfg)
p_api = &self->hal_api;
hw_flag = mpp_get_vcodec_type();
if (hw_flag & HAVE_VPU2)
if (hw_flag & HAVE_VDPU2)
hard_mode = VDPU2_MODE;
if (hw_flag & HAVE_VPU1)
if (hw_flag & HAVE_VDPU1)
hard_mode = VDPU1_MODE;
switch (hard_mode) {

4
mpp/hal/vpu/jpegd/hal_jpegd_vdpu1.c
View File

@@ -748,7 +748,7 @@ MPP_RET hal_jpegd_vdpu1_init(void *hal, MppHalCfg *cfg)
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingMJPEG, /* coding */
.platform = 0, /* platform */
.platform = HAVE_VDPU1, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&JpegHalCtx->dev_ctx, &dev_cfg);
@@ -892,7 +892,7 @@ MPP_RET hal_jpegd_vdpu1_gen_regs(void *hal, HalTaskInfo *syn)
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingMJPEG, /* coding */
.platform = 0, /* platform */
.platform = HAVE_VDPU1, /* platform */
.pp_enable = 1, /* pp_enable */
};
ret = mpp_device_init(&JpegHalCtx->dev_ctx, &dev_cfg);

4
mpp/hal/vpu/jpegd/hal_jpegd_vdpu2.c
View File

@@ -735,7 +735,7 @@ MPP_RET hal_jpegd_vdpu2_init(void *hal, MppHalCfg *cfg)
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingMJPEG, /* coding */
.platform = 0, /* platform */
.platform = HAVE_VDPU2, /* platform */
.pp_enable = 0, /* pp_enable */
};
@@ -878,7 +878,7 @@ MPP_RET hal_jpegd_vdpu2_gen_regs(void *hal, HalTaskInfo *syn)
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingMJPEG, /* coding */
.platform = 0, /* platform */
.platform = HAVE_VDPU2, /* platform */
.pp_enable = 1, /* pp_enable */
};
ret = mpp_device_init(&JpegHalCtx->dev_ctx, &dev_cfg);

4
mpp/hal/vpu/jpege/hal_jpege_api.c
View File

@@ -99,9 +99,9 @@ static MPP_RET hal_jpege_init(void *hal, MppHalCfg *cfg)
}
hw_flag = mpp_get_vcodec_type();
if (hw_flag & HAVE_VPU2)
if (hw_flag & HAVE_VEPU2)
hard_mode = VDPU2_MODE;
if (hw_flag & HAVE_VPU1)
if (hw_flag & HAVE_VEPU1)
hard_mode = VDPU1_MODE;
switch (hard_mode) {

2
mpp/hal/vpu/jpege/hal_jpege_vepu1.c
View File

@@ -62,7 +62,7 @@ MPP_RET hal_jpege_vepu1_init(void *hal, MppHalCfg *cfg)
MppDevCfg dev_cfg = {
.type = MPP_CTX_ENC, /* type */
.coding = MPP_VIDEO_CodingMJPEG, /* coding */
.platform = 0, /* platform */
.platform = HAVE_VEPU1, /* platform */
.pp_enable = 0, /* pp_enable */
};

2
mpp/hal/vpu/jpege/hal_jpege_vepu2.c
View File

@@ -61,7 +61,7 @@ MPP_RET hal_jpege_vepu2_init(void *hal, MppHalCfg *cfg)
MppDevCfg dev_cfg = {
.type = MPP_CTX_ENC, /* type */
.coding = MPP_VIDEO_CodingMJPEG, /* coding */
.platform = 0, /* platform */
.platform = HAVE_VEPU2, /* platform */
.pp_enable = 0, /* pp_enable */
};

4
mpp/hal/vpu/m2vd/hal_m2vd_api.c
View File

@@ -86,9 +86,9 @@ static MPP_RET hal_m2vd_init (void *hal, MppHalCfg *cfg)
mpp_env_get_u32("m2vh_debug", &m2vh_debug, 0);
hw_flag = mpp_get_vcodec_type();
if (hw_flag & HAVE_VPU1)
if (hw_flag & HAVE_VDPU1)
hard_mode = VDPU1_MODE;
if (hw_flag & HAVE_VPU2)
if (hw_flag & HAVE_VDPU2)
hard_mode = VDPU2_MODE;
switch (hard_mode) {

2
mpp/hal/vpu/m2vd/hal_m2vd_vdpu1.c
View File

@@ -42,7 +42,7 @@ MPP_RET hal_m2vd_vdpu1_init(void *hal, MppHalCfg *cfg)
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingMPEG2, /* coding */
.platform = 0, /* platform */
.platform = HAVE_VDPU1, /* platform */
.pp_enable = 0, /* pp_enable */
};

2
mpp/hal/vpu/m2vd/hal_m2vd_vdpu2.c
View File

@@ -45,7 +45,7 @@ MPP_RET hal_m2vd_vdpu2_init(void *hal, MppHalCfg *cfg)
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingMPEG2, /* coding */
.platform = 0, /* platform */
.platform = HAVE_VDPU2, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&p->dev_ctx, &dev_cfg);

6
mpp/hal/vpu/mpg4d/hal_m4vd_api.c
View File

@@ -58,11 +58,11 @@ MPP_RET hal_vpu_mpg4d_init(void *hal, MppHalCfg *cfg)
p_api = &p_hal->hal_api;
hw_flag = mpp_get_vcodec_type();
mpp_assert(hw_flag & (HAVE_VPU2 | HAVE_VPU1));
mpp_assert(hw_flag & (HAVE_VDPU2 | HAVE_VDPU1));
if (hw_flag & HAVE_VPU2)
if (hw_flag & HAVE_VDPU2)
hard_mode = VDPU2_MODE;
if (hw_flag & HAVE_VPU1)
if (hw_flag & HAVE_VDPU1)
hard_mode = VDPU1_MODE;
switch (hard_mode) {

2
mpp/hal/vpu/mpg4d/hal_m4vd_vdpu1.c
View File

@@ -260,7 +260,7 @@ MPP_RET vdpu1_mpg4d_init(void *hal, MppHalCfg *cfg)
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingMPEG4, /* coding */
.platform = 0, /* platform */
.platform = HAVE_VDPU1, /* platform */
.pp_enable = 0, /* pp_enable */
};

2
mpp/hal/vpu/mpg4d/hal_m4vd_vdpu2.c
View File

@@ -258,7 +258,7 @@ MPP_RET vdpu2_mpg4d_init(void *hal, MppHalCfg *cfg)
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingMPEG4, /* coding */
.platform = 0, /* platform */
.platform = HAVE_VDPU2, /* platform */
.pp_enable = 0, /* pp_enable */
};

4
mpp/hal/vpu/vp8d/hal_vp8d_api.c
View File

@@ -108,9 +108,9 @@ static MPP_RET hal_vp8d_init (void *hal, MppHalCfg *cfg)
p_api = &self->hal_api;
hw_flag = mpp_get_vcodec_type();
if (hw_flag & HAVE_VPU1)
if (hw_flag & HAVE_VDPU1)
hard_mode = VDPU1_MODE;
if (hw_flag & HAVE_VPU2)
if (hw_flag & HAVE_VDPU2)
hard_mode = VDPU2_MODE;
switch (hard_mode) {

2
mpp/hal/vpu/vp8d/hal_vp8d_vdpu1.c
View File

@@ -56,7 +56,7 @@ MPP_RET hal_vp8d_vdpu1_init(void *hal, MppHalCfg *cfg)
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingVP8, /* coding */
.platform = 0, /* platform */
.platform = HAVE_VDPU1, /* platform */
.pp_enable = 0, /* pp_enable */
};

2
mpp/hal/vpu/vp8d/hal_vp8d_vdpu2.c
View File

@@ -56,7 +56,7 @@ MPP_RET hal_vp8d_vdpu2_init(void *hal, MppHalCfg *cfg)
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingVP8, /* coding */
.platform = 0, /* platform */
.platform = HAVE_VDPU2, /* platform */
.pp_enable = 0, /* pp_enable */
};

4
mpp/hal/vpu/vp8e/hal_vp8e_api.c
View File

@@ -97,9 +97,9 @@ static MPP_RET hal_vp8e_init(void *hal, MppHalCfg *cfg)
p_api = &ctx->hal_api;
{
RK_U32 hw_flag = mpp_get_vcodec_type();
if (hw_flag & HAVE_VPU2)
if (hw_flag & HAVE_VEPU2)
hard_mode = VDPU2_MODE;
else if (hw_flag & HAVE_VPU1)
else if (hw_flag & HAVE_VEPU1)
hard_mode = VDPU1_MODE;
else {
mpp_err_f("Failed to init due to unsupported hard mode, hw_flag = %d\n", hw_flag);

2
mpp/hal/vpu/vp8e/hal_vp8e_vepu1.c
View File

@@ -305,7 +305,7 @@ MPP_RET hal_vp8e_vepu1_init(void *hal, MppHalCfg *cfg)
MppDevCfg dev_cfg = {
.type = MPP_CTX_ENC, /* type */
.coding = MPP_VIDEO_CodingVP8, /* coding */
.platform = 0, /* platform */
.platform = HAVE_VEPU1, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);

2
mpp/hal/vpu/vp8e/hal_vp8e_vepu2.c
View File

@@ -307,7 +307,7 @@ MPP_RET hal_vp8e_vepu2_init(void *hal, MppHalCfg *cfg)
MppDevCfg dev_cfg = {
.type = MPP_CTX_ENC, /* type */
.coding = MPP_VIDEO_CodingVP8, /* coding */
.platform = 0, /* platform */
.platform = HAVE_VEPU2, /* platform */
.pp_enable = 0, /* pp_enable */
};

35
mpp/hal/worker/inc/mpp_device.h
View File

@@ -20,6 +20,14 @@
#include "rk_type.h"
#include "mpp_err.h"
/* define flags for mpp_request */
#define MPP_FLAGS_MULTI_MSG (0x00000001)
#define MPP_FLAGS_LAST_MSG (0x00000002)
#define MPP_FLAGS_REG_FD_NO_TRANS (0x00000004)
#define MPP_FLAGS_SCL_FD_NO_TRANS (0x00000008)
#define MPP_FLAGS_SECURE_MODE (0x00010000)
/* mpp service capability description */
typedef enum MppDevCmd_e {
MPP_DEV_GET_START = 0,
@@ -36,6 +44,33 @@ typedef enum MppDevCmd_e {
MPP_DEV_PROP_BUTT,
} MppDevCmd;
enum MPP_DEV_COMMAND_TYPE {
MPP_CMD_QUERY_BASE = 0,
MPP_CMD_PROBE_HW_SUPPORT = MPP_CMD_QUERY_BASE + 0,
MPP_CMD_PROBE_IOMMU_STATUS = MPP_CMD_QUERY_BASE + 1,
MPP_CMD_INIT_BASE = 0x100,
MPP_CMD_INIT_CLIENT_TYPE = MPP_CMD_INIT_BASE + 0,
MPP_CMD_INIT_DRIVER_DATA = MPP_CMD_INIT_BASE + 1,
MPP_CMD_INIT_TRANS_TABLE = MPP_CMD_INIT_BASE + 2,
MPP_CMD_SEND_BASE = 0x200,
MPP_CMD_SET_REG = MPP_CMD_SEND_BASE + 0,
MPP_CMD_SET_VEPU22_CFG = MPP_CMD_SEND_BASE + 1,
MPP_CMD_SET_RKVENC_OSD_PLT = MPP_CMD_SEND_BASE + 2,
MPP_CMD_SET_RKVENC_L2_REG = MPP_CMD_SEND_BASE + 3,
MPP_CMD_SET_REG_ADDR_OFFSET = MPP_CMD_SEND_BASE + 4,
MPP_CMD_POLL_BASE = 0x300,
MPP_CMD_GET_REG = MPP_CMD_POLL_BASE + 0,
MPP_CMD_CONTROL_BASE = 0x400,
MPP_CMD_RESET_SESSION = MPP_CMD_CONTROL_BASE + 0,
MPP_CMD_TRANS_FD_TO_IOVA = MPP_CMD_CONTROL_BASE + 1,
MPP_CMD_BUTT,
};
typedef struct MppDevCfg_t {
// input
MppCtxType type;

179
mpp/hal/worker/mpp_device/mpp_device.c
View File

@@ -44,11 +44,23 @@
#define VPU_IOC_WRITE(nr, size) _IOC(_IOC_WRITE, VPU_IOC_MAGIC, (nr), (size))
/* Use 'v' as magic number */
#define MPP_IOC_MAGIC 'v'
#define MPP_IOC_CFG_V1 _IOW(MPP_IOC_MAGIC, 1, unsigned int)
typedef struct MppReq_t {
RK_U32 *req;
RK_U32 size;
} MppReq;
typedef struct mppReqV1_t {
RK_U32 cmd;
RK_U32 flag;
RK_U32 size;
RK_U32 offset;
RK_U64 data_ptr;
} MppReqV1;
#define MAX_TIME_RECORD 4
typedef struct MppDevCtxImpl_t {
@@ -59,6 +71,7 @@ typedef struct MppDevCtxImpl_t {
RK_U32 mmu_status; // 0 disable, 1 enable
RK_U32 pp_enable; // postprocess, 0 disable, 1 enable
RK_S32 vpu_fd;
RK_S32 ioctl_version; // 0 original version, > 1 for others version
RK_S64 time_start[MAX_TIME_RECORD];
RK_S64 time_end[MAX_TIME_RECORD];
@@ -69,14 +82,57 @@ typedef struct MppDevCtxImpl_t {
#define MPP_DEVICE_DBG_REG (0x00000001)
#define MPP_DEVICE_DBG_TIME (0x00000002)
#define MPP_DEVICE_DBG_HW_SUPPORT (0x00000004)
#if __SIZEOF_POINTER__ == 4
#define REQ_DATA_PTR(ptr) ((RK_U32)ptr)
#elif __SIZEOF_POINTER__ == 8
#define REQ_DATA_PTR(ptr) ((RK_U64)ptr)
#endif
static RK_U32 mpp_device_debug = 0;
static RK_S32 mpp_device_set_client_type(int dev, RK_S32 client_type)
static RK_U32 mpp_probe_hw_support(RK_S32 dev)
{
static RK_S32 mpp_device_ioctl_version = -1;
RK_S32 ret;
RK_U32 flag = 0;
MppReqV1 mpp_req;
mpp_req.cmd = MPP_CMD_PROBE_HW_SUPPORT;
mpp_req.flag = 0;
mpp_req.size = 0;
mpp_req.offset = 0;
mpp_req.data_ptr = REQ_DATA_PTR(&flag);
ret = (RK_S32)ioctl(dev, MPP_IOC_CFG_V1, &mpp_req);
if (ret) {
mpp_err_f("probe error.\n");
flag = 0;
} else {
mpp_refresh_vcodec_type(flag);
if (mpp_device_debug & MPP_DEVICE_DBG_HW_SUPPORT)
mpp_log_f("vcodec_support=%08x\n", flag);
}
return flag;
}
static RK_S32 mpp_device_set_client_type(MppDevCtx ctx, int dev, RK_S32 client_type)
{
RK_S32 ret;
static RK_S32 mpp_device_ioctl_version = -1;
MppDevCtxImpl *p = (MppDevCtxImpl *)ctx;
if (p->ioctl_version > 0) {
MppReqV1 mpp_req;
RK_U32 client_data = client_type;
mpp_req.cmd = MPP_CMD_INIT_CLIENT_TYPE;
mpp_req.flag = 0;
mpp_req.size = sizeof(client_data);
mpp_req.offset = 0;
mpp_req.data_ptr = REQ_DATA_PTR(&client_data);
ret = (RK_S32)ioctl(dev, MPP_IOC_CFG_V1, &mpp_req);
} else {
if (mpp_device_ioctl_version < 0) {
ret = ioctl(dev, VPU_IOC_SET_CLIENT_TYPE, (unsigned long)client_type);
if (!ret) {
@@ -86,10 +142,6 @@ static RK_S32 mpp_device_set_client_type(int dev, RK_S32 client_type)
if (!ret)
mpp_device_ioctl_version = 1;
}
if (ret)
mpp_err_f("can not find valid client type ioctl\n");
mpp_assert(ret == 0);
} else {
RK_U32 cmd = (mpp_device_ioctl_version == 0) ?
@@ -98,7 +150,7 @@ static RK_S32 mpp_device_set_client_type(int dev, RK_S32 client_type)
ret = ioctl(dev, cmd, client_type);
}
}
if (ret)
mpp_err_f("set client type failed ret %d errno %d\n", ret, errno);
@@ -118,16 +170,24 @@ static RK_S32 mpp_device_get_client_type(MppDevCtx ctx, MppCtxType type, MppCodi
p = (MppDevCtxImpl *)ctx;
if (p->ioctl_version > 0) {
if (p->pp_enable)
client_type = (p->platform & HAVE_VDPU1) ?
VPU_CLIENT_VDPU1_PP : VPU_CLIENT_VDPU2_PP;
else {
RK_U32 i = 0;
while (i < 32 && !((p->platform >> i) & 0x1)) i++;
client_type = i;
}
} else { /* ioctl mode is original */
if (type == MPP_CTX_ENC)
client_type = VPU_ENC;
else { /* MPP_CTX_DEC */
client_type = VPU_DEC;
if (p->pp_enable)
client_type = VPU_DEC_PP;
else /* MPP_CTX_DEC */
client_type = p->pp_enable ? VPU_DEC_PP : VPU_DEC;
}
(void) type;
return client_type;
}
@@ -156,6 +216,7 @@ MPP_RET mpp_device_init(MppDevCtx *ctx, MppDevCfg *cfg)
p->type = cfg->type;
p->platform = cfg->platform;
p->pp_enable = cfg->pp_enable;
p->ioctl_version = mpp_get_ioctl_version();
if (p->platform)
name = mpp_get_platform_dev_name(p->type, p->coding, p->platform);
@@ -164,9 +225,15 @@ MPP_RET mpp_device_init(MppDevCtx *ctx, MppDevCfg *cfg)
if (name) {
dev = open(name, O_RDWR);
if (dev > 0) {
RK_S32 client_type = mpp_device_get_client_type(p, p->type, p->coding);
RK_S32 ret = mpp_device_set_client_type(dev, client_type);
RK_S32 client_type;
RK_S32 ret;
/* if ioctl_version=1, query hw supprot*/
if (p->ioctl_version > 0)
mpp_probe_hw_support(dev);
client_type = mpp_device_get_client_type(p, p->type, p->coding);
ret = mpp_device_set_client_type(p, dev, client_type);
if (ret) {
close(dev);
dev = -2;
@@ -207,7 +274,6 @@ MPP_RET mpp_device_deinit(MppDevCtx ctx)
MPP_RET mpp_device_send_reg(MppDevCtx ctx, RK_U32 *regs, RK_U32 nregs)
{
MPP_RET ret;
MppReq req;
MppDevCtxImpl *p;
if (NULL == ctx || NULL == regs) {
@@ -225,17 +291,28 @@ MPP_RET mpp_device_send_reg(MppDevCtx ctx, RK_U32 *regs, RK_U32 nregs)
}
}
nregs *= sizeof(RK_U32);
req.req = regs;
req.size = nregs;
if (mpp_device_debug & MPP_DEVICE_DBG_TIME) {
p->time_start[p->idx_send++] = mpp_time();
if (p->idx_send >= MAX_TIME_RECORD)
p->idx_send = 0;
}
if (p->ioctl_version > 0) {
MppReqV1 mpp_req;
mpp_req.cmd = MPP_CMD_SET_REG;
mpp_req.flag = 0;
mpp_req.size = nregs * sizeof(RK_U32);
mpp_req.offset = 0;
mpp_req.data_ptr = REQ_DATA_PTR(regs);
ret = (RK_S32)ioctl(p->vpu_fd, MPP_IOC_CFG_V1, &mpp_req);
} else {
MppReq req;
req.req = regs;
req.size = nregs * sizeof(RK_U32);
ret = (RK_S32)ioctl(p->vpu_fd, VPU_IOC_SET_REG, &req);
}
if (ret) {
mpp_err_f("ioctl VPU_IOC_SET_REG failed ret %d errno %d %s\n",
ret, errno, strerror(errno));
@@ -258,14 +335,19 @@ MPP_RET mpp_device_wait_reg(MppDevCtx ctx, RK_U32 *regs, RK_U32 nregs)
p = (MppDevCtxImpl *)ctx;
nregs *= sizeof(RK_U32);
if (p->ioctl_version > 0) {
MppReqV1 mpp_req;
mpp_req.cmd = MPP_CMD_GET_REG;
mpp_req.flag = 0;
mpp_req.size = nregs * sizeof(RK_U32);
mpp_req.offset = 0;
mpp_req.data_ptr = REQ_DATA_PTR(regs);
ret = (RK_S32)ioctl(p->vpu_fd, MPP_IOC_CFG_V1, &mpp_req);
} else {
req.req = regs;
req.size = nregs;
req.size = nregs * sizeof(RK_U32);
ret = (RK_S32)ioctl(p->vpu_fd, VPU_IOC_GET_REG, &req);
if (ret) {
mpp_err_f("ioctl VPU_IOC_GET_REG failed ret %d errno %d %s\n",
ret, errno, strerror(errno));
ret = errno;
}
if (mpp_device_debug & MPP_DEVICE_DBG_TIME) {
@@ -280,7 +362,6 @@ MPP_RET mpp_device_wait_reg(MppDevCtx ctx, RK_U32 *regs, RK_U32 nregs)
p->idx_wait = 0;
}
if (mpp_device_debug & MPP_DEVICE_DBG_REG) {
RK_U32 i;
nregs >>= 2;
@@ -293,6 +374,36 @@ MPP_RET mpp_device_wait_reg(MppDevCtx ctx, RK_U32 *regs, RK_U32 nregs)
return ret;
}
#define RKVE_IOC_CUSTOM_BASE 0x1000
#define RKVE_IOC_SET_OSD_PLT (RKVE_IOC_CUSTOM_BASE + 1)
#define RKVE_IOC_SET_L2_REG (RKVE_IOC_CUSTOM_BASE + 2)
#define H265E_SET_PARAMETER (RKVE_IOC_CUSTOM_BASE + 6)
#define H265E_GET_HEADER (RKVE_IOC_CUSTOM_BASE + 7)
#define H265E_RESET (RKVE_IOC_CUSTOM_BASE + 8)
static RK_S32 mpp_change_cmd_id(RK_S32 id)
{
RK_S32 ret_id = 0;
switch (id) {
case RKVE_IOC_SET_OSD_PLT:
ret_id = MPP_CMD_SET_RKVENC_OSD_PLT;
break;
case RKVE_IOC_SET_L2_REG:
ret_id = MPP_CMD_SET_RKVENC_L2_REG;
break;
case H265E_SET_PARAMETER:
ret_id = MPP_CMD_SET_VEPU22_CFG;
break;
case H265E_GET_HEADER:
case H265E_RESET:
default:
mpp_err_f("unknow cmd %d\n", id);
break;
}
return ret_id;
}
MPP_RET mpp_device_send_reg_with_id(MppDevCtx ctx, RK_S32 id, void *param,
RK_S32 size)
{
@@ -306,9 +417,21 @@ MPP_RET mpp_device_send_reg_with_id(MppDevCtx ctx, RK_S32 id, void *param,
p = (MppDevCtxImpl *)ctx;
if (p->ioctl_version > 0) {
MppReqV1 mpp_req;
mpp_req.cmd = (id > RKVE_IOC_CUSTOM_BASE) ? mpp_change_cmd_id(id) : id;
mpp_req.flag = 0;
mpp_req.size = size;
mpp_req.offset = 0;
mpp_req.data_ptr = REQ_DATA_PTR(param);
ret = (RK_S32)ioctl(p->vpu_fd, MPP_IOC_CFG_V1, &mpp_req);
} else {
ret = (RK_S32)ioctl(p->vpu_fd, VPU_IOC_WRITE(id, size), param);
}
if (ret) {
mpp_err_f("ioctl VPU_IOC_WRITE failed ret %d errno %d %s\n",
mpp_err_f("ioctl failed ret %d errno %d %s\n",
ret, errno, strerror(errno));
ret = errno;
}

3
mpp/legacy/vpu_api.cpp
View File

@@ -298,6 +298,9 @@ RK_S32 vpu_open_context(VpuCodecContext **ctx)
} else if (force_mpp_mode) {
/* force mpp mode here */
use_mpp = 1;
} else if (!access("/dev/mpp_service", F_OK)) {
/* if mpp_service exist, force mpp mode */
use_mpp = 1;
} else if (!!access("/dev/rkvdec", F_OK)) {
/* if there is no rkvdec it means the platform must be vpu1 */
if (s && s->videoCoding == OMX_RK_VIDEO_CodingHEVC &&

40
osal/inc/mpp_platform.h
View File

@@ -26,18 +26,40 @@
/*
* Platform video codec hardware feature
*/
typedef enum {
VPU_CLIENT_VDPU1 = 0, /* 0x00000001 */
VPU_CLIENT_VDPU2 = 1, /* 0x00000002 */
VPU_CLIENT_VDPU1_PP = 2, /* 0x00000004 */
VPU_CLIENT_VDPU2_PP = 3, /* 0x00000008 */
VPU_CLIENT_HEVC_DEC = 8, /* 0x00000100 */
VPU_CLIENT_RKVDEC = 9, /* 0x00000200 */
VPU_CLIENT_AVSPLUS_DEC = 12, /* 0x00001000 */
VPU_CLIENT_RKVENC = 16, /* 0x00010000 */
VPU_CLIENT_VEPU1 = 17, /* 0x00020000 */
VPU_CLIENT_VEPU2 = 18, /* 0x00040000 */
VPU_CLIENT_VEPU2_LITE = 19, /* 0x00080000 */
VPU_CLIENT_VEPU22 = 24, /* 0x01000000 */
VPU_CLIENT_BUTT,
} VPU_CLIENT2_TYPE;
/* RK combined codec */
#define HAVE_VPU1 (0x00000001)
#define HAVE_VPU2 (0x00000002)
#define HAVE_VDPU1 (1 << VPU_CLIENT_VDPU1) /* 0x00000001 */
#define HAVE_VDPU2 (1 << VPU_CLIENT_VDPU2) /* 0x00000002 */
#define HAVE_VDPU1_PP (1 << VPU_CLIENT_VDPU1_PP) /* 0x00000004 */
#define HAVE_VDPU2_PP (1 << VPU_CLIENT_VDPU2_PP) /* 0x00000008 */
/* RK standalone decoder */
#define HAVE_HEVC_DEC (0x00000100)
#define HAVE_RKVDEC (0x00000200)
#define HAVE_AVSDEC (0x00001000)
#define HAVE_HEVC_DEC (1 << VPU_CLIENT_HEVC_DEC) /* 0x00000100 */
#define HAVE_RKVDEC (1 << VPU_CLIENT_RKVDEC) /* 0x00000200 */
#define HAVE_AVSDEC (1 << VPU_CLIENT_AVSPLUS_DEC) /* 0x00001000 */
/* RK standalone encoder */
#define HAVE_RKVENC (0x00010000)
#define HAVE_VEPU (0x00020000)
#define HAVE_RKVENC (1 << VPU_CLIENT_RKVENC) /* 0x00010000 */
#define HAVE_VEPU1 (1 << VPU_CLIENT_VEPU1) /* 0x00020000 */
#define HAVE_VEPU2 (1 << VPU_CLIENT_VEPU2) /* 0x00040000 */
#define HAVE_VEPU2_LITE (1 << VPU_CLIENT_VEPU2_LITE) /* 0x00080000 */
/* External encoder */
#define HAVE_H265ENC (0x01000000)
#define HAVE_VEPU22 (1 << VPU_CLIENT_VEPU22) /* 0x01000000 */
/* Platform image process hardware feature */
#define HAVE_IPP (0x00000001)
@@ -61,6 +83,8 @@ extern "C" {
const char *mpp_get_soc_name(void);
RK_U32 mpp_get_vcodec_type(void);
RK_U32 mpp_get_2d_hw_flag(void);
RK_U32 mpp_get_ioctl_version(void);
RK_U32 mpp_refresh_vcodec_type(RK_U32 vcodec_type);
const char *mpp_get_platform_dev_name(MppCtxType type, MppCodingType coding, RK_U32 platform);
const char *mpp_get_vcodec_dev_name(MppCtxType type, MppCodingType coding);

95
osal/mpp_platform.cpp
View File

@@ -55,61 +55,72 @@ typedef struct {
} MppVpuType;
static const MppVpuType mpp_vpu_version[] = {
{ "rk3036", ROCKCHIP_SOC_RK3036, HAVE_VPU1 | HAVE_HEVC_DEC, },
{ "rk3066", ROCKCHIP_SOC_RK3066, HAVE_VPU1, },
{ "rk3188", ROCKCHIP_SOC_RK3188, HAVE_VPU1, },
{ "rk3288", ROCKCHIP_SOC_RK3288, HAVE_VPU1 | HAVE_HEVC_DEC, },
{ "rk3126", ROCKCHIP_SOC_RK312X, HAVE_VPU1 | HAVE_HEVC_DEC, },
{ "rk3128h", ROCKCHIP_SOC_RK3128H, HAVE_VPU2 | HAVE_RKVDEC, },
{ "rk3128", ROCKCHIP_SOC_RK312X, HAVE_VPU1 | HAVE_HEVC_DEC, },
{ "rk3368", ROCKCHIP_SOC_RK3368, HAVE_VPU1 | HAVE_HEVC_DEC, },
{ "rk3399", ROCKCHIP_SOC_RK3399, HAVE_VPU2 | HAVE_RKVDEC, },
{ "rk3036", ROCKCHIP_SOC_RK3036, HAVE_VDPU1 | HAVE_VEPU1 | HAVE_HEVC_DEC, },
{ "rk3066", ROCKCHIP_SOC_RK3066, HAVE_VDPU1 | HAVE_VEPU1, },
{ "rk3188", ROCKCHIP_SOC_RK3188, HAVE_VDPU1 | HAVE_VEPU1, },
{ "rk3288", ROCKCHIP_SOC_RK3288, HAVE_VDPU1 | HAVE_VEPU1 | HAVE_HEVC_DEC, },
{ "rk3126", ROCKCHIP_SOC_RK312X, HAVE_VDPU1 | HAVE_VEPU1 | HAVE_HEVC_DEC, },
{ "rk3128h", ROCKCHIP_SOC_RK3128H, HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC, },
{ "rk3128", ROCKCHIP_SOC_RK312X, HAVE_VDPU1 | HAVE_VEPU1 | HAVE_HEVC_DEC, },
{ "rk3368", ROCKCHIP_SOC_RK3368, HAVE_VDPU1 | HAVE_VEPU1 | HAVE_HEVC_DEC, },
{ "rk3399", ROCKCHIP_SOC_RK3399, HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC, },
/* 3228h first for string matching */
{ "rk3228h", ROCKCHIP_SOC_RK3228H, HAVE_VPU2 | HAVE_RKVDEC | HAVE_AVSDEC | HAVE_H265ENC, },
{ "rk3328", ROCKCHIP_SOC_RK3328, HAVE_VPU2 | HAVE_RKVDEC | HAVE_H265ENC, },
{ "rk3228", ROCKCHIP_SOC_RK3228, HAVE_VPU2 | HAVE_RKVDEC, },
{ "rk3229", ROCKCHIP_SOC_RK3229, HAVE_VPU2 | HAVE_RKVDEC, },
{ "rv1108", ROCKCHIP_SOC_RV1108, HAVE_VPU2 | HAVE_RKVDEC | HAVE_RKVENC, },
{ "rk3326", ROCKCHIP_SOC_RK3326, HAVE_VPU2 | HAVE_HEVC_DEC, },
{ "px30", ROCKCHIP_SOC_RK3326, HAVE_VPU2 | HAVE_HEVC_DEC, },
{ "rk1808", ROCKCHIP_SOC_RK1808, HAVE_VPU2, },
{ "rk3228h", ROCKCHIP_SOC_RK3228H, HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_AVSDEC | HAVE_VEPU22, },
{ "rk3328", ROCKCHIP_SOC_RK3328, HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_VEPU22, },
{ "rk3228", ROCKCHIP_SOC_RK3228, HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC, },
{ "rk3229", ROCKCHIP_SOC_RK3229, HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC, },
{ "rv1108", ROCKCHIP_SOC_RV1108, HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC, },
{ "rk3326", ROCKCHIP_SOC_RK3326, HAVE_VDPU2 | HAVE_VEPU2 | HAVE_HEVC_DEC, },
{ "px30", ROCKCHIP_SOC_RK3326, HAVE_VDPU2 | HAVE_VEPU2 | HAVE_HEVC_DEC, },
{ "rk1808", ROCKCHIP_SOC_RK1808, HAVE_VDPU2 | HAVE_VEPU2, },
};
/* For vpu1 / vpu2 */
static const char *mpp_vpu_dev[] = {
"/dev/vpu_service",
"/dev/vpu-service",
"/dev/mpp_service",
};
/* For hevc 4K decoder */
static const char *mpp_hevc_dev[] = {
"/dev/hevc_service",
"/dev/hevc-service",
"/dev/mpp_service",
};
/* For H.264/H.265/VP9 4K decoder */
static const char *mpp_rkvdec_dev[] = {
"/dev/rkvdec",
"/dev/mpp_service",
};
/* For H.264 4K encoder */
static const char *mpp_rkvenc_dev[] = {
"/dev/rkvenc",
"/dev/mpp_service",
};
/* For avs+ decoder */
static const char *mpp_avsd_dev[] = {
"/dev/avsd",
"/dev/mpp_service",
};
/* For H.264 / jpeg encoder */
static const char *mpp_vepu_dev[] = {
"/dev/vepu",
"/dev/mpp_service",
};
/* For H.265 encoder */
static const char *mpp_h265e_dev[] = {
"/dev/h265e",
"/dev/mpp_service",
};
static const char *mpp_service_dev[] = {
"/dev/mpp_service",
};
#define mpp_find_device(dev) _mpp_find_device(dev, MPP_ARRAY_ELEMS(dev))
@@ -148,6 +159,7 @@ public:
const char *get_soc_name() { return soc_name; };
RockchipSocType get_soc_type() { return soc_type; };
RK_U32 get_vcodec_type() { return vcodec_type; };
void refresh_vcodec_type(RK_U32 val) { vcodec_type = val; };
RK_U32 get_vcodec_capability() { return vcodec_capability; };
};
@@ -162,7 +174,7 @@ MppPlatformService::MppPlatformService()
mpp_env_get_u32("mpp_debug", &mpp_debug, 0);
/* set vpu1 defalut for old chip without dts */
vcodec_type = HAVE_VPU1;
vcodec_type = HAVE_VDPU1 | HAVE_VEPU1;
fd = open("/proc/device-tree/compatible", O_RDONLY);
if (fd < 0) {
mpp_err("open /proc/device-tree/compatible error.\n");
@@ -204,6 +216,12 @@ MppPlatformService::MppPlatformService()
close(fd);
}
/* if /dev/mpp_service not double check */
if (mpp_find_device(mpp_service_dev)) {
mpp_dbg(MPP_DBG_PLATFORM, "/dev/mpp_service not double check device\n");
goto __return;
}
/*
* NOTE: The following check is for kernel driver device double check
* Some kernel does not have all device dts. So we need to remove the
@@ -237,19 +255,19 @@ MppPlatformService::MppPlatformService()
/* for rk3228h / rk3328 H.264/jpeg encoder */
if (!mpp_find_device(mpp_vepu_dev))
vcodec_type &= ~HAVE_VEPU;
vcodec_type &= ~HAVE_VEPU2_LITE;
else
vcodec_type |= HAVE_VEPU;
vcodec_type |= HAVE_VEPU2_LITE;
/* for rk3228h / rk3328 H.265 encoder */
if (!mpp_find_device(mpp_h265e_dev))
vcodec_type &= ~HAVE_H265ENC;
vcodec_type &= ~HAVE_VEPU22;
else
vcodec_type |= HAVE_H265ENC;
vcodec_type |= HAVE_VEPU22;
/* for all chip vpu decoder */
if (!mpp_find_device(mpp_vpu_dev))
vcodec_type &= ~(HAVE_VPU1 | HAVE_VPU2);
vcodec_type &= ~(HAVE_VDPU1 | HAVE_VEPU1 | HAVE_VDPU2 | HAVE_VEPU2);
__return:
mpp_dbg(MPP_DBG_PLATFORM, "vcodec type %08x\n", vcodec_type);
}
@@ -273,10 +291,9 @@ RK_U32 mpp_get_vcodec_type(void)
{
static RK_U32 vcodec_type = 0;
if (vcodec_type)
return vcodec_type;
if (!vcodec_type)
vcodec_type = MppPlatformService::get_instance()->get_vcodec_type();
return vcodec_type;
}
@@ -293,11 +310,29 @@ RK_U32 mpp_get_2d_hw_flag(void)
return flag;
}
RK_U32 mpp_get_ioctl_version(void)
{
RK_U32 flag = 0;
flag = mpp_find_device(mpp_service_dev) ? 1 : 0;
return flag;
}
RK_U32 mpp_refresh_vcodec_type(RK_U32 vcodec_type)
{
MppPlatformService::get_instance()->refresh_vcodec_type(vcodec_type);
return 0;
}
const char *mpp_get_platform_dev_name(MppCtxType type, MppCodingType coding, RK_U32 platform)
{
const char *dev = NULL;
if ((platform & HAVE_RKVDEC) && (type == MPP_CTX_DEC) &&
if ((dev = mpp_find_device(mpp_service_dev)) != NULL) {
mpp_log("got the %s\n", dev);
} else if ((platform & HAVE_RKVDEC) && (type == MPP_CTX_DEC) &&
(coding == MPP_VIDEO_CodingAVC ||
coding == MPP_VIDEO_CodingHEVC ||
coding == MPP_VIDEO_CodingVP9)) {
@@ -311,10 +346,10 @@ const char *mpp_get_platform_dev_name(MppCtxType type, MppCodingType coding, RK_
} else if ((platform & HAVE_RKVENC) && (type == MPP_CTX_ENC) &&
(coding == MPP_VIDEO_CodingAVC)) {
dev = mpp_find_device(mpp_rkvenc_dev);
} else if ((platform & HAVE_H265ENC) && (type == MPP_CTX_ENC) &&
} else if ((platform & HAVE_VEPU22) && (type == MPP_CTX_ENC) &&
(coding == MPP_VIDEO_CodingHEVC)) {
dev = mpp_find_device(mpp_h265e_dev);
} else if ((platform & HAVE_VEPU) && (type == MPP_CTX_ENC) &&
} else if ((platform & (HAVE_VEPU2_LITE)) && (type == MPP_CTX_ENC) &&
((coding == MPP_VIDEO_CodingAVC ||
coding == MPP_VIDEO_CodingMJPEG))) {
dev = mpp_find_device(mpp_vepu_dev);

9
osal/mpp_runtime.cpp
View File

@@ -94,6 +94,15 @@ MppRuntimeService::MppRuntimeService()
mpp_log("found drm allocator\n");
}
if ((!access("/dev/mpp_service", F_OK | R_OK | W_OK)) &&
allocator_valid[MPP_BUFFER_TYPE_ION] &&
allocator_valid[MPP_BUFFER_TYPE_DRM]) {
allocator_valid[MPP_BUFFER_TYPE_ION] = 0;
mpp_log("use drm allocator for mpp_service\n");
return;
}
// If both ion and drm is enabled detect allocator in dts to choose one
// TODO: When unify dma fd kernel is completed this part will be removed.
if (allocator_valid[MPP_BUFFER_TYPE_ION] &&

8
osal/test/mpp_platform_test.c
View File

@@ -28,10 +28,10 @@ int main()
mpp_log("\n");
mpp_log("chip vcodec type %08x\n", vcodec_type);
if (vcodec_type & HAVE_VPU1)
if (vcodec_type & (HAVE_VDPU1 | HAVE_VEPU1))
mpp_log("found vpu1 codec\n");
if (vcodec_type & HAVE_VPU2)
if (vcodec_type & (HAVE_VDPU2 | HAVE_VEPU2))
mpp_log("found vpu2 codec\n");
if (vcodec_type & HAVE_HEVC_DEC)
@@ -46,10 +46,10 @@ int main()
if (vcodec_type & HAVE_RKVENC)
mpp_log("found rkvenc encoder\n");
if (vcodec_type & HAVE_VEPU)
if (vcodec_type & HAVE_VEPU2)
mpp_log("found vpu2 encoder\n");
if (vcodec_type & HAVE_H265ENC)
if (vcodec_type & HAVE_VEPU22)
mpp_log("found h265 stand-alone encoder\n");
mpp_log("\n");