From 7939be124696e6cc554674fea453bdcb2eafdb2a Mon Sep 17 00:00:00 2001 From: Yandong Lin Date: Thu, 9 Jan 2025 11:36:39 +0800 Subject: [PATCH] refactor[mpp_enc_cfg]: Adjust cu_qp_delta_depth sync from mpp_interface Change-Id: I2dfabef3acf01566df289396678a433ac84f3a15 Signed-off-by: Yandong Lin --- inc/rk_venc_cmd.h | 3 +-- mpp/base/mpp_enc_cfg.cpp | 2 +- mpp/codec/enc/h265/h265e_api.c | 6 +++++- mpp/codec/enc/h265/h265e_ps.c | 3 +-- mpp/codec/mpp_enc_impl.cpp | 3 --- test/mpi_enc_test.c | 5 +++-- 6 files changed, 11 insertions(+), 11 deletions(-) diff --git a/inc/rk_venc_cmd.h b/inc/rk_venc_cmd.h index 799f96fe..b381f0e6 100644 --- a/inc/rk_venc_cmd.h +++ b/inc/rk_venc_cmd.h @@ -239,7 +239,6 @@ typedef enum MppEncRcCfgChange_e { MPP_ENC_RC_CFG_CHANGE_REFRESH = (1 << 27), MPP_ENC_RC_CFG_CHANGE_GOP_REF_CFG = (1 << 28), MPP_ENC_RC_CFG_CHANGE_FQP = (1 << 29), - MPP_ENC_RC_CFG_CHANGE_QPDD = (1 << 30), MPP_ENC_RC_CFG_CHANGE_ALL = (0xFFFFFFFF), } MppEncRcCfgChange; @@ -417,7 +416,6 @@ typedef struct MppEncRcCfg_t { RK_S32 fqp_min_p; RK_S32 fqp_max_i; RK_S32 fqp_max_p; - RK_S32 cu_qp_delta_depth; RK_S32 mt_st_swth_frm_qp; RK_S32 hier_qp_en; @@ -1077,6 +1075,7 @@ typedef struct MppEncH265TransCfg_t { RK_U32 defalut_ScalingList_enable; /* default: 0 */ RK_S32 cb_qp_offset; RK_S32 cr_qp_offset; + RK_S32 diff_cu_qp_delta_depth; } MppEncH265TransCfg; typedef struct MppEncH265MergeCfg_t { diff --git a/mpp/base/mpp_enc_cfg.cpp b/mpp/base/mpp_enc_cfg.cpp index 9e02810f..99d8f91c 100644 --- a/mpp/base/mpp_enc_cfg.cpp +++ b/mpp/base/mpp_enc_cfg.cpp @@ -139,7 +139,6 @@ public: ENTRY(rc, fqp_min_p, S32, MPP_ENC_RC_CFG_CHANGE_FQP, rc, fqp_min_p) \ ENTRY(rc, fqp_max_i, S32, MPP_ENC_RC_CFG_CHANGE_FQP, rc, fqp_max_i) \ ENTRY(rc, fqp_max_p, S32, MPP_ENC_RC_CFG_CHANGE_FQP, rc, fqp_max_p) \ - ENTRY(rc, cu_qp_delta_depth, S32, MPP_ENC_RC_CFG_CHANGE_QPDD, rc, cu_qp_delta_depth) \ ENTRY(rc, mt_st_swth_frm_qp, S32, MPP_ENC_RC_CFG_CHANGE_FQP, rc, mt_st_swth_frm_qp) \ /* prep config */ \ ENTRY(prep, width, S32, MPP_ENC_PREP_CFG_CHANGE_INPUT, prep, width) \ @@ -202,6 +201,7 @@ public: ENTRY(h265, scaling_list, U32, MPP_ENC_H265_CFG_TRANS_CHANGE, codec.h265, trans_cfg.defalut_ScalingList_enable) \ ENTRY(h265, cb_qp_offset, S32, MPP_ENC_H265_CFG_TRANS_CHANGE, codec.h265, trans_cfg.cb_qp_offset) \ ENTRY(h265, cr_qp_offset, S32, MPP_ENC_H265_CFG_TRANS_CHANGE, codec.h265, trans_cfg.cr_qp_offset) \ + ENTRY(h265, diff_cu_qp_delta_depth, S32, MPP_ENC_H265_CFG_TRANS_CHANGE, codec.h265, trans_cfg.diff_cu_qp_delta_depth) \ ENTRY(h265, dblk_disable, U32, MPP_ENC_H265_CFG_DBLK_CHANGE, codec.h265, dblk_cfg.slice_deblocking_filter_disabled_flag) \ ENTRY(h265, dblk_alpha, S32, MPP_ENC_H265_CFG_DBLK_CHANGE, codec.h265, dblk_cfg.slice_beta_offset_div2) \ ENTRY(h265, dblk_beta, S32, MPP_ENC_H265_CFG_DBLK_CHANGE, codec.h265, dblk_cfg.slice_tc_offset_div2) \ diff --git a/mpp/codec/enc/h265/h265e_api.c b/mpp/codec/enc/h265/h265e_api.c index 8f7f272a..91d51cdf 100644 --- a/mpp/codec/enc/h265/h265e_api.c +++ b/mpp/codec/enc/h265/h265e_api.c @@ -109,6 +109,7 @@ static MPP_RET h265e_init(void *ctx, EncImplCfg *ctrlCfg) h265->merge_cfg.max_mrg_cnd = 2; h265->merge_cfg.merge_left_flag = 1; h265->merge_cfg.merge_up_flag = 1; + h265->trans_cfg.diff_cu_qp_delta_depth = 0; p->cfg->tune.scene_mode = MPP_ENC_SCENE_MODE_DEFAULT; p->cfg->tune.lambda_idx_i = 2; p->cfg->tune.lambda_idx_p = 4; @@ -179,7 +180,6 @@ static MPP_RET h265e_init(void *ctx, EncImplCfg *ctrlCfg) rc_cfg->fqp_min_p = INT_MAX; rc_cfg->fqp_max_i = INT_MAX; rc_cfg->fqp_max_p = INT_MAX; - rc_cfg->cu_qp_delta_depth = 0; INIT_LIST_HEAD(&p->rc_list); h265e_dbg_func("leave ctx %p\n", ctx); @@ -574,6 +574,10 @@ static MPP_RET h265e_proc_h265_cfg(MppEncH265Cfg *dst, MppEncH265Cfg *src) src->trans_cfg.cb_qp_offset, src->trans_cfg.cr_qp_offset); src->trans_cfg.cr_qp_offset = src->trans_cfg.cb_qp_offset; } + if (src->trans_cfg.diff_cu_qp_delta_depth > 2 || src->trans_cfg.diff_cu_qp_delta_depth < 0) { + mpp_log("diff_cu_qp_delta_depth must be in [0, 2]\n"); + src->trans_cfg.diff_cu_qp_delta_depth = 0; + } memcpy(&dst->trans_cfg, &src->trans_cfg, sizeof(src->trans_cfg)); } diff --git a/mpp/codec/enc/h265/h265e_ps.c b/mpp/codec/enc/h265/h265e_ps.c index aaec0073..4ae942fc 100644 --- a/mpp/codec/enc/h265/h265e_ps.c +++ b/mpp/codec/enc/h265/h265e_ps.c @@ -400,14 +400,13 @@ MPP_RET h265e_set_sps(H265eCtx *ctx, H265eSps *sps, H265eVps *vps) MPP_RET h265e_set_pps(H265eCtx *ctx, H265ePps *pps, H265eSps *sps) { MppEncH265Cfg *codec = &ctx->cfg->codec.h265; - MppEncRcCfg *rc = &ctx->cfg->rc; pps->m_bConstrainedIntraPred = codec->const_intra_pred; pps->m_PPSId = 0; pps->m_SPSId = 0; pps->m_picInitQPMinus26 = 0; pps->m_useDQP = 1; - pps->m_maxCuDQPDepth = rc->cu_qp_delta_depth; + pps->m_maxCuDQPDepth = codec->trans_cfg.diff_cu_qp_delta_depth; pps->m_minCuDQPSize = (sps->m_maxCUSize >> pps->m_maxCuDQPDepth); pps->m_sps = sps; diff --git a/mpp/codec/mpp_enc_impl.cpp b/mpp/codec/mpp_enc_impl.cpp index a2eb735c..f9543cd3 100644 --- a/mpp/codec/mpp_enc_impl.cpp +++ b/mpp/codec/mpp_enc_impl.cpp @@ -696,9 +696,6 @@ MPP_RET mpp_enc_proc_rc_cfg(MppCodingType coding, MppEncRcCfg *dst, MppEncRcCfg dst->refresh_num = src->refresh_num; } - if (change & MPP_ENC_RC_CFG_CHANGE_QPDD) - dst->cu_qp_delta_depth = src->cu_qp_delta_depth; - // parameter checking if (dst->rc_mode >= MPP_ENC_RC_MODE_BUTT) { mpp_err("invalid rc mode %d should be RC_MODE_VBR or RC_MODE_CBR\n", diff --git a/test/mpi_enc_test.c b/test/mpi_enc_test.c index e1196616..2d4228b8 100644 --- a/test/mpi_enc_test.c +++ b/test/mpi_enc_test.c @@ -385,7 +385,6 @@ MPP_RET test_mpp_enc_cfg_setup(MpiEncMultiCtxInfo *info) } mpp_enc_cfg_set_s32(cfg, "rc:max_reenc_times", 0); - mpp_enc_cfg_set_s32(cfg, "rc:cu_qp_delta_depth", p->cu_qp_delta_depth); mpp_enc_cfg_set_s32(cfg, "tune:anti_flicker_str", p->anti_flicker_str); mpp_enc_cfg_set_s32(cfg, "tune:atr_str_i", p->atr_str_i); mpp_enc_cfg_set_s32(cfg, "tune:atr_str_p", p->atr_str_p); @@ -541,7 +540,9 @@ MPP_RET test_mpp_enc_cfg_setup(MpiEncMultiCtxInfo *info) if (constraint_set & 0x3f0000) mpp_enc_cfg_set_s32(cfg, "h264:constraint_set", constraint_set); } break; - case MPP_VIDEO_CodingHEVC : + case MPP_VIDEO_CodingHEVC : { + mpp_enc_cfg_set_s32(cfg, "h265:diff_cu_qp_delta_depth", p->cu_qp_delta_depth); + } break; case MPP_VIDEO_CodingMJPEG : case MPP_VIDEO_CodingVP8 : { } break;