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[h265e]: rename fivm_max_mrg_cnd to max_mrg_cnd

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Change-Id: I7e1b4fb37a8af9812c393e095006f4af9f625bea
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>
This commit is contained in:
sayon.chen
2020-01-03 14:43:24 +08:00
committed by Herman Chen
parent 459eace205
commit 72606f13fa
7 changed files with 7 additions and 9 deletions
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4
inc/rk_venc_cmd.h
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@@ -817,8 +817,6 @@ typedef struct MppEncH265CuCfg_t {
RK_U32 pcm_enabled_flag; /*default: 0, enable ipcm*/ RK_U32 pcm_enabled_flag; /*default: 0, enable ipcm*/
RK_U32 pcm_loop_filter_disabled_flag; RK_U32 pcm_loop_filter_disabled_flag;
// inter pred
RK_U32 max_num_merge_cand;
} MppEncH265CuCfg; } MppEncH265CuCfg;
typedef struct MppEncH265RefCfg_t { typedef struct MppEncH265RefCfg_t {
@@ -846,7 +844,7 @@ typedef struct MppEncH265TransCfg_t {
} MppEncH265TransCfg; } MppEncH265TransCfg;
typedef struct MppEncH265MergeCfg_t { typedef struct MppEncH265MergeCfg_t {
RK_U32 fivm_max_mrg_cnd; RK_U32 max_mrg_cnd;
RK_U32 merge_up_flag; RK_U32 merge_up_flag;
RK_U32 merge_left_flag; RK_U32 merge_left_flag;
} MppEncH265MergesCfg; } MppEncH265MergesCfg;

2
mpp/codec/enc/h265/h265e_api_v2.c
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@@ -121,7 +121,7 @@ static MPP_RET h265e_init(void *ctx, EncImplCfg *ctrlCfg)
h265->sao_cfg.slice_sao_luma_flag = 0; h265->sao_cfg.slice_sao_luma_flag = 0;
h265->dblk_cfg.slice_deblocking_filter_disabled_flag = 0; h265->dblk_cfg.slice_deblocking_filter_disabled_flag = 0;
h265->cu_cfg.strong_intra_smoothing_enabled_flag = 1; h265->cu_cfg.strong_intra_smoothing_enabled_flag = 1;
h265->merge_cfg.fivm_max_mrg_cnd = 2; h265->merge_cfg.max_mrg_cnd = 2;
h265->merge_cfg.merge_left_flag = 1; h265->merge_cfg.merge_left_flag = 1;
h265->merge_cfg.merge_up_flag = 1; h265->merge_cfg.merge_up_flag = 1;

2
mpp/codec/enc/h265/h265e_slice.c
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@@ -260,7 +260,7 @@ void h265e_slice_init(void *ctx, H265eSlice *slice)
} }
slice->m_saoEnabledFlag = codec->sao_cfg.slice_sao_luma_flag; slice->m_saoEnabledFlag = codec->sao_cfg.slice_sao_luma_flag;
slice->m_saoEnabledFlagChroma = codec->sao_cfg.slice_sao_chroma_flag; slice->m_saoEnabledFlagChroma = codec->sao_cfg.slice_sao_chroma_flag;
slice->m_maxNumMergeCand = codec->merge_cfg.fivm_max_mrg_cnd; slice->m_maxNumMergeCand = codec->merge_cfg.max_mrg_cnd;
slice->m_cabacInitFlag = codec->entropy_cfg.cabac_init_flag; slice->m_cabacInitFlag = codec->entropy_cfg.cabac_init_flag;
slice->m_picOutputFlag = 1; slice->m_picOutputFlag = 1;
slice->m_ppsId = pps->m_PPSId; slice->m_ppsId = pps->m_PPSId;

2
mpp/codec/enc/h265/h265e_syntax.c
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@@ -161,7 +161,7 @@ static void fill_slice_parameters( const H265eCtx *h,
sp->dblk_fltr_ovrd_flg = slice->m_deblockingFilterOverrideFlag; sp->dblk_fltr_ovrd_flg = slice->m_deblockingFilterOverrideFlag;
sp->sli_cb_qp_ofst = slice->m_sliceQpDeltaCb; sp->sli_cb_qp_ofst = slice->m_sliceQpDeltaCb;
sp->sli_qp = slice->m_sliceQp; sp->sli_qp = slice->m_sliceQp;
sp->fivm_max_mrg_cnd = slice->m_maxNumMergeCand; sp->max_mrg_cnd = slice->m_maxNumMergeCand;
sp->col_ref_idx = 0; sp->col_ref_idx = 0;
sp->col_frm_l0_flg = slice->m_colFromL0Flag; sp->col_frm_l0_flg = slice->m_colFromL0Flag;

2
mpp/common/h265e_syntax_new.h
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@@ -158,7 +158,7 @@ typedef struct H265eSlicParams_t {
RK_S8 sli_beta_ofst_div2; RK_S8 sli_beta_ofst_div2;
RK_S8 sli_cb_qp_ofst; RK_S8 sli_cb_qp_ofst;
RK_U8 sli_qp; RK_U8 sli_qp;
RK_U8 fivm_max_mrg_cnd; RK_U8 max_mrg_cnd;
RK_U8 lst_entry_l0; RK_U8 lst_entry_l0;
RK_U8 num_refidx_l1_act; RK_U8 num_refidx_l1_act;
RK_U8 num_refidx_l0_act; RK_U8 num_refidx_l0_act;

2
mpp/hal/rkenc/h265e/hal_h265e_rkv.c
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@@ -715,7 +715,7 @@ static void h265e_rkv_set_slice_regs(H265eSyntax_new *syn, H265eRkvRegSet *regs)
regs->synt_sli1.sli_dblk_fltr_dis = syn->sp.sli_dblk_fltr_dis; regs->synt_sli1.sli_dblk_fltr_dis = syn->sp.sli_dblk_fltr_dis;
regs->synt_sli1.dblk_fltr_ovrd_flg = syn->sp.dblk_fltr_ovrd_flg; regs->synt_sli1.dblk_fltr_ovrd_flg = syn->sp.dblk_fltr_ovrd_flg;
regs->synt_sli1.sli_cb_qp_ofst = syn->sp.sli_cb_qp_ofst; regs->synt_sli1.sli_cb_qp_ofst = syn->sp.sli_cb_qp_ofst;
regs->synt_sli1.fivm_max_mrg_cnd = syn->sp.fivm_max_mrg_cnd; regs->synt_sli1.max_mrg_cnd = syn->sp.max_mrg_cnd;
regs->synt_sli1.col_ref_idx = syn->sp.col_ref_idx; regs->synt_sli1.col_ref_idx = syn->sp.col_ref_idx;
regs->synt_sli1.col_frm_l0_flg = syn->sp.col_frm_l0_flg; regs->synt_sli1.col_frm_l0_flg = syn->sp.col_frm_l0_flg;

2
mpp/hal/rkenc/h265e/hal_h265e_rkv.h
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@@ -716,7 +716,7 @@ typedef struct H265eRkvRegSet_t {
RK_U32 dblk_fltr_ovrd_flg : 1; RK_U32 dblk_fltr_ovrd_flg : 1;
RK_S32 sli_cb_qp_ofst : 5; RK_S32 sli_cb_qp_ofst : 5;
RK_U32 sli_qp : 6; RK_U32 sli_qp : 6;
RK_U32 fivm_max_mrg_cnd : 3; RK_U32 max_mrg_cnd : 3;
RK_U32 col_ref_idx : 1; RK_U32 col_ref_idx : 1;
RK_U32 col_frm_l0_flg : 1; RK_U32 col_frm_l0_flg : 1;
RK_U32 lst_entry_l0 : 4; RK_U32 lst_entry_l0 : 4;