From 71ff5475cb858e3629fa89c43eaefb687784b17c Mon Sep 17 00:00:00 2001 From: "sayon.chen" Date: Fri, 27 Mar 2020 09:47:39 +0800 Subject: [PATCH] [hevc_v345_dec]: Support hevc_v345 hw_rps 1. must define HW_RPS for support 2. defalut open hw_rps Change-Id: Ic699fa2fba24217a082ee4ef62538e3f92d11e1c Signed-off-by: sayon.chen --- mpp/codec/dec/h265/h265d_parser2_syntax.c | 22 ++++++++ mpp/common/h265d_syntax.h | 19 ++++++- mpp/hal/rkdec/h265d/hal_h265d_reg.c | 63 ++++++++++++++++++++++- mpp/hal/rkdec/h265d/hal_h265d_reg.h | 6 ++- 4 files changed, 107 insertions(+), 3 deletions(-) diff --git a/mpp/codec/dec/h265/h265d_parser2_syntax.c b/mpp/codec/dec/h265/h265d_parser2_syntax.c index 8b990a40..bc0678f4 100644 --- a/mpp/codec/dec/h265/h265d_parser2_syntax.c +++ b/mpp/codec/dec/h265/h265d_parser2_syntax.c @@ -160,6 +160,28 @@ static void fill_picture_parameters(const HEVCContext *h, pp->log2_parallel_merge_level_minus2 = pps->log2_parallel_merge_level - 2; pp->CurrPicOrderCntVal = h->poc; + for (i = 0; i < 32; i++) { + pp->sps_lt_rps[i].lt_ref_pic_poc_lsb = sps->lt_ref_pic_poc_lsb_sps[i]; + pp->sps_lt_rps[i].used_by_curr_pic_lt_flag = sps->used_by_curr_pic_lt_sps_flag[i]; + } + + for (i = 0; i < 64; i++) { + if (i < sps->nb_st_rps) { + pp->sps_st_rps[i].num_negative_pics = sps->st_rps[i].num_negative_pics; + pp->sps_st_rps[i].num_positive_pics = sps->st_rps[i].num_delta_pocs - sps->st_rps[i].num_negative_pics; + + for (j = 0; j < pp->sps_st_rps[i].num_negative_pics; j++) { + pp->sps_st_rps[i].delta_poc_s0[j] = sps->st_rps[i].delta_poc[j]; + pp->sps_st_rps[i].s0_used_flag[j] = sps->st_rps[i].used[j]; + } + + for ( j = 0; j < (RK_U32)sps->st_rps[i].num_delta_pocs; j++) { + pp->sps_st_rps[i].delta_poc_s1[j] = sps->st_rps[i].delta_poc[j]; + pp->sps_st_rps[i].s1_used_flag[j] = sps->st_rps[i].used[j]; + } + } + } + nb_rps_used = 0; for (i = 0; i < NB_RPS_TYPE; i++) { for (j = 0; j < (RK_U32)h->rps[i].nb_refs; j++) { diff --git a/mpp/common/h265d_syntax.h b/mpp/common/h265d_syntax.h index 52b1d080..15a5c252 100644 --- a/mpp/common/h265d_syntax.h +++ b/mpp/common/h265d_syntax.h @@ -54,6 +54,19 @@ typedef struct _DXVA_PicEntry_HEVC { }; } DXVA_PicEntry_HEVC, *LPDXVA_PicEntry_HEVC; +typedef struct _Short_SPS_RPS_HEVC { + UCHAR num_negative_pics; + UCHAR num_positive_pics; + SHORT delta_poc_s0[16]; + UCHAR s0_used_flag[16]; + SHORT delta_poc_s1[16]; + UCHAR s1_used_flag[16]; +} Short_SPS_RPS_HEVC; + +typedef struct _LT_SPS_RPS_HEVC { + USHORT lt_ref_pic_poc_lsb; + UCHAR used_by_curr_pic_lt_flag; +} LT_SPS_RPS_HEVC; /* HEVC Picture Parameter structure */ typedef struct _DXVA_PicParams_HEVC { USHORT PicWidthInMinCbsY; @@ -160,7 +173,11 @@ typedef struct _DXVA_PicParams_HEVC { UINT32 vps_id; UINT32 pps_id; UINT32 sps_id; - UCHAR scaling_list_data_present_flag; + + Short_SPS_RPS_HEVC sps_st_rps[64]; + LT_SPS_RPS_HEVC sps_lt_rps[32]; + + UCHAR scaling_list_data_present_flag; } DXVA_PicParams_HEVC, *LPDXVA_PicParams_HEVC; /* HEVC Quantizatiuon Matrix structure */ diff --git a/mpp/hal/rkdec/h265d/hal_h265d_reg.c b/mpp/hal/rkdec/h265d/hal_h265d_reg.c index 05de182a..0917f4bf 100644 --- a/mpp/hal/rkdec/h265d/hal_h265d_reg.c +++ b/mpp/hal/rkdec/h265d/hal_h265d_reg.c @@ -46,7 +46,7 @@ #ifdef dump static FILE *fp = NULL; #endif - +#define HW_RPS #define MAX_GEN_REG 3 RK_U32 h265h_debug = 0; typedef struct h265d_reg_buf { @@ -745,6 +745,61 @@ static int hal_h265d_slice_rpl(void *dxva, SliceHeader_t *sh, RefPicListTab_t *r return 0; } +#ifdef HW_RPS +static RK_S32 hal_h265d_slice_hw_rps(void *dxva, void *rps_buf) +{ + BitputCtx_t bp; + RK_S32 fifo_len = 400; + RK_S32 i = 0, j = 0; + h265d_dxva2_picture_context_t *dxva_cxt = (h265d_dxva2_picture_context_t*)dxva; + mpp_set_bitput_ctx(&bp, (RK_U64*)rps_buf, fifo_len); + for (i = 0; i < 32; i ++) { + mpp_put_bits(&bp, dxva_cxt->pp.sps_lt_rps[i].lt_ref_pic_poc_lsb, 16); + mpp_put_bits(&bp, dxva_cxt->pp.sps_lt_rps[i].used_by_curr_pic_lt_flag, 1); + mpp_put_bits(&bp, 0, 15); + } + + for (i = 0; i < 64; i++) { + if (i < dxva_cxt->pp.num_short_term_ref_pic_sets) { + + mpp_put_bits(&bp, dxva_cxt->pp.sps_st_rps[i].num_negative_pics, 4); + mpp_put_bits(&bp, dxva_cxt->pp.sps_st_rps[i].num_positive_pics, 4); + for ( j = 0; j < dxva_cxt->pp.sps_st_rps[i].num_negative_pics; j++) { + + mpp_put_bits(&bp, dxva_cxt->pp.sps_st_rps[i].delta_poc_s0[j], 16); + mpp_put_bits(&bp, dxva_cxt->pp.sps_st_rps[i].s0_used_flag[j], 1); + } + + for (j = 0; j < dxva_cxt->pp.sps_st_rps[i].num_positive_pics; j++) { + mpp_put_bits(&bp, dxva_cxt->pp.sps_st_rps[i].delta_poc_s1[j], 16); + mpp_put_bits(&bp, dxva_cxt->pp.sps_st_rps[i].s1_used_flag[j], 1); + + } + + for ( j = dxva_cxt->pp.sps_st_rps[i].num_negative_pics + dxva_cxt->pp.sps_st_rps[i].num_positive_pics; j < 15; j++) { + mpp_put_bits(&bp, 0, 16); + mpp_put_bits(&bp, 0, 1); + } + + } else { + mpp_put_bits(&bp, 0, 4); + mpp_put_bits(&bp, 0, 4); + for ( j = 0; j < 15; j++) { + mpp_put_bits(&bp, 0, 16); + mpp_put_bits(&bp, 0, 1); + } + } + mpp_put_align(&bp, 64, 0); + mpp_put_bits(&bp, 0, 64); + } + RK_U32 *tmp = (RK_U32 *)rps_buf; + for (i = 0; i < 400 * 8 / 4; i++) { + h265h_dbg(H265H_DBG_RPS, "rps[%3d] = 0x%08x\n", i, tmp[i]); + } + return 0; +} +#endif + static RK_S32 hal_h265d_slice_output_rps(void *dxva, void *rps_buf) { @@ -1675,8 +1730,14 @@ MPP_RET hal_h265d_gen_regs(void *hal, HalTaskInfo *syn) dxva_cxt->bitstream = mpp_buffer_get_ptr(streambuf); } if (reg_cxt->is_v345) { +#ifdef HW_RPS + hw_regs->sw_sysctrl.sw_wait_reset_en = 1; + hw_regs->v345_reg_ends.reg064_mvc0.refp_layer_same_with_cur = 0xffff; + hal_h265d_slice_hw_rps(syn->dec.syntax.data, rps_ptr); +#else hw_regs->sw_sysctrl.sw_h26x_rps_mode = 1; hal_h265d_slice_output_rps(syn->dec.syntax.data, rps_ptr); +#endif } else { hal_h265d_slice_output_rps(syn->dec.syntax.data, rps_ptr); } diff --git a/mpp/hal/rkdec/h265d/hal_h265d_reg.h b/mpp/hal/rkdec/h265d/hal_h265d_reg.h index 1e81d23b..560b44ab 100644 --- a/mpp/hal/rkdec/h265d/hal_h265d_reg.h +++ b/mpp/hal/rkdec/h265d/hal_h265d_reg.h @@ -58,7 +58,11 @@ typedef struct RKV_HEVC_REG_END { } rkv_reg_end; typedef struct V345_HEVC_REG_END { - RK_U32 reserve[56]; + struct hevc_mvc0 { + RK_U32 refp_layer_same_with_cur : 16 ; + RK_U32 reserve : 16 ; + } reg064_mvc0; + RK_U32 reserve[55]; } v345_reg_end; typedef struct {