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[hal_h265e_vepu580]: Fix tile osd offset error

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Use new multi register offset config function to setup all offset for
vepu580 and vepu541.

Change-Id: I78e77ddd818b7875c028b660aa06a16b527a8409
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
This commit is contained in:
Herman Chen
2022-02-09 18:16:58 +08:00
parent 502bb4543e
commit 6e316ddc10
7 changed files with 47 additions and 36 deletions
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10
mpp/hal/rkenc/common/vepu541_common.c
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@@ -983,6 +983,7 @@ MPP_RET vepu580_set_osd(Vepu541OsdCfg *cfg)
{ {
Vepu580OsdReg *regs = (Vepu580OsdReg *)cfg->reg_base; Vepu580OsdReg *regs = (Vepu580OsdReg *)cfg->reg_base;
MppDev dev = cfg->dev; MppDev dev = cfg->dev;
MppDevRegOffCfgs *reg_cfg = cfg->reg_cfg;
MppEncOSDPltCfg *plt_cfg = cfg->plt_cfg; MppEncOSDPltCfg *plt_cfg = cfg->plt_cfg;
MppEncOSDData2 osd; MppEncOSDData2 osd;
@@ -1044,11 +1045,10 @@ MPP_RET vepu580_set_osd(Vepu541OsdCfg *cfg)
regs->osd_addr[k] = fd; regs->osd_addr[k] = fd;
if (tmp->buf_offset) { if (tmp->buf_offset) {
MppDevRegOffsetCfg trans_cfg; if (reg_cfg)
mpp_dev_multi_offset_update(reg_cfg, VEPU580_OSD_ADDR_IDX_BASE + k, tmp->buf_offset);
trans_cfg.reg_idx = VEPU580_OSD_ADDR_IDX_BASE + k; else
trans_cfg.offset = tmp->buf_offset; mpp_dev_set_reg_offset(dev, VEPU580_OSD_ADDR_IDX_BASE + k, tmp->buf_offset);
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
} }
/* There should be enough buffer and offset should be 16B aligned */ /* There should be enough buffer and offset should be 16B aligned */

1
mpp/hal/rkenc/common/vepu541_common.h
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@@ -150,6 +150,7 @@ typedef struct Vepu541OsdPltColor_t {
typedef struct Vepu541OsdCfg_t { typedef struct Vepu541OsdCfg_t {
void *reg_base; void *reg_base;
MppDev dev; MppDev dev;
MppDevRegOffCfgs *reg_cfg;
MppEncOSDPltCfg *plt_cfg; MppEncOSDPltCfg *plt_cfg;
MppEncOSDData *osd_data; MppEncOSDData *osd_data;
MppEncOSDData2 *osd_data2; MppEncOSDData2 *osd_data2;

1
mpp/hal/rkenc/h264e/hal_h264e_vepu541.c
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@@ -185,6 +185,7 @@ static MPP_RET hal_h264e_vepu541_init(void *hal, MppEncHalCfg *cfg)
p->osd_cfg.reg_base = &p->regs_set; p->osd_cfg.reg_base = &p->regs_set;
p->osd_cfg.dev = p->dev; p->osd_cfg.dev = p->dev;
p->osd_cfg.reg_cfg = NULL;
p->osd_cfg.plt_cfg = &p->cfg->plt_cfg; p->osd_cfg.plt_cfg = &p->cfg->plt_cfg;
p->osd_cfg.osd_data = NULL; p->osd_cfg.osd_data = NULL;
p->osd_cfg.osd_data2 = NULL; p->osd_cfg.osd_data2 = NULL;

1
mpp/hal/rkenc/h264e/hal_h264e_vepu580.c
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@@ -182,6 +182,7 @@ static MPP_RET hal_h264e_vepu580_init(void *hal, MppEncHalCfg *cfg)
p->osd_cfg.reg_base = &p->regs_set.reg_osd; p->osd_cfg.reg_base = &p->regs_set.reg_osd;
p->osd_cfg.dev = p->dev; p->osd_cfg.dev = p->dev;
p->osd_cfg.reg_cfg = NULL;
p->osd_cfg.plt_cfg = &p->cfg->plt_cfg; p->osd_cfg.plt_cfg = &p->cfg->plt_cfg;
p->osd_cfg.osd_data = NULL; p->osd_cfg.osd_data = NULL;
p->osd_cfg.osd_data2 = NULL; p->osd_cfg.osd_data2 = NULL;

1
mpp/hal/rkenc/h265e/hal_h265e_vepu541.c
View File

@@ -656,6 +656,7 @@ MPP_RET hal_h265e_v541_init(void *hal, MppEncHalCfg *cfg)
ctx->osd_cfg.reg_base = ctx->regs; ctx->osd_cfg.reg_base = ctx->regs;
ctx->osd_cfg.dev = ctx->dev; ctx->osd_cfg.dev = ctx->dev;
ctx->osd_cfg.reg_cfg = NULL;
ctx->osd_cfg.plt_cfg = &ctx->cfg->plt_cfg; ctx->osd_cfg.plt_cfg = &ctx->cfg->plt_cfg;
ctx->osd_cfg.osd_data = NULL; ctx->osd_cfg.osd_data = NULL;
ctx->osd_cfg.osd_data2 = NULL; ctx->osd_cfg.osd_data2 = NULL;

50
mpp/hal/rkenc/h265e/hal_h265e_vepu580.c
View File

@@ -80,6 +80,7 @@ typedef struct H265eV580HalContext_t {
/* @frame_cnt starts from ZERO */ /* @frame_cnt starts from ZERO */
RK_U32 frame_cnt; RK_U32 frame_cnt;
Vepu541OsdCfg osd_cfg; Vepu541OsdCfg osd_cfg;
MppDevRegOffCfgs *reg_cfg;
void *roi_data; void *roi_data;
MppEncCfgSet *cfg; MppEncCfgSet *cfg;
@@ -1146,6 +1147,9 @@ MPP_RET hal_h265e_v580_init(void *hal, MppEncHalCfg *cfg)
ctx->osd_cfg.osd_data = NULL; ctx->osd_cfg.osd_data = NULL;
ctx->osd_cfg.osd_data2 = NULL; ctx->osd_cfg.osd_data2 = NULL;
mpp_dev_multi_offset_init(&ctx->reg_cfg, 24);
ctx->osd_cfg.reg_cfg = ctx->reg_cfg;
ctx->frame_type = INTRA_FRAME; ctx->frame_type = INTRA_FRAME;
{ /* setup default hardware config */ { /* setup default hardware config */
@@ -1212,6 +1216,11 @@ MPP_RET hal_h265e_v580_deinit(void *hal)
ctx->dev = NULL; ctx->dev = NULL;
} }
if (ctx->reg_cfg) {
mpp_dev_multi_offset_deinit(ctx->reg_cfg);
ctx->reg_cfg = NULL;
}
if (ctx->tune) { if (ctx->tune) {
vepu580_h265e_tune_deinit(ctx->tune); vepu580_h265e_tune_deinit(ctx->tune);
ctx->tune = NULL; ctx->tune = NULL;
@@ -1244,9 +1253,9 @@ static MPP_RET hal_h265e_vepu580_prepare(void *hal)
} }
static MPP_RET static MPP_RET
vepu580_h265_set_patch_info(MppDev dev, H265eSyntax_new *syn, Vepu541Fmt input_fmt, HalEncTask *task) vepu580_h265_set_patch_info(MppDevRegOffCfgs *cfgs, H265eSyntax_new *syn,
Vepu541Fmt input_fmt, HalEncTask *task)
{ {
MppDevRegOffsetCfg cfg_fd;
RK_U32 hor_stride = syn->pp.hor_stride; RK_U32 hor_stride = syn->pp.hor_stride;
RK_U32 ver_stride = syn->pp.ver_stride ? syn->pp.ver_stride : syn->pp.pic_height; RK_U32 ver_stride = syn->pp.ver_stride ? syn->pp.ver_stride : syn->pp.pic_height;
RK_U32 frame_size = hor_stride * ver_stride; RK_U32 frame_size = hor_stride * ver_stride;
@@ -1300,18 +1309,14 @@ vepu580_h265_set_patch_info(MppDev dev, H265eSyntax_new *syn, Vepu541Fmt input_f
/* input cb addr */ /* input cb addr */
if (u_offset) { if (u_offset) {
cfg_fd.reg_idx = 161; ret = mpp_dev_multi_offset_update(cfgs, 161, u_offset);
cfg_fd.offset = u_offset;
ret = mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &cfg_fd);
if (ret) if (ret)
mpp_err_f("set input cb addr offset failed %d\n", ret); mpp_err_f("set input cb addr offset failed %d\n", ret);
} }
/* input cr addr */ /* input cr addr */
if (v_offset) { if (v_offset) {
cfg_fd.reg_idx = 162; ret = mpp_dev_multi_offset_update(cfgs, 162, v_offset);
cfg_fd.offset = v_offset;
ret = mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &cfg_fd);
if (ret) if (ret)
mpp_err_f("set input cr addr offset failed %d\n", ret); mpp_err_f("set input cr addr offset failed %d\n", ret);
} }
@@ -1845,7 +1850,7 @@ void vepu580_h265_set_hw_address(H265eV580HalContext *ctx, hevc_vepu580_base *re
if (!syn->sp.non_reference_flag) { if (!syn->sp.non_reference_flag) {
regs->reg0163_rfpw_h_addr = mpp_buffer_get_fd(recon_buf->buf[0]); regs->reg0163_rfpw_h_addr = mpp_buffer_get_fd(recon_buf->buf[0]);
regs->reg0164_rfpw_b_addr = regs->reg0163_rfpw_h_addr; regs->reg0164_rfpw_b_addr = regs->reg0163_rfpw_h_addr;
mpp_dev_set_reg_offset(ctx->dev, 164, ctx->fbc_header_len); mpp_dev_multi_offset_update(ctx->reg_cfg, 164, ctx->fbc_header_len);
} }
regs->reg0165_rfpr_h_addr = mpp_buffer_get_fd(ref_buf->buf[0]); regs->reg0165_rfpr_h_addr = mpp_buffer_get_fd(ref_buf->buf[0]);
regs->reg0166_rfpr_b_addr = regs->reg0165_rfpr_h_addr; regs->reg0166_rfpr_b_addr = regs->reg0165_rfpr_h_addr;
@@ -1854,7 +1859,7 @@ void vepu580_h265_set_hw_address(H265eV580HalContext *ctx, hevc_vepu580_base *re
regs->reg0169_dspw_addr = mpp_buffer_get_fd(recon_buf->buf[1]); regs->reg0169_dspw_addr = mpp_buffer_get_fd(recon_buf->buf[1]);
regs->reg0170_dspr_addr = mpp_buffer_get_fd(ref_buf->buf[1]); regs->reg0170_dspr_addr = mpp_buffer_get_fd(ref_buf->buf[1]);
mpp_dev_set_reg_offset(ctx->dev, 166, ctx->fbc_header_len); mpp_dev_multi_offset_update(ctx->reg_cfg, 166, ctx->fbc_header_len);
if (syn->pp.tiles_enabled_flag) { if (syn->pp.tiles_enabled_flag) {
if (NULL == ctx->tile_grp) if (NULL == ctx->tile_grp)
@@ -1889,11 +1894,11 @@ void vepu580_h265_set_hw_address(H265eV580HalContext *ctx, hevc_vepu580_base *re
regs->reg0172_bsbt_addr = mpp_buffer_get_fd(enc_task->output); regs->reg0172_bsbt_addr = mpp_buffer_get_fd(enc_task->output);
/* TODO: stream size relative with syntax */ /* TODO: stream size relative with syntax */
regs->reg0173_bsbb_addr = regs->reg0172_bsbt_addr; regs->reg0173_bsbb_addr = regs->reg0172_bsbt_addr;
regs->reg0174_bsbr_addr = regs->reg0172_bsbt_addr; regs->reg0174_bsbr_addr = regs->reg0172_bsbt_addr;
regs->reg0175_adr_bsbs = regs->reg0172_bsbt_addr; regs->reg0175_adr_bsbs = regs->reg0172_bsbt_addr;
mpp_dev_set_reg_offset(ctx->dev, 175, mpp_packet_get_length(task->packet)); mpp_dev_multi_offset_update(ctx->reg_cfg, 175, mpp_packet_get_length(task->packet));
mpp_dev_set_reg_offset(ctx->dev, 172, mpp_buffer_get_size(enc_task->output)); mpp_dev_multi_offset_update(ctx->reg_cfg, 172, mpp_buffer_get_size(enc_task->output));
regs->reg0204_pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame); regs->reg0204_pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
regs->reg0204_pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame); regs->reg0204_pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
@@ -2121,7 +2126,7 @@ MPP_RET hal_h265e_v580_start(void *hal, HalEncTask *enc_task)
vepu580_h265_set_me_ram(syn, &hw_regs->reg_base, k); vepu580_h265_set_me_ram(syn, &hw_regs->reg_base, k);
/* set input info */ /* set input info */
vepu580_h265_set_patch_info(ctx->dev, syn, (Vepu541Fmt)fmt->format, enc_task); vepu580_h265_set_patch_info(ctx->reg_cfg, syn, (Vepu541Fmt)fmt->format, enc_task);
if (tile_num > 1) if (tile_num > 1)
hal_h265e_v580_set_uniform_tile(&hw_regs->reg_base, syn, k); hal_h265e_v580_set_uniform_tile(&hw_regs->reg_base, syn, k);
@@ -2131,21 +2136,24 @@ MPP_RET hal_h265e_v580_start(void *hal, HalEncTask *enc_task)
offset += stream_len; offset += stream_len;
reg_base->reg0173_bsbb_addr = mpp_buffer_get_fd(enc_task->output); reg_base->reg0173_bsbb_addr = mpp_buffer_get_fd(enc_task->output);
mpp_dev_set_reg_offset(ctx->dev, 175, offset); mpp_dev_multi_offset_update(ctx->reg_cfg, 175, offset);
mpp_dev_set_reg_offset(ctx->dev, 172, mpp_buffer_get_size(enc_task->output)); mpp_dev_multi_offset_update(ctx->reg_cfg, 172, mpp_buffer_get_size(enc_task->output));
} else { } else {
reg_base->reg0172_bsbt_addr = mpp_buffer_get_fd(ctx->hw_tile_stream); reg_base->reg0172_bsbt_addr = mpp_buffer_get_fd(ctx->hw_tile_stream);
/* TODO: stream size relative with syntax */ /* TODO: stream size relative with syntax */
reg_base->reg0173_bsbb_addr = reg_base->reg0172_bsbt_addr; reg_base->reg0173_bsbb_addr = reg_base->reg0172_bsbt_addr;
reg_base->reg0174_bsbr_addr = reg_base->reg0172_bsbt_addr; reg_base->reg0174_bsbr_addr = reg_base->reg0172_bsbt_addr;
reg_base->reg0175_adr_bsbs = reg_base->reg0172_bsbt_addr; reg_base->reg0175_adr_bsbs = reg_base->reg0172_bsbt_addr;
mpp_dev_set_reg_offset(ctx->dev, 172, mpp_buffer_get_size(ctx->hw_tile_stream)); mpp_dev_multi_offset_update(ctx->reg_cfg, 175, 0);
mpp_dev_multi_offset_update(ctx->reg_cfg, 172, mpp_buffer_get_size(ctx->hw_tile_stream));
} }
mpp_dev_set_reg_offset(ctx->dev, 164, ctx->fbc_header_len); mpp_dev_multi_offset_update(ctx->reg_cfg, 164, ctx->fbc_header_len);
mpp_dev_set_reg_offset(ctx->dev, 166, ctx->fbc_header_len); mpp_dev_multi_offset_update(ctx->reg_cfg, 166, ctx->fbc_header_len);
} }
hal_h265e_v580_send_regs(ctx->dev, hw_regs, reg_out); hal_h265e_v580_send_regs(ctx->dev, hw_regs, reg_out);
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFS, ctx->reg_cfg);
if (k < tile_num - 1) { if (k < tile_num - 1) {
if (!ctx->tile_parall_en) { if (!ctx->tile_parall_en) {
vepu580_h265_fbk *fb = &ctx->feedback; vepu580_h265_fbk *fb = &ctx->feedback;
@@ -2401,6 +2409,8 @@ MPP_RET hal_h265e_v580_get_task(void *hal, HalEncTask *task)
} }
memset(&ctx->feedback, 0, sizeof(vepu580_h265_fbk)); memset(&ctx->feedback, 0, sizeof(vepu580_h265_fbk));
mpp_dev_multi_offset_reset(ctx->reg_cfg);
hal_h265e_leave(); hal_h265e_leave();
return MPP_OK; return MPP_OK;
} }

19
utils/mpi_enc_utils.c
View File

@@ -904,11 +904,6 @@ MPP_RET mpi_enc_gen_osd_plt(MppEncOSDPlt *osd_plt, RK_U32 frame_cnt)
return MPP_OK; return MPP_OK;
} }
#define STEP_X 3
#define STEP_Y 2
#define STEP_W 2
#define STEP_H 2
MPP_RET mpi_enc_gen_osd_data(MppEncOSDData *osd_data, MppBufferGroup group, MPP_RET mpi_enc_gen_osd_data(MppEncOSDData *osd_data, MppBufferGroup group,
RK_U32 width, RK_U32 height, RK_U32 frame_cnt) RK_U32 width, RK_U32 height, RK_U32 frame_cnt)
{ {
@@ -919,10 +914,12 @@ MPP_RET mpi_enc_gen_osd_data(MppEncOSDData *osd_data, MppBufferGroup group,
RK_U32 buf_size = 0; RK_U32 buf_size = 0;
RK_U32 mb_w_max = MPP_ALIGN(width, 16) / 16; RK_U32 mb_w_max = MPP_ALIGN(width, 16) / 16;
RK_U32 mb_h_max = MPP_ALIGN(height, 16) / 16; RK_U32 mb_h_max = MPP_ALIGN(height, 16) / 16;
RK_U32 mb_x = (frame_cnt * STEP_X) % mb_w_max; RK_U32 step_x = MPP_ALIGN(mb_w_max, 8) / 8;
RK_U32 mb_y = (frame_cnt * STEP_Y) % mb_h_max; RK_U32 step_y = MPP_ALIGN(mb_h_max, 16) / 16;
RK_U32 mb_w = STEP_W; RK_U32 mb_x = (frame_cnt * step_x) % mb_w_max;
RK_U32 mb_h = STEP_H; RK_U32 mb_y = (frame_cnt * step_y) % mb_h_max;
RK_U32 mb_w = step_x;
RK_U32 mb_h = step_y;
MppBuffer buf = osd_data->buf; MppBuffer buf = osd_data->buf;
if (buf) if (buf)
@@ -947,8 +944,8 @@ MPP_RET mpi_enc_gen_osd_data(MppEncOSDData *osd_data, MppBufferGroup group,
buf_offset += region_size; buf_offset += region_size;
mb_x += STEP_X; mb_x += step_x;
mb_y += STEP_Y; mb_y += step_y;
if (mb_x >= mb_w_max) if (mb_x >= mb_w_max)
mb_x -= mb_w_max; mb_x -= mb_w_max;
if (mb_y >= mb_h_max) if (mb_y >= mb_h_max)