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[mpp_enc]: Add split output flag

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Split output flag is for low delay packet output mode.

Change-Id: I2f743f14b89864625406ebf94687f4f838f0df15
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
This commit is contained in:
Herman Chen
2022-05-10 11:19:23 +08:00
parent badde4fc94
commit 6ddafd0bfa
4 changed files with 17 additions and 1 deletions
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10
inc/rk_venc_cmd.h
View File

@@ -902,6 +902,7 @@ typedef struct MppEncH265SliceCfg_t {
* when splitmode is 1, this value presents lcu line number * when splitmode is 1, this value presents lcu line number
*/ */
RK_U32 slice_size; RK_U32 slice_size;
RK_U32 slice_out;
RK_U32 loop_filter_across_slices_enabled_flag; RK_U32 loop_filter_across_slices_enabled_flag;
} MppEncH265SliceCfg; } MppEncH265SliceCfg;
@@ -1094,6 +1095,7 @@ typedef enum MppEncSliceSplit_e {
/* change on quant parameter */ /* change on quant parameter */
MPP_ENC_SPLIT_CFG_CHANGE_MODE = (1 << 0), MPP_ENC_SPLIT_CFG_CHANGE_MODE = (1 << 0),
MPP_ENC_SPLIT_CFG_CHANGE_ARG = (1 << 1), MPP_ENC_SPLIT_CFG_CHANGE_ARG = (1 << 1),
MPP_ENC_SPLIT_CFG_CHANGE_OUTPUT = (1 << 2),
MPP_ENC_SPLIT_CFG_CHANGE_ALL = (0xFFFFFFFF), MPP_ENC_SPLIT_CFG_CHANGE_ALL = (0xFFFFFFFF),
} MppEncSliceSplitChange; } MppEncSliceSplitChange;
@@ -1124,6 +1126,14 @@ typedef struct MppEncSliceSplit_t {
* for each slice. * for each slice.
*/ */
RK_U32 split_arg; RK_U32 split_arg;
/*
* slice split output mode
*
* 0 - output all slice in one packet
* 1 - output each slice in a single packet
*/
RK_U32 split_out;
} MppEncSliceSplit; } MppEncSliceSplit;
/** /**

3
mpp/base/mpp_enc_cfg.cpp
View File

@@ -244,6 +244,7 @@ public:
/* split config */ \ /* split config */ \
ENTRY(split, mode, U32, RK_U32, MPP_ENC_SPLIT_CFG_CHANGE_MODE, split, split_mode) \ ENTRY(split, mode, U32, RK_U32, MPP_ENC_SPLIT_CFG_CHANGE_MODE, split, split_mode) \
ENTRY(split, arg, U32, RK_U32, MPP_ENC_SPLIT_CFG_CHANGE_ARG, split, split_arg) \ ENTRY(split, arg, U32, RK_U32, MPP_ENC_SPLIT_CFG_CHANGE_ARG, split, split_arg) \
ENTRY(split, out, U32, RK_U32, MPP_ENC_SPLIT_CFG_CHANGE_OUTPUT, split, split_out) \
/* hardware detail config */ \ /* hardware detail config */ \
ENTRY(hw, qp_row, S32, RK_S32, MPP_ENC_HW_CFG_CHANGE_QP_ROW, hw, qp_delta_row) \ ENTRY(hw, qp_row, S32, RK_S32, MPP_ENC_HW_CFG_CHANGE_QP_ROW, hw, qp_delta_row) \
ENTRY(hw, qp_row_i, S32, RK_S32, MPP_ENC_HW_CFG_CHANGE_QP_ROW_I, hw, qp_delta_row_i) \ ENTRY(hw, qp_row_i, S32, RK_S32, MPP_ENC_HW_CFG_CHANGE_QP_ROW_I, hw, qp_delta_row_i) \
@@ -352,7 +353,7 @@ MppEncCfgService::MppEncCfgService() :
MPP_RET ret; MPP_RET ret;
RK_S32 i; RK_S32 i;
ret = mpp_trie_init(&trie, 1555, cfg_cnt); ret = mpp_trie_init(&trie, 1560, cfg_cnt);
if (ret) { if (ret) {
mpp_err_f("failed to init enc cfg set trie\n"); mpp_err_f("failed to init enc cfg set trie\n");
return ; return ;

3
mpp/codec/enc/h264/h264e_api_v2.c
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@@ -447,6 +447,9 @@ static MPP_RET h264e_proc_split_cfg(MppEncSliceSplit *dst, MppEncSliceSplit *src
if (change & MPP_ENC_SPLIT_CFG_CHANGE_ARG) if (change & MPP_ENC_SPLIT_CFG_CHANGE_ARG)
dst->split_arg = src->split_arg; dst->split_arg = src->split_arg;
if (change & MPP_ENC_SPLIT_CFG_CHANGE_OUTPUT)
dst->split_out = src->split_out;
dst->change |= change; dst->change |= change;
src->change = 0; src->change = 0;

2
mpp/codec/enc/h265/h265e_api.c
View File

@@ -454,8 +454,10 @@ static MPP_RET h265e_proc_split_cfg(MppEncH265SliceCfg *dst, MppEncSliceSplit *s
if (src->split_mode == MPP_ENC_SPLIT_BY_CTU) if (src->split_mode == MPP_ENC_SPLIT_BY_CTU)
dst->split_mode = 1; dst->split_mode = 1;
dst->slice_size = src->split_arg; dst->slice_size = src->split_arg;
dst->slice_out = src->split_out;
} else { } else {
dst->split_enable = 0; dst->split_enable = 0;
dst->slice_out = 0;
} }
return MPP_OK; return MPP_OK;