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[avs2d]: Fix fbc output error.

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1. add offset_y for output frame.
2. set hor_stride 64 aligned.

Signed-off-by: xueman.ruan <xueman.ruan@rock-chips.com>
Change-Id: Ie399c2d1f9d783e498d16fbaa409529f7dff71ea
This commit is contained in:
xueman.ruan
2022-11-21 10:39:02 +08:00
parent f36b3425dc
commit 69870145ef
3 changed files with 26 additions and 2 deletions
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7
mpp/codec/dec/avs2/avs2d_dpb.c
View File

@@ -458,6 +458,7 @@ static Avs2dFrame_t *dpb_alloc_frame(Avs2dCtx_t *p_dec, HalDecTask *task)
Avs2dFrameMgr_t *mgr = &p_dec->frm_mgr;
RK_U32 ctu_size = 1 << (p_dec->vsh.lcu_size);
RK_U32 bitdepth = p_dec->vsh.bit_depth;
RK_U32 ver_stride = vsh->vertical_size;
avs2d_dbg_dpb("In.");
frm = dpb_get_one_frame(mgr, vsh, ph);
@@ -484,6 +485,7 @@ static Avs2dFrame_t *dpb_alloc_frame(Avs2dCtx_t *p_dec, HalDecTask *task)
}
if (MPP_FRAME_FMT_IS_FBC(p_dec->init.cfg->base.out_fmt)) {
// fbc header alignment
RK_U32 fbc_hdr_stride = MPP_ALIGN(vsh->horizontal_size, 64);
mpp_frame_set_fmt(mframe, mpp_frame_get_fmt(mframe) | (p_dec->init.cfg->base.out_fmt & (MPP_FRAME_FBC_MASK)));
@@ -492,6 +494,9 @@ static Avs2dFrame_t *dpb_alloc_frame(Avs2dCtx_t *p_dec, HalDecTask *task)
fbc_hdr_stride = MPP_ALIGN(vsh->horizontal_size, 256) | 256;
mpp_frame_set_fbc_hdr_stride(mframe, fbc_hdr_stride);
// fbc output frame update
mpp_frame_set_offset_y(mframe, 8);
ver_stride += 16;
}
if (p_dec->is_hdr)
@@ -500,7 +505,7 @@ static Avs2dFrame_t *dpb_alloc_frame(Avs2dCtx_t *p_dec, HalDecTask *task)
mpp_frame_set_width(mframe, vsh->horizontal_size);
mpp_frame_set_height(mframe, vsh->vertical_size);
mpp_frame_set_hor_stride(mframe, (MPP_ALIGN(vsh->horizontal_size, ctu_size) * bitdepth + 7) / 8);
mpp_frame_set_ver_stride(mframe, MPP_ALIGN(vsh->vertical_size, ctu_size));
mpp_frame_set_ver_stride(mframe, MPP_ALIGN(ver_stride, ctu_size));
mpp_frame_set_pts(mframe, mpp_packet_get_pts(task->input_packet));
mpp_frame_set_dts(mframe, mpp_packet_get_dts(task->input_packet));
mpp_frame_set_errinfo(mframe, 0);

9
mpp/hal/rkdec/avs2d/hal_avs2d_rkv.c
View File

@@ -95,6 +95,11 @@ static RK_U32 avs2d_len_align(RK_U32 val)
return (2 * MPP_ALIGN(val, 16));
}
static RK_U32 avs2d_hor_align_64(RK_U32 val)
{
return MPP_ALIGN(val, 64);
}
static MPP_RET prepare_header(Avs2dHalCtx_t *p_hal, RK_U8 *data, RK_U32 len)
{
RK_U32 i, j;
@@ -529,7 +534,11 @@ MPP_RET hal_avs2d_rkv_init(void *hal, MppHalCfg *cfg)
reg_ctx->sclst_offset = reg_ctx->reg_buf[0].offset_sclst;
}
if (MPP_FRAME_FMT_IS_FBC(cfg->cfg->base.out_fmt))
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, avs2d_hor_align_64);
else
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, avs2d_hor_align);
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, avs2d_ver_align);
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, avs2d_len_align);

10
mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.c
View File

@@ -95,6 +95,11 @@ static RK_U32 avs2d_len_align(RK_U32 val)
return (2 * MPP_ALIGN(val, 16));
}
static RK_U32 avs2d_hor_align_64(RK_U32 val)
{
return MPP_ALIGN(val, 64);
}
static MPP_RET prepare_header(Avs2dHalCtx_t *p_hal, RK_U8 *data, RK_U32 len)
{
RK_U32 i, j;
@@ -592,6 +597,11 @@ MPP_RET hal_avs2d_vdpu382_init(void *hal, MppHalCfg *cfg)
reg_ctx->sclst_offset = reg_ctx->reg_buf[0].offset_sclst;
}
if (MPP_FRAME_FMT_IS_FBC(cfg->cfg->base.out_fmt))
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, avs2d_hor_align_64);
else
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, avs2d_hor_align);
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, avs2d_hor_align);
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, avs2d_ver_align);
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, avs2d_len_align);