mirror of
https://github.com/nyanmisaka/mpp.git
synced 2025-10-06 17:46:50 +08:00
[mpp]: Remove RKPLATFORM macro
Mpp will only run under Linux environment. Windows support will be removed. Change-Id: I52de4bd69f6d7b34507edeb6642668e225fcbd38 Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
This commit is contained in:
110
CMakeLists.txt
110
CMakeLists.txt
@@ -31,11 +31,6 @@ if(NOT COMMAND find_host_program)
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endmacro()
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endif()
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set(RKPLATFORM "" CACHE BOOL "Enable RK HW CONFIG")
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if (RKPLATFORM)
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ADD_DEFINITIONS(-DRKPLATFORM)
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endif(RKPLATFORM)
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project (rk_mpp)
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cmake_minimum_required (VERSION 2.8.8) # OBJECT libraries require 2.8.8
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@@ -127,25 +122,6 @@ if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
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set(GCC true)
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endif()
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if(INTEL_CXX AND WIN32)
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# treat icl roughly like MSVC
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set(MSVC true)
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endif()
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if(MSVC)
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option(STATIC_LINK_CRT "Statically link C runtime for release builds" OFF)
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if (STATIC_LINK_CRT)
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set(CompilerFlags CMAKE_CXX_FLAGS_RELEASE CMAKE_C_FLAGS_RELEASE)
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foreach(CompilerFlag ${CompilerFlags})
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string(REPLACE "/MD" "/MT" ${CompilerFlag} "${${CompilerFlag}}")
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endforeach()
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endif (STATIC_LINK_CRT)
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add_definitions(/W3) # Full warnings
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add_definitions(/Ob2) # always inline
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add_definitions(/MP) # multithreaded build
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# disable Microsofts suggestions for proprietary secure APIs
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add_definitions(/D_CRT_SECURE_NO_WARNINGS)
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endif(MSVC)
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if(INTEL_CXX AND UNIX)
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# treat icpc roughly like gcc
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set(GCC true)
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@@ -198,48 +174,6 @@ if(EXISTS "${PROJECT_SOURCE_DIR}/.svn/")
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find_host_package(Subversion)
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if(Subversion_FOUND)
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set(HAVE_SVN true)
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else()
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if(WIN32)
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# The official subversion client is not available, so fall back to
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# tortoise if it is installed.
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find_program(TORTOISE_WCREV_EXECUTABLE
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NAMES SubWCRev.exe
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PATHS "[HKEY_LOCAL_MACHINE\\SOFTWARE\\TortoiseSVN;Directory]/bin"
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)
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if (NOT TORTOISE_WCREV_EXECUTABLE)
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message(STATUS "TortoiseSVN was not found.")
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else(NOT TORTOISE_WCREV_EXECUTABLE)
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message(STATUS "TortoiseSVN was Found.")
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set(HAVE_SVN true)
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macro(Subversion_WC_INFO dir prefix)
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# the subversion commands should be executed with the C locale, otherwise
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# the message (which are parsed) may be translated, Alex
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set(_Subversion_SAVED_LC_ALL "$ENV{LC_ALL}")
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set(ENV{LC_ALL} C)
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execute_process(COMMAND ${TORTOISE_WCREV_EXECUTABLE} ${dir}
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OUTPUT_VARIABLE ${prefix}_WC_INFO
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ERROR_VARIABLE Subversion_svn_info_error
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RESULT_VARIABLE Subversion_svn_info_result
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OUTPUT_STRIP_TRAILING_WHITESPACE
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ERROR_STRIP_TRAILING_WHITESPACE)
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if(NOT ${Subversion_svn_info_result} EQUAL 0)
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message(SEND_ERROR "Command \"${TORTOISE_WCREV_EXECUTABLE} ${dir}\" failed with output:\n${Subversion_svn_info_error}")
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else()
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string(REGEX REPLACE "^(.*\n)?Last committed at revision ([0-9]*)\n.*"
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"\\2" ${prefix}_WC_REVISION "${${prefix}_WC_INFO}")
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endif()
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set(Project_WC_LAST_CHANGED_AUTHOR "unknown")
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set(Project_WC_LAST_CHANGED_DATE "unknown")
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# restore the previous LC_ALL
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set(ENV{LC_ALL} ${_Subversion_SAVED_LC_ALL})
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endmacro()
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endif (NOT TORTOISE_WCREV_EXECUTABLE)
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endif(WIN32)
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endif(Subversion_FOUND)
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endif(EXISTS "${PROJECT_SOURCE_DIR}/.svn/")
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@@ -363,25 +297,6 @@ if(WARNINGS_AS_ERRORS)
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endif()
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endif(WARNINGS_AS_ERRORS)
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# ----------------------------------------------------------------------------
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# Visual leak detector
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# ----------------------------------------------------------------------------
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if (WIN32)
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find_host_package(VLD QUIET)
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if(VLD_FOUND)
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add_definitions(-DHAVE_VLD)
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include_directories(${VLD_INCLUDE_DIRS})
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set(PLATFORM_LIBS ${PLATFORM_LIBS} ${VLD_LIBRARIES})
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link_directories(${VLD_LIBRARY_DIRS})
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endif()
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option(WINXP_SUPPORT "Make binaries compatible with Windows XP" OFF)
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if(WINXP_SUPPORT)
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# force use of workarounds for CONDITION_VARIABLE and atomic
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# intrinsics introduced after XP
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add_definitions(-D_WIN32_WINNT=_WIN32_WINNT_WINXP)
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endif()
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endif()
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# ----------------------------------------------------------------------------
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# look for stdint.h
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# ----------------------------------------------------------------------------
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@@ -392,31 +307,6 @@ if(MSVC)
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endif(NOT HAVE_STDINT_H)
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endif(MSVC)
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# ----------------------------------------------------------------------------
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# On window import win32 pthread library
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# ----------------------------------------------------------------------------
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if(MSVC)
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set(WIN32_PTHREAD_INCLUDE_DIRS "${CMAKE_CURRENT_SOURCE_DIR}/osal/windows/pthread/inc")
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include_directories(${WIN32_PTHREAD_INCLUDE_DIRS})
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add_library(pthread SHARED IMPORTED)
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message(STATUS "platform X86 ${X86} X64 ${X64}")
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set(WIN32_PTHREAD_LIB_DIRS "${CMAKE_CURRENT_SOURCE_DIR}/osal/windows/pthread/lib")
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set(WIN32_PTHREAD_DLL_DIRS "${CMAKE_CURRENT_SOURCE_DIR}/osal/windows/pthread/dll")
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if(X64)
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set(WIN32_ARCH "x64")
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else()
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set(WIN32_ARCH "x86")
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endif()
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include_directories("${WIN32_PTHREAD_LIB_DIRS}/${WIN32_ARCH}")
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include_directories("${WIN32_PTHREAD_DLL_DIRS}/${WIN32_ARCH}")
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set_target_properties(pthread PROPERTIES
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IMPORTED_LOCATION
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"${WIN32_PTHREAD_LIB_DIRS}/${WIN32_ARCH}/pthreadVC2.dll")
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set_target_properties(pthread PROPERTIES
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IMPORTED_IMPLIB
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"${WIN32_PTHREAD_LIB_DIRS}/${WIN32_ARCH}/pthreadVC2.lib")
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endif()
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# ----------------------------------------------------------------------------
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# Share library option
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# ----------------------------------------------------------------------------
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1
debian/rules
vendored
1
debian/rules
vendored
@@ -26,6 +26,5 @@ override_dh_auto_configure:
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dh_auto_configure -- \
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-DCMAKE_TOOLCHAIN_FILE=/etc/dpkg-cross/cmake/CMakeCross.txt \
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-DCMAKE_BUILD_TYPE=Release \
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-DRKPLATFORM=ON \
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-DHAVE_DRM=ON \
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-DARM_MIX_32_64=ON
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@@ -825,9 +825,10 @@ MPP_RET mpp_buf_slot_set_prop(MppBufSlots slots, RK_S32 index, SlotPropType type
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dst->eos = slot->eos;
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if (mpp_frame_info_cmp(impl->info, impl->info_set)) {
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impl->info_changed = 1;
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#ifdef RKPLATFORM
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MppFrameImpl *old = (MppFrameImpl *)impl->info;
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impl->info_changed = 1;
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if (old->width || old->height) {
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mpp_dbg(MPP_DBG_INFO, "info change found\n");
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mpp_dbg(MPP_DBG_INFO,
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@@ -839,7 +840,6 @@ MPP_RET mpp_buf_slot_set_prop(MppBufSlots slots, RK_S32 index, SlotPropType type
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"new width %4d height %4d stride hor %4d ver %4d fmt %4d\n",
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dst->width, dst->height, dst->hor_stride, dst->ver_stride,
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dst->fmt);
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#endif
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// info change found here
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}
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} break;
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@@ -188,12 +188,9 @@ int mpp_buffer_get_fd_with_caller(MppBuffer buffer, const char *caller)
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MppBufferImpl *p = (MppBufferImpl*)buffer;
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int fd = p->info.fd;
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#ifdef RKPLATFORM
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mpp_assert(fd >= 0);
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if (fd < 0)
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mpp_err("mpp_buffer_get_fd buffer %p fd %d caller %s\n", buffer, fd, caller);
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#endif
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return fd;
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}
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@@ -28,10 +28,6 @@ set_target_properties(mpp_hal PROPERTIES FOLDER "mpp/hal")
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add_subdirectory(worker/mpp_device)
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add_subdirectory(worker/libv4l2)
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if(RKPLATFORM)
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set(RKPLAT_VPU mpp_device)
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endif(RKPLATFORM)
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target_link_libraries(mpp_hal
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${HAL_AVSD}
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${HAL_H263D}
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@@ -45,5 +41,5 @@ target_link_libraries(mpp_hal
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${HAL_H264E}
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${HAL_JPEGE}
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hal_dummy
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${RKPLAT_VPU}
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mpp_device
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)
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@@ -18,9 +18,7 @@
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#include <stdio.h>
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#include <string.h>
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#ifdef RKPLATFORM
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#include <unistd.h>
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#endif
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#include "mpp_common.h"
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#include "mpp_platform.h"
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@@ -114,7 +114,7 @@ MPP_RET hal_avsd_init(void *decoder, MppHalCfg *cfg)
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//!< callback function to parser module
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p_hal->init_cb = cfg->hal_int_cb;
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//!< mpp_device_init
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#ifdef RKPLATFORM
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MppDevCfg dev_cfg = {
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.type = MPP_CTX_DEC, /* type */
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.coding = MPP_VIDEO_CodingAVS, /* coding */
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@@ -126,19 +126,15 @@ MPP_RET hal_avsd_init(void *decoder, MppHalCfg *cfg)
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mpp_err("mpp_device_init failed. ret: %d\n", ret);
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return ret;
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}
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#endif
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//< get buffer group
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if (p_hal->buf_group == NULL) {
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RK_U32 buf_size = 0;
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#ifdef RKPLATFORM
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mpp_log_f("mpp_buffer_group_get_internal used ion In");
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RK_U32 buf_size = (1920 * 1088) / 16;
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FUN_CHECK(ret = mpp_buffer_group_get_internal(&p_hal->buf_group, MPP_BUFFER_TYPE_ION));
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#else
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FUN_CHECK(ret = mpp_buffer_group_get_internal(&p_hal->buf_group, MPP_BUFFER_TYPE_NORMAL));
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#endif
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buf_size = (1920 * 1088) / 16;
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FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, &p_hal->mv_buf, buf_size));
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}
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mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, avsd_hor_align);
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mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, avsd_ver_align);
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mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, avsd_len_align);
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@@ -178,14 +174,11 @@ MPP_RET hal_avsd_deinit(void *decoder)
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INP_CHECK(ret, NULL == decoder);
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//!< mpp_device_init
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#ifdef RKPLATFORM
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if (p_hal->dev_ctx) {
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ret = mpp_device_deinit(p_hal->dev_ctx);
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if (MPP_OK != ret) {
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if (ret)
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mpp_err("mpp_device_deinit failed. ret: %d\n", ret);
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}
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}
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#endif
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if (p_hal->mv_buf) {
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FUN_CHECK(ret = mpp_buffer_put(p_hal->mv_buf));
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}
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@@ -248,18 +241,17 @@ MPP_RET hal_avsd_start(void *decoder, HalTaskInfo *task)
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AVSD_HAL_TRACE("In.");
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INP_CHECK(ret, NULL == decoder);
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if (task->dec.flags.parse_err ||
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task->dec.flags.ref_err) {
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if (task->dec.flags.parse_err || task->dec.flags.ref_err) {
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goto __RETURN;
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}
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p_hal->frame_no++;
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#ifdef RKPLATFORM
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if (mpp_device_send_reg(p_hal->dev_ctx, p_hal->p_regs, AVSD_REGISTERS)) {
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ret = mpp_device_send_reg(p_hal->dev_ctx, p_hal->p_regs, AVSD_REGISTERS);
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if (ret) {
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ret = MPP_ERR_VPUHW;
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mpp_err_f("Avs decoder FlushRegs fail. \n");
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}
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#endif
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__RETURN:
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AVSD_HAL_TRACE("Out.");
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@@ -285,9 +277,8 @@ MPP_RET hal_avsd_wait(void *decoder, HalTaskInfo *task)
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task->dec.flags.ref_err) {
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goto __SKIP_HARD;
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}
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#ifdef RKPLATFORM
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mpp_device_wait_reg(p_hal->dev_ctx, p_hal->p_regs, AVSD_REGISTERS);
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#endif
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__SKIP_HARD:
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if (p_hal->init_cb.callBack) {
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@@ -393,5 +384,3 @@ const MppHalApi hal_api_avsd = {
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.flush = hal_avsd_flush,
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.control = hal_avsd_control,
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};
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@@ -21,10 +21,8 @@
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#ifdef RKPLATFORM
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#include <dlfcn.h>
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#include <unistd.h>
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#endif
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#include "rk_type.h"
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#include "mpp_device.h"
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@@ -74,20 +72,6 @@ static void explain_input_buffer(void *hal, HalDecTask *task)
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}
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}
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/*!
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***********************************************************************
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* \brief
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* VPUClientGetIOMMUStatus
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***********************************************************************
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*/
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//extern "C"
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#ifndef RKPLATFORM
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RK_S32 VPUClientGetIOMMUStatus()
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{
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return 0;
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}
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#endif
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/*!
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***********************************************************************
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* \brief
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@@ -172,31 +156,27 @@ MPP_RET hal_h264d_init(void *hal, MppHalCfg *cfg)
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}
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//!< callback function to parser module
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p_hal->init_cb = cfg->hal_int_cb;
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mpp_env_get_u32("rkv_h264d_debug", &rkv_h264d_hal_debug, 0);
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//!< mpp_device_init
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#ifdef RKPLATFORM
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MppDevCfg dev_cfg = {
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.type = MPP_CTX_DEC, /* type */
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.coding = MPP_VIDEO_CodingAVC, /* coding */
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.platform = hard_platform, /* platform */
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.pp_enable = 0, /* pp_enable */
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};
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ret = mpp_device_init(&p_hal->dev_ctx, &dev_cfg);
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if (ret) {
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mpp_err("mpp_device_init failed ret: %d\n", ret);
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goto __FAILED;
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}
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#endif
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//< get buffer group
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if (p_hal->buf_group == NULL) {
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#ifdef RKPLATFORM
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mpp_log_f("mpp_buffer_group_get_internal used ion In");
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FUN_CHECK(ret = mpp_buffer_group_get_internal
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(&p_hal->buf_group, MPP_BUFFER_TYPE_ION));
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#else
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FUN_CHECK(ret = mpp_buffer_group_get_internal
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(&p_hal->buf_group, MPP_BUFFER_TYPE_NORMAL));
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#endif
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}
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//!< run init funtion
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@@ -220,15 +200,14 @@ MPP_RET hal_h264d_deinit(void *hal)
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H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
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FUN_CHECK(ret = p_hal->hal_api.deinit(hal));
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//!< mpp_device_init
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#ifdef RKPLATFORM
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if (p_hal->dev_ctx) {
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ret = mpp_device_deinit(p_hal->dev_ctx);
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if (MPP_OK != ret) {
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if (ret)
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mpp_err("mpp_device_deinit failed. ret: %d\n", ret);
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}
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}
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#endif
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if (p_hal->buf_group) {
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FUN_CHECK(ret = mpp_buffer_group_put(p_hal->buf_group));
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}
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|
@@ -704,12 +704,12 @@ MPP_RET rkv_h264d_start(void *hal, HalTaskInfo *task)
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p_regs[1] |= 0x00000061; // run hardware, enable buf_empty_en
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#ifdef RKPLATFORM
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if (mpp_device_send_reg(p_hal->dev_ctx, (RK_U32 *)p_regs, DEC_RKV_REGISTERS)) {
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ret = mpp_device_send_reg(p_hal->dev_ctx, (RK_U32 *)p_regs,
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DEC_RKV_REGISTERS);
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if (ret) {
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ret = MPP_ERR_VPUHW;
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H264D_ERR("H264 RKV FlushRegs fail. \n");
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}
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#endif
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(void)task;
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__RETURN:
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@@ -736,7 +736,6 @@ MPP_RET rkv_h264d_wait(void *hal, HalTaskInfo *task)
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goto __SKIP_HARD;
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}
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#ifdef RKPLATFORM
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{
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RK_S32 wait_ret = -1;
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wait_ret = mpp_device_wait_reg(p_hal->dev_ctx, (RK_U32 *)p_regs, DEC_RKV_REGISTERS);
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@@ -745,7 +744,6 @@ MPP_RET rkv_h264d_wait(void *hal, HalTaskInfo *task)
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H264D_ERR("H264 RKV FlushRegs fail. \n");
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}
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}
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#endif
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__SKIP_HARD:
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if (p_hal->init_cb.callBack) {
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||||
|
@@ -858,14 +858,12 @@ MPP_RET vdpu1_h264d_start(void *hal, HalTaskInfo *task)
|
||||
p_regs->SwReg57.sw_intra_dblspeed = 1;
|
||||
p_regs->SwReg57.sw_paral_bus = 1;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (mpp_device_send_reg(p_hal->dev_ctx, (RK_U32 *)reg_ctx->regs,
|
||||
DEC_VDPU1_REGISTERS)) {
|
||||
ret = mpp_device_send_reg(p_hal->dev_ctx, (RK_U32 *)reg_ctx->regs,
|
||||
DEC_VDPU1_REGISTERS);
|
||||
if (ret) {
|
||||
ret = MPP_ERR_VPUHW;
|
||||
mpp_err_f("H264 VDPU1 FlushRegs fail, pid=%d, hal_frame_no=%d. \n",
|
||||
getpid());
|
||||
mpp_err_f("H264 VDPU1 FlushRegs fail, pid %d. \n", getpid());
|
||||
}
|
||||
#endif
|
||||
|
||||
__RETURN:
|
||||
(void)task;
|
||||
@@ -890,7 +888,7 @@ MPP_RET vdpu1_h264d_wait(void *hal, HalTaskInfo *task)
|
||||
task->dec.flags.ref_err) {
|
||||
goto __SKIP_HARD;
|
||||
}
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
{
|
||||
RK_S32 wait_ret = -1;
|
||||
wait_ret = mpp_device_wait_reg(p_hal->dev_ctx, (RK_U32 *)reg_ctx->regs,
|
||||
@@ -900,7 +898,6 @@ MPP_RET vdpu1_h264d_wait(void *hal, HalTaskInfo *task)
|
||||
mpp_err("H264 VDPU1 wait result fail, pid=%d.\n", getpid());
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
__SKIP_HARD:
|
||||
if (p_hal->init_cb.callBack) {
|
||||
|
@@ -818,13 +818,14 @@ MPP_RET vdpu2_h264d_start(void *hal, HalTaskInfo *task)
|
||||
p_regs->sw57.intra_dbl3t = 1;
|
||||
p_regs->sw57.inter_dblspeed = 1;
|
||||
p_regs->sw57.intra_dblspeed = 1;
|
||||
#ifdef RKPLATFORM
|
||||
if (mpp_device_send_reg(p_hal->dev_ctx, (RK_U32 *)reg_ctx->regs,
|
||||
DEC_VDPU_REGISTERS)) {
|
||||
|
||||
ret = mpp_device_send_reg(p_hal->dev_ctx, (RK_U32 *)reg_ctx->regs,
|
||||
DEC_VDPU_REGISTERS);
|
||||
if (ret) {
|
||||
ret = MPP_ERR_VPUHW;
|
||||
mpp_err("H264 VDPU FlushRegs fail, pid=%d.\n", getpid());
|
||||
}
|
||||
#endif
|
||||
|
||||
__RETURN:
|
||||
(void)task;
|
||||
return ret = MPP_OK;
|
||||
@@ -847,7 +848,7 @@ MPP_RET vdpu2_h264d_wait(void *hal, HalTaskInfo *task)
|
||||
task->dec.flags.ref_err) {
|
||||
goto __SKIP_HARD;
|
||||
}
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
{
|
||||
RK_S32 wait_ret = -1;
|
||||
wait_ret = mpp_device_wait_reg(p_hal->dev_ctx, (RK_U32 *)reg_ctx->regs,
|
||||
@@ -857,7 +858,6 @@ MPP_RET vdpu2_h264d_wait(void *hal, HalTaskInfo *task)
|
||||
mpp_err("H264 VDPU wait result fail, pid=%d.\n", getpid());
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
__SKIP_HARD:
|
||||
if (p_hal->init_cb.callBack) {
|
||||
|
@@ -292,21 +292,21 @@ static MPP_RET hal_h265d_alloc_res(void *hal)
|
||||
ret = mpp_buffer_get(reg_cxt->group,
|
||||
®_cxt->g_buf[i].scaling_list_data,
|
||||
SCALING_LIST_SIZE);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("h265d scaling_list_data get buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = mpp_buffer_get(reg_cxt->group, ®_cxt->g_buf[i].pps_data,
|
||||
PPS_SIZE);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("h265d pps_data get buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = mpp_buffer_get(reg_cxt->group, ®_cxt->g_buf[i].rps_data,
|
||||
RPS_SIZE);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("h265d rps_data get buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -315,19 +315,19 @@ static MPP_RET hal_h265d_alloc_res(void *hal)
|
||||
reg_cxt->hw_regs = mpp_calloc_size(void, sizeof(H265d_REGS_t));
|
||||
ret = mpp_buffer_get(reg_cxt->group, ®_cxt->scaling_list_data,
|
||||
SCALING_LIST_SIZE);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("h265d scaling_list_data get buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = mpp_buffer_get(reg_cxt->group, ®_cxt->pps_data, PPS_SIZE);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("h265d pps_data get buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = mpp_buffer_get(reg_cxt->group, ®_cxt->rps_data, RPS_SIZE);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("h265d rps_data get buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -345,14 +345,14 @@ static MPP_RET hal_h265d_release_res(void *hal)
|
||||
for (i = 0; i < MAX_GEN_REG; i++) {
|
||||
if (reg_cxt->g_buf[i].scaling_list_data) {
|
||||
ret = mpp_buffer_put(reg_cxt->g_buf[i].scaling_list_data);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("h265d scaling_list_data free buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
if (reg_cxt->g_buf[i].pps_data) {
|
||||
ret = mpp_buffer_put(reg_cxt->g_buf[i].pps_data);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("h265d pps_data free buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -360,7 +360,7 @@ static MPP_RET hal_h265d_release_res(void *hal)
|
||||
|
||||
if (reg_cxt->g_buf[i].rps_data) {
|
||||
ret = mpp_buffer_put(reg_cxt->g_buf[i].rps_data);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("h265d rps_data free buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -374,14 +374,14 @@ static MPP_RET hal_h265d_release_res(void *hal)
|
||||
} else {
|
||||
if (reg_cxt->scaling_list_data) {
|
||||
ret = mpp_buffer_put(reg_cxt->scaling_list_data);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("h265d scaling_list_data free buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
if (reg_cxt->pps_data) {
|
||||
ret = mpp_buffer_put(reg_cxt->pps_data);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("h265d pps_data free buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -389,7 +389,7 @@ static MPP_RET hal_h265d_release_res(void *hal)
|
||||
|
||||
if (reg_cxt->rps_data) {
|
||||
ret = mpp_buffer_put(reg_cxt->rps_data);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("h265d rps_data free buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -433,40 +433,43 @@ MPP_RET hal_h265d_init(void *hal, MppHalCfg *cfg)
|
||||
return MPP_ERR_MALLOC;
|
||||
}
|
||||
reg_cxt->packet_slots = cfg->packet_slots;
|
||||
|
||||
///<- mpp_device_init
|
||||
#ifdef RKPLATFORM
|
||||
MppDevCfg dev_cfg = {
|
||||
.type = MPP_CTX_DEC, /* type */
|
||||
.coding = MPP_VIDEO_CodingHEVC, /* coding */
|
||||
.platform = 0, /* platform */
|
||||
.pp_enable = 0, /* pp_enable */
|
||||
};
|
||||
|
||||
ret = mpp_device_init(®_cxt->dev_ctx, &dev_cfg);
|
||||
if (ret) {
|
||||
mpp_err("mpp_device_init failed. ret: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (reg_cxt->group == NULL) {
|
||||
ret = mpp_buffer_group_get_internal(®_cxt->group, MPP_BUFFER_TYPE_ION);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("h265d mpp_buffer_group_get failed\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
ret = mpp_buffer_get(reg_cxt->group, ®_cxt->cabac_table_data, sizeof(cabac_table));
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("h265d cabac_table get buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = mpp_buffer_write(reg_cxt->cabac_table_data, 0, (void*)cabac_table, sizeof(cabac_table));
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("h265d write cabac_table data failed\n");
|
||||
return ret;
|
||||
}
|
||||
ret = hal_h265d_alloc_res(hal);
|
||||
|
||||
if (MPP_OK != ret) {
|
||||
ret = hal_h265d_alloc_res(hal);
|
||||
if (ret) {
|
||||
mpp_err("hal_h265d_alloc_res failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -485,17 +488,14 @@ MPP_RET hal_h265d_deinit(void *hal)
|
||||
h265d_reg_context_t *reg_cxt = (h265d_reg_context_t *)hal;
|
||||
|
||||
///<- mpp_device_init
|
||||
#ifdef RKPLATFORM
|
||||
if (reg_cxt->dev_ctx) {
|
||||
ret = mpp_device_deinit(reg_cxt->dev_ctx);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret)
|
||||
mpp_err("mpp_device_deinit failed. ret: %d\n", ret);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
ret = mpp_buffer_put(reg_cxt->cabac_table_data);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("h265d cabac_table free buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -512,7 +512,7 @@ MPP_RET hal_h265d_deinit(void *hal)
|
||||
|
||||
if (reg_cxt->group) {
|
||||
ret = mpp_buffer_group_put(reg_cxt->group);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("h265d group free buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -1100,31 +1100,27 @@ static RK_S32 hal_h265d_output_pps_packet(void *hal, void *dxva)
|
||||
RK_S32 fifo_len = 10;
|
||||
RK_S32 i, j;
|
||||
RK_U32 addr;
|
||||
RK_U64 *pps_packet = NULL;
|
||||
RK_U32 log2_min_cb_size;
|
||||
RK_S32 width, height;
|
||||
h265d_reg_context_t *reg_cxt = ( h265d_reg_context_t *)hal;
|
||||
h265d_dxva2_picture_context_t *dxva_cxt = (h265d_dxva2_picture_context_t*)dxva;
|
||||
BitputCtx_t bp;
|
||||
pps_packet = mpp_calloc(RK_U64, fifo_len + 1);
|
||||
RK_U64 *pps_packet = mpp_calloc(RK_U64, fifo_len + 1);
|
||||
|
||||
if (NULL == reg_cxt || dxva_cxt == NULL) {
|
||||
|
||||
mpp_err("%s:%s:%d reg_cxt or dxva_cxt is NULL",
|
||||
__FILE__, __FUNCTION__, __LINE__);
|
||||
MPP_FREE(pps_packet);
|
||||
return MPP_ERR_NULL_PTR;
|
||||
}
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
void *pps_ptr = mpp_buffer_get_ptr(reg_cxt->pps_data);
|
||||
if (NULL == pps_ptr) {
|
||||
|
||||
mpp_err("pps_data get ptr error");
|
||||
return MPP_ERR_NOMEM;
|
||||
}
|
||||
memset(pps_ptr, 0, 80 * 64);
|
||||
// pps_packet = (RK_U64 *)(pps_ptr + dxva_cxt->pp.pps_id * 80);
|
||||
#endif
|
||||
|
||||
|
||||
for (i = 0; i < 10; i++) pps_packet[i] = 0;
|
||||
|
||||
@@ -1300,27 +1296,23 @@ static RK_S32 hal_h265d_output_pps_packet(void *hal, void *dxva)
|
||||
|
||||
hal_h265d_output_scalinglist_packet(hal, ptr_scaling + addr, dxva);
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
RK_U32 fd = mpp_buffer_get_fd(reg_cxt->scaling_list_data);
|
||||
/* need to config addr */
|
||||
addr = fd | (addr << 10);
|
||||
#endif
|
||||
|
||||
mpp_put_bits(&bp, addr, 32);
|
||||
mpp_put_align(&bp, 64, 0xf);
|
||||
}
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
for (i = 0; i < 64; i++) {
|
||||
for (i = 0; i < 64; i++)
|
||||
memcpy(pps_ptr + i * 80, pps_packet, 80);
|
||||
}
|
||||
|
||||
#ifdef dump
|
||||
fwrite(pps_ptr, 1, 80 * 64, fp);
|
||||
fflush(fp);
|
||||
#endif
|
||||
#endif
|
||||
if (pps_packet != NULL) {
|
||||
mpp_free(pps_packet);
|
||||
}
|
||||
|
||||
MPP_FREE(pps_packet);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1336,11 +1328,8 @@ MPP_RET hal_h265d_gen_regs(void *hal, HalTaskInfo *syn)
|
||||
RK_S32 ret = MPP_SUCCESS;
|
||||
MppBuffer streambuf = NULL;
|
||||
RK_S32 aglin_offset = 0;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
RK_S32 valid_ref = -1;
|
||||
MppBuffer framebuf = NULL;
|
||||
#endif
|
||||
|
||||
h265d_dxva2_picture_context_t *dxva_cxt =
|
||||
(h265d_dxva2_picture_context_t *)syn->dec.syntax.data;
|
||||
@@ -1423,11 +1412,9 @@ MPP_RET hal_h265d_gen_regs(void *hal, HalTaskInfo *syn)
|
||||
hw_regs->sw_yuv_virstride
|
||||
= virstrid_yuv >> 4;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
mpp_buf_slot_get_prop(reg_cxt->slots, dxva_cxt->pp.CurrPic.Index7Bits,
|
||||
SLOT_BUFFER, &framebuf);
|
||||
hw_regs->sw_decout_base = mpp_buffer_get_fd(framebuf); //just index need map
|
||||
#endif
|
||||
|
||||
/*if out_base is equal to zero it means this frame may error
|
||||
we return directly add by csy*/
|
||||
@@ -1443,14 +1430,13 @@ MPP_RET hal_h265d_gen_regs(void *hal, HalTaskInfo *syn)
|
||||
if ( dxva_cxt->bitstream == NULL) {
|
||||
dxva_cxt->bitstream = mpp_buffer_get_ptr(streambuf);
|
||||
}
|
||||
|
||||
hal_h265d_slice_output_rps(syn->dec.syntax.data, rps_ptr);
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
hw_regs->sw_cabactbl_base = mpp_buffer_get_fd(reg_cxt->cabac_table_data);
|
||||
hw_regs->sw_pps_base = mpp_buffer_get_fd(reg_cxt->pps_data);
|
||||
hw_regs->sw_rps_base = mpp_buffer_get_fd(reg_cxt->rps_data);
|
||||
hw_regs->sw_strm_rlc_base = mpp_buffer_get_fd(streambuf);
|
||||
#endif
|
||||
|
||||
hw_regs->sw_stream_len = ((dxva_cxt->bitstream_size + 15)
|
||||
& (~15)) + 64;
|
||||
aglin_offset = hw_regs->sw_stream_len - dxva_cxt->bitstream_size;
|
||||
@@ -1470,7 +1456,6 @@ MPP_RET hal_h265d_gen_regs(void *hal, HalTaskInfo *syn)
|
||||
hw_regs->cabac_error_en = 0xfdfffffd;
|
||||
hw_regs->extern_error_en = 0x30000000;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
valid_ref = hw_regs->sw_decout_base;
|
||||
for (i = 0; i < (RK_S32)MPP_ARRAY_ELEMS(dxva_cxt->pp.RefPicList); i++) {
|
||||
if (dxva_cxt->pp.RefPicList[i].bPicEntry != 0xff &&
|
||||
@@ -1495,7 +1480,7 @@ MPP_RET hal_h265d_gen_regs(void *hal, HalTaskInfo *syn)
|
||||
hw_regs->sw_refer_base[1] |= (((hw_regs->sw_ref_valid >> 4) & 0xf) << 10);
|
||||
hw_regs->sw_refer_base[2] |= (((hw_regs->sw_ref_valid >> 8) & 0xf) << 10);
|
||||
hw_regs->sw_refer_base[3] |= (((hw_regs->sw_ref_valid >> 12) & 0x7) << 10);
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -1526,14 +1511,14 @@ MPP_RET hal_h265d_start(void *hal, HalTaskInfo *task)
|
||||
//mpp_log("RK_HEVC_DEC: regs[%02d]=%08X\n", i, *((RK_U32*)p));
|
||||
p += 4;
|
||||
}
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
// 68 is the nb of uint32_t
|
||||
ret = mpp_device_send_reg(reg_cxt->dev_ctx, (RK_U32*)hw_regs, RKVDEC_HEVC_REGISTERS);
|
||||
if (ret != 0) {
|
||||
if (ret) {
|
||||
mpp_err("RK_HEVC_DEC: ERROR: mpp_device_send_reg Failed!!!\n");
|
||||
return MPP_ERR_VPUHW;
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -1541,23 +1526,21 @@ MPP_RET hal_h265d_start(void *hal, HalTaskInfo *task)
|
||||
MPP_RET hal_h265d_wait(void *hal, HalTaskInfo *task)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
|
||||
(void)task;
|
||||
(void) hal;
|
||||
#ifdef RKPLATFORM
|
||||
RK_S32 index = task->dec.reg_index;
|
||||
h265d_reg_context_t *reg_cxt = (h265d_reg_context_t *)hal;
|
||||
RK_U8* p = NULL;
|
||||
H265d_REGS_t *hw_regs = NULL;
|
||||
RK_S32 i;
|
||||
|
||||
if (reg_cxt->fast_mode) {
|
||||
hw_regs = ( H265d_REGS_t *)reg_cxt->g_buf[index].hw_regs;
|
||||
} else {
|
||||
hw_regs = ( H265d_REGS_t *)reg_cxt->hw_regs;
|
||||
}
|
||||
p = (RK_U8*)hw_regs;
|
||||
ret = mpp_device_wait_reg(reg_cxt->dev_ctx, (RK_U32*)hw_regs, RKVDEC_HEVC_REGISTERS);
|
||||
|
||||
p = (RK_U8*)hw_regs;
|
||||
|
||||
ret = mpp_device_wait_reg(reg_cxt->dev_ctx, (RK_U32*)hw_regs, RKVDEC_HEVC_REGISTERS);
|
||||
if (hw_regs->sw_interrupt.sw_dec_error_sta
|
||||
|| hw_regs->sw_interrupt.sw_dec_empty_sta) {
|
||||
if (!reg_cxt->fast_mode) {
|
||||
@@ -1607,10 +1590,11 @@ MPP_RET hal_h265d_wait(void *hal, HalTaskInfo *task)
|
||||
}
|
||||
p += 4;
|
||||
}
|
||||
|
||||
if (reg_cxt->fast_mode) {
|
||||
reg_cxt->g_buf[index].use_flag = 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@@ -126,25 +126,25 @@ static MPP_RET hal_vp9d_alloc_res(hal_vp9_context_t *reg_cxt)
|
||||
reg_cxt->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(VP9_REGS));
|
||||
ret = mpp_buffer_get(reg_cxt->group,
|
||||
®_cxt->g_buf[i].probe_base, PROBE_SIZE);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("vp9 probe_base get buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
ret = mpp_buffer_get(reg_cxt->group,
|
||||
®_cxt->g_buf[i].count_base, COUNT_SIZE);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("vp9 count_base get buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
ret = mpp_buffer_get(reg_cxt->group,
|
||||
®_cxt->g_buf[i].segid_cur_base, MAX_SEGMAP_SIZE);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("vp9 segid_cur_base get buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
ret = mpp_buffer_get(reg_cxt->group,
|
||||
®_cxt->g_buf[i].segid_last_base, MAX_SEGMAP_SIZE);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("vp9 segid_last_base get buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -152,22 +152,22 @@ static MPP_RET hal_vp9d_alloc_res(hal_vp9_context_t *reg_cxt)
|
||||
} else {
|
||||
reg_cxt->hw_regs = mpp_calloc_size(void, sizeof(VP9_REGS));
|
||||
ret = mpp_buffer_get(reg_cxt->group, ®_cxt->probe_base, PROBE_SIZE);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("vp9 probe_base get buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
ret = mpp_buffer_get(reg_cxt->group, ®_cxt->count_base, COUNT_SIZE);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("vp9 count_base get buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
ret = mpp_buffer_get(reg_cxt->group, ®_cxt->segid_cur_base, MAX_SEGMAP_SIZE);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("vp9 segid_cur_base get buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
ret = mpp_buffer_get(reg_cxt->group, ®_cxt->segid_last_base, MAX_SEGMAP_SIZE);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("vp9 segid_last_base get buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -184,28 +184,28 @@ static MPP_RET hal_vp9d_release_res(hal_vp9_context_t *reg_cxt)
|
||||
for (i = 0; i < MAX_GEN_REG; i++) {
|
||||
if (reg_cxt->g_buf[i].probe_base) {
|
||||
ret = mpp_buffer_put(reg_cxt->g_buf[i].probe_base);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("vp9 probe_base put buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
if (reg_cxt->g_buf[i].count_base) {
|
||||
ret = mpp_buffer_put(reg_cxt->g_buf[i].count_base);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("vp9 count_base put buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
if (reg_cxt->g_buf[i].segid_cur_base) {
|
||||
ret = mpp_buffer_put(reg_cxt->g_buf[i].segid_cur_base);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("vp9 segid_cur_base put buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
if (reg_cxt->g_buf[i].segid_last_base) {
|
||||
ret = mpp_buffer_put(reg_cxt->g_buf[i].segid_last_base);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("vp9 segid_last_base put buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -218,28 +218,28 @@ static MPP_RET hal_vp9d_release_res(hal_vp9_context_t *reg_cxt)
|
||||
} else {
|
||||
if (reg_cxt->probe_base) {
|
||||
ret = mpp_buffer_put(reg_cxt->probe_base);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("vp9 probe_base get buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
if (reg_cxt->count_base) {
|
||||
ret = mpp_buffer_put(reg_cxt->count_base);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("vp9 count_base put buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
if (reg_cxt->segid_cur_base) {
|
||||
ret = mpp_buffer_put(reg_cxt->segid_cur_base);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("vp9 segid_cur_base put buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
if (reg_cxt->segid_last_base) {
|
||||
ret = mpp_buffer_put(reg_cxt->segid_last_base);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("vp9 segid_last_base put buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -279,35 +279,29 @@ MPP_RET hal_vp9d_init(void *hal, MppHalCfg *cfg)
|
||||
reg_cxt->packet_slots = cfg->packet_slots;
|
||||
|
||||
///<- mpp_device_init
|
||||
#ifdef RKPLATFORM
|
||||
MppDevCfg dev_cfg = {
|
||||
.type = MPP_CTX_DEC, /* type */
|
||||
.coding = MPP_VIDEO_CodingVP9, /* coding */
|
||||
.platform = 0, /* platform */
|
||||
.pp_enable = 0, /* pp_enable */
|
||||
};
|
||||
|
||||
ret = mpp_device_init(®_cxt->dev_ctx, &dev_cfg);
|
||||
if (ret) {
|
||||
mpp_err("mpp_device_init failed. ret: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif
|
||||
if (reg_cxt->group == NULL) {
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
mpp_err("mpp_buffer_group_get_internal used ion in");
|
||||
ret = mpp_buffer_group_get_internal(®_cxt->group, MPP_BUFFER_TYPE_ION);
|
||||
#else
|
||||
ret = mpp_buffer_group_get_internal(®_cxt->group, MPP_BUFFER_TYPE_NORMAL);
|
||||
#endif
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("vp9 mpp_buffer_group_get failed\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
ret = hal_vp9d_alloc_res(reg_cxt);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("hal_vp9d_alloc_res failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -337,19 +331,19 @@ MPP_RET hal_vp9d_deinit(void *hal)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
hal_vp9_context_t *reg_cxt = (hal_vp9_context_t *)hal;
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
if (reg_cxt->dev_ctx) {
|
||||
ret = mpp_device_deinit(reg_cxt->dev_ctx);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("mpp_device_deinit failed. ret: %d\n", ret);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
hal_vp9d_release_res(reg_cxt);
|
||||
|
||||
if (reg_cxt->group) {
|
||||
ret = mpp_buffer_group_put(reg_cxt->group);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("vp9d group free buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -367,18 +361,14 @@ MPP_RET hal_vp9d_output_probe(void *hal, void *dxva)
|
||||
RK_S32 intraFlag = (!pic_param->frame_type || pic_param->intra_only);
|
||||
vp9_prob partition_probs[PARTITION_CONTEXTS][PARTITION_TYPES - 1];
|
||||
vp9_prob uv_mode_prob[INTRA_MODES][INTRA_MODES - 1];
|
||||
#ifdef RKPLATFORM
|
||||
hal_vp9_context_t *reg_cxt = (hal_vp9_context_t*)hal;
|
||||
void *probe_ptr = mpp_buffer_get_ptr(reg_cxt->probe_base);
|
||||
if (NULL == probe_ptr) {
|
||||
|
||||
mpp_err("probe_ptr get ptr error");
|
||||
return MPP_ERR_NOMEM;
|
||||
}
|
||||
|
||||
memset(probe_ptr, 0, 304 * 8);
|
||||
#else
|
||||
(void)hal;
|
||||
#endif
|
||||
|
||||
if (intraFlag) {
|
||||
memcpy(partition_probs, vp9_kf_partition_probs, sizeof(partition_probs));
|
||||
@@ -596,9 +586,9 @@ MPP_RET hal_vp9d_output_probe(void *hal, void *dxva)
|
||||
}
|
||||
mpp_put_align(&bp, 128, 0);
|
||||
}
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
memcpy(probe_ptr, probe_packet, 304 * 8);
|
||||
#endif
|
||||
|
||||
#ifdef dump
|
||||
if (intraFlag) {
|
||||
fwrite(probe_packet, 1, 302 * 8, vp9_fp);
|
||||
@@ -695,19 +685,15 @@ MPP_RET hal_vp9d_gen_regs(void *hal, HalTaskInfo *task)
|
||||
RK_U32 sw_yuv_virstride ;
|
||||
RK_U8 ref_idx = 0;
|
||||
RK_U32 *reg_ref_base = 0;
|
||||
RK_S32 intraFlag = 0;
|
||||
MppBuffer framebuf = NULL;
|
||||
|
||||
#ifdef dump
|
||||
char filename[20] = "data/probe";
|
||||
char filename1[20] = "data/count";
|
||||
#endif
|
||||
RK_S32 intraFlag = 0;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
MppBuffer framebuf = NULL;
|
||||
#endif
|
||||
#ifdef dump
|
||||
if (vp9_fp != NULL) {
|
||||
fclose(vp9_fp);
|
||||
|
||||
}
|
||||
if (vp9_fp1 != NULL) {
|
||||
fclose(vp9_fp1);
|
||||
@@ -775,7 +761,6 @@ MPP_RET hal_vp9d_gen_regs(void *hal, HalTaskInfo *task)
|
||||
vp9_hw_regs->swreg8_y_virstride.sw_y_virstride = sw_y_virstride;
|
||||
vp9_hw_regs->swreg9_yuv_virstride.sw_yuv_virstride = sw_yuv_virstride;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (!pic_param->intra_only && pic_param->frame_type && !pic_param->error_resilient_mode) {
|
||||
reg_cxt->pre_mv_base_addr = reg_cxt->mv_base_addr;
|
||||
}
|
||||
@@ -809,7 +794,6 @@ MPP_RET hal_vp9d_gen_regs(void *hal, HalTaskInfo *task)
|
||||
reg_cxt->pre_mv_base_addr = reg_cxt->mv_base_addr;
|
||||
}
|
||||
vp9_hw_regs->swreg52_vp9_refcolmv_base = reg_cxt->pre_mv_base_addr;
|
||||
#endif
|
||||
|
||||
vp9_hw_regs->swreg10_vp9_cprheader_offset.sw_vp9_cprheader_offset = 0; //no use now.
|
||||
reg_ref_base = &vp9_hw_regs->swreg11_vp9_referlast_base;
|
||||
@@ -824,11 +808,11 @@ MPP_RET hal_vp9d_gen_regs(void *hal, HalTaskInfo *task)
|
||||
y_virstride = y_hor_virstride * pic_h[0];
|
||||
uv_virstride = uv_hor_virstride * pic_h[1];
|
||||
yuv_virstride = y_virstride + uv_virstride;
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
if (pic_param->ref_frame_map[ref_idx].Index7Bits < 0x7f) {
|
||||
mpp_buf_slot_get_prop(reg_cxt->slots, pic_param->ref_frame_map[ref_idx].Index7Bits, SLOT_BUFFER, &framebuf);
|
||||
}
|
||||
#endif
|
||||
|
||||
if (pic_param->ref_frame_map[ref_idx].Index7Bits < 0x7f) {
|
||||
switch (i) {
|
||||
case 0: {
|
||||
@@ -861,7 +845,7 @@ MPP_RET hal_vp9d_gen_regs(void *hal, HalTaskInfo *task)
|
||||
break;
|
||||
|
||||
}
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
/*0 map to 11*/
|
||||
/*1 map to 12*/
|
||||
/*2 map to 13*/
|
||||
@@ -871,7 +855,6 @@ MPP_RET hal_vp9d_gen_regs(void *hal, HalTaskInfo *task)
|
||||
mpp_log("ref buff address is no valid used out as base slot index 0x%x", pic_param->ref_frame_map[ref_idx].Index7Bits);
|
||||
reg_ref_base[i] = vp9_hw_regs->swreg7_decout_base; //set
|
||||
}
|
||||
#endif
|
||||
} else {
|
||||
reg_ref_base[i] = vp9_hw_regs->swreg7_decout_base; //set
|
||||
}
|
||||
@@ -1002,15 +985,12 @@ MPP_RET hal_vp9d_start(void *hal, HalTaskInfo *task)
|
||||
//mpp_log("RK_VP9_DEC: regs[%02d]=%08X\n", i, *((RK_U32*)p));
|
||||
p += 4;
|
||||
}
|
||||
#ifdef RKPLATFORM
|
||||
#if 1
|
||||
|
||||
ret = mpp_device_send_reg(reg_cxt->dev_ctx, (RK_U32*)hw_regs, sizeof(VP9_REGS) / 4); // 68 is the nb of uint32_t
|
||||
if (ret != 0) {
|
||||
if (ret) {
|
||||
mpp_err("VP9H_DBG_REG: ERROR: mpp_device_send_reg Failed!!!\n");
|
||||
return MPP_ERR_VPUHW;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
(void)task;
|
||||
return ret;
|
||||
@@ -1025,10 +1005,10 @@ MPP_RET hal_vp9d_start(void *hal, HalTaskInfo *task)
|
||||
MPP_RET hal_vp9d_wait(void *hal, HalTaskInfo *task)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
#ifdef RKPLATFORM
|
||||
hal_vp9_context_t *reg_cxt = (hal_vp9_context_t *)hal;
|
||||
RK_U32 i;
|
||||
VP9_REGS *hw_regs = NULL;
|
||||
|
||||
if (reg_cxt->fast_mode) {
|
||||
hw_regs = (VP9_REGS *)reg_cxt->g_buf[task->dec.reg_index].hw_regs;
|
||||
} else {
|
||||
@@ -1037,13 +1017,12 @@ MPP_RET hal_vp9d_wait(void *hal, HalTaskInfo *task)
|
||||
|
||||
ret = mpp_device_wait_reg(reg_cxt->dev_ctx, (RK_U32*)hw_regs, sizeof(VP9_REGS) / 4);
|
||||
|
||||
RK_U8 *p = (RK_U8*)hw_regs;
|
||||
RK_U32 *p = (RK_U32*)hw_regs;
|
||||
for (i = 0; i < sizeof(VP9_REGS) / 4; i++) {
|
||||
if (i == 1) {
|
||||
vp9h_dbg(VP9H_DBG_REG, "RK_VP9_DEC: regs[%02d]=%08X\n", i, *((RK_U32*)p));
|
||||
vp9h_dbg(VP9H_DBG_REG, "RK_VP9_DEC: regs[%02d]=%08X\n", i, p[i]);
|
||||
// mpp_log("RK_VP9_DEC: regs[%02d]=%08X\n", i, *((RK_U32*)p));
|
||||
}
|
||||
p += 4;
|
||||
}
|
||||
|
||||
if (task->dec.flags.parse_err ||
|
||||
@@ -1062,9 +1041,7 @@ MPP_RET hal_vp9d_wait(void *hal, HalTaskInfo *task)
|
||||
if (reg_cxt->fast_mode) {
|
||||
reg_cxt->g_buf[task->dec.reg_index].use_flag = 0;
|
||||
}
|
||||
#else
|
||||
(void)hal;
|
||||
#endif
|
||||
|
||||
(void)task;
|
||||
return ret;
|
||||
}
|
||||
|
@@ -206,7 +206,7 @@ h264e_rkv_allocate_buffers(H264eHalContext *ctx, H264eHwCfg *hw_cfg)
|
||||
for (k = 0; k < 2; k++) {
|
||||
ret = mpp_buffer_get(buffers->hw_buf_grp[H264E_HAL_RKV_BUF_GRP_PP],
|
||||
&buffers->hw_pp_buf[k], frame_size);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
h264e_hal_err("hw_pp_buf[%d] get failed", k);
|
||||
return ret;
|
||||
}
|
||||
@@ -216,7 +216,7 @@ h264e_rkv_allocate_buffers(H264eHalContext *ctx, H264eHwCfg *hw_cfg)
|
||||
for (k = 0; k < 2; k++) {
|
||||
ret = mpp_buffer_get(buffers->hw_buf_grp[H264E_HAL_RKV_BUF_GRP_DSP],
|
||||
&buffers->hw_dsp_buf[k], frame_size / 16);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
h264e_hal_err("hw_dsp_buf[%d] get failed", k);
|
||||
return ret;
|
||||
}
|
||||
@@ -238,7 +238,7 @@ h264e_rkv_allocate_buffers(H264eHalContext *ctx, H264eHwCfg *hw_cfg)
|
||||
for (k = 0; k < RKV_H264E_LINKTABLE_FRAME_NUM; k++) {
|
||||
ret = mpp_buffer_get(buffers->hw_buf_grp[H264E_HAL_RKV_BUF_GRP_ROI],
|
||||
&buffers->hw_roi_buf[k], num_mbs_oneframe * 1);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
h264e_hal_err("hw_roi_buf[%d] get failed", k);
|
||||
return ret;
|
||||
}
|
||||
@@ -250,7 +250,7 @@ h264e_rkv_allocate_buffers(H264eHalContext *ctx, H264eHwCfg *hw_cfg)
|
||||
for (k = 0; k < num_buf; k++) {
|
||||
ret = mpp_buffer_get(buffers->hw_buf_grp[H264E_HAL_RKV_BUF_GRP_REC],
|
||||
&buffers->hw_rec_buf[k], frame_size);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
h264e_hal_err("hw_rec_buf[%d] get failed", k);
|
||||
return ret;
|
||||
}
|
||||
@@ -336,7 +336,6 @@ MPP_RET hal_h264e_rkv_init(void *hal, MppHalCfg *cfg)
|
||||
dpb_ctx->i_frame_cnt = 0;
|
||||
dpb_ctx->i_frame_num = 0;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
MppDevCfg dev_cfg = {
|
||||
.type = MPP_CTX_ENC, /* type */
|
||||
.coding = MPP_VIDEO_CodingAVC, /* coding */
|
||||
@@ -348,7 +347,6 @@ MPP_RET hal_h264e_rkv_init(void *hal, MppHalCfg *cfg)
|
||||
h264e_hal_err("mpp_device_init failed. ret: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
buffers = (h264e_hal_rkv_buffers *)ctx->buffers;
|
||||
for (k = 0; k < H264E_HAL_RKV_BUF_GRP_BUTT; k++) {
|
||||
@@ -426,14 +424,11 @@ MPP_RET hal_h264e_rkv_deinit(void *hal)
|
||||
ctx->inter_qs = NULL;
|
||||
}
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (ctx->dev_ctx) {
|
||||
ret = mpp_device_deinit(ctx->dev_ctx);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret)
|
||||
h264e_hal_err("mpp_device_deinit failed. ret: %d\n", ret);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
h264e_hal_leave();
|
||||
return MPP_OK;
|
||||
@@ -1496,19 +1491,13 @@ MPP_RET hal_h264e_rkv_start(void *hal, HalTaskInfo *task)
|
||||
|
||||
ctx->frame_cnt_send_ready ++;
|
||||
|
||||
(void)task;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
h264e_hal_dbg(H264E_DBG_DETAIL, "vpu client is sending %d regs", length);
|
||||
if (MPP_OK != mpp_device_send_reg(ctx->dev_ctx, (RK_U32 *)ioctl_info, length)) {
|
||||
if (mpp_device_send_reg(ctx->dev_ctx, (RK_U32 *)ioctl_info, length)) {
|
||||
h264e_hal_err("mpp_device_send_reg Failed!!!");
|
||||
return MPP_ERR_VPUHW;
|
||||
} else {
|
||||
h264e_hal_dbg(H264E_DBG_DETAIL, "mpp_device_send_reg successfully!");
|
||||
}
|
||||
#else
|
||||
(void)length;
|
||||
#endif
|
||||
|
||||
h264e_hal_leave();
|
||||
|
||||
@@ -1605,8 +1594,8 @@ static MPP_RET h264e_rkv_resend(H264eHalContext *ctx, RK_S32 mb_rc)
|
||||
sizeof(ioctl_info->reg_info[0]) *
|
||||
ioctl_info->frame_num) >> 2;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (mpp_device_send_reg(ctx->dev_ctx, (RK_U32 *)ioctl_info, length)) {
|
||||
hw_ret = mpp_device_send_reg(ctx->dev_ctx, (RK_U32 *)ioctl_info, length);
|
||||
if (hw_ret) {
|
||||
h264e_hal_err("mpp_device_send_reg Failed!!!");
|
||||
return MPP_ERR_VPUHW;
|
||||
} else {
|
||||
@@ -1614,8 +1603,7 @@ static MPP_RET h264e_rkv_resend(H264eHalContext *ctx, RK_S32 mb_rc)
|
||||
}
|
||||
|
||||
hw_ret = mpp_device_wait_reg(ctx->dev_ctx, (RK_U32 *)reg_out, length);
|
||||
#endif
|
||||
if (hw_ret != MPP_OK) {
|
||||
if (hw_ret) {
|
||||
h264e_hal_err("hardware returns error:%d", hw_ret);
|
||||
return MPP_ERR_VPUHW;
|
||||
}
|
||||
@@ -1674,7 +1662,6 @@ MPP_RET hal_h264e_rkv_wait(void *hal, HalTaskInfo *task)
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
h264e_hal_dbg(H264E_DBG_DETAIL, "mpp_device_wait_reg expect length %d\n",
|
||||
length);
|
||||
|
||||
@@ -1686,9 +1673,6 @@ MPP_RET hal_h264e_rkv_wait(void *hal, HalTaskInfo *task)
|
||||
h264e_hal_err("hardware returns error:%d", hw_ret);
|
||||
return MPP_ERR_VPUHW;
|
||||
}
|
||||
#else
|
||||
(void)hw_ret;
|
||||
#endif
|
||||
|
||||
h264e_rkv_set_feedback(ctx, reg_out, enc_task);
|
||||
|
||||
|
@@ -28,15 +28,14 @@ MPP_RET h264e_rkv_set_osd_plt(H264eHalContext *ctx, void *param)
|
||||
h264e_hal_enter();
|
||||
|
||||
if (plt->buf) {
|
||||
MPP_RET ret = mpp_device_send_reg_with_id(ctx->dev_ctx,
|
||||
H264E_IOC_SET_OSD_PLT,
|
||||
param, sizeof(MppEncOSDPlt));
|
||||
ctx->osd_plt_type = H264E_OSD_PLT_TYPE_USERDEF;
|
||||
#ifdef RKPLATFORM
|
||||
if (MPP_OK != mpp_device_send_reg_with_id(ctx->dev_ctx,
|
||||
H264E_IOC_SET_OSD_PLT, param,
|
||||
sizeof(MppEncOSDPlt))) {
|
||||
if (ret) {
|
||||
h264e_hal_err("set osd plt error");
|
||||
return MPP_NOK;
|
||||
}
|
||||
#endif
|
||||
} else {
|
||||
ctx->osd_plt_type = H264E_OSD_PLT_TYPE_DEFAULT;
|
||||
}
|
||||
|
@@ -133,7 +133,6 @@ MPP_RET hal_vpu1_h263d_init(void *hal, MppHalCfg *cfg)
|
||||
goto ERR_RET;
|
||||
}
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
MppDevCfg dev_cfg = {
|
||||
.type = MPP_CTX_DEC, /* type */
|
||||
.coding = MPP_VIDEO_CodingH263, /* coding */
|
||||
@@ -146,7 +145,6 @@ MPP_RET hal_vpu1_h263d_init(void *hal, MppHalCfg *cfg)
|
||||
ret = MPP_ERR_UNKNOW;
|
||||
goto ERR_RET;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* basic register configuration setup here
|
||||
@@ -194,12 +192,9 @@ MPP_RET hal_vpu1_h263d_deinit(void *hal)
|
||||
ctx->regs = NULL;
|
||||
}
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
ret = mpp_device_deinit(ctx->dev_ctx);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret)
|
||||
mpp_err("mpp_device_deinit failed ret: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
@@ -239,21 +234,20 @@ MPP_RET hal_vpu1_h263d_gen_regs(void *hal, HalTaskInfo *syn)
|
||||
MPP_RET hal_vpu1_h263d_start(void *hal, HalTaskInfo *task)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
#ifdef RKPLATFORM
|
||||
hal_h263_ctx *ctx = (hal_h263_ctx *)hal;
|
||||
RK_U32 reg_count = (sizeof(*(Vpu1H263dRegSet_t*)ctx->regs) / sizeof(RK_U32));
|
||||
RK_U32* regs = (RK_U32 *)ctx->regs;
|
||||
|
||||
if (h263d_hal_debug & H263D_HAL_DBG_REG_PUT) {
|
||||
RK_U32 i = 0;
|
||||
|
||||
for (i = 0; i < reg_count; i++) {
|
||||
mpp_log("reg[%03d]: %08x\n", i, regs[i]);
|
||||
}
|
||||
}
|
||||
|
||||
ret = mpp_device_send_reg(ctx->dev_ctx, regs, reg_count);
|
||||
#endif
|
||||
(void)hal;
|
||||
|
||||
(void)task;
|
||||
return ret;
|
||||
}
|
||||
@@ -261,7 +255,6 @@ MPP_RET hal_vpu1_h263d_start(void *hal, HalTaskInfo *task)
|
||||
MPP_RET hal_vpu1_h263d_wait(void *hal, HalTaskInfo *task)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
#ifdef RKPLATFORM
|
||||
hal_h263_ctx *ctx = (hal_h263_ctx *)hal;
|
||||
Vpu1H263dRegSet_t reg_out;
|
||||
RK_U32* regs = (RK_U32 *)®_out;
|
||||
@@ -276,8 +269,7 @@ MPP_RET hal_vpu1_h263d_wait(void *hal, HalTaskInfo *task)
|
||||
mpp_log("reg[%03d]: %08x\n", i, regs[i]);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
(void)hal;
|
||||
|
||||
(void)task;
|
||||
return ret;
|
||||
}
|
||||
|
@@ -133,20 +133,19 @@ MPP_RET hal_vpu2_h263d_init(void *hal, MppHalCfg *cfg)
|
||||
goto ERR_RET;
|
||||
}
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
MppDevCfg dev_cfg = {
|
||||
.type = MPP_CTX_DEC, /* type */
|
||||
.coding = MPP_VIDEO_CodingH263, /* coding */
|
||||
.platform = 0, /* platform */
|
||||
.pp_enable = 0, /* pp_enable */
|
||||
};
|
||||
|
||||
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);
|
||||
if (ret != MPP_OK) {
|
||||
if (ret) {
|
||||
mpp_err_f("mpp_device_init failed. ret: %d\n", ret);
|
||||
ret = MPP_ERR_UNKNOW;
|
||||
goto ERR_RET;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* basic register configuration setup here
|
||||
@@ -194,12 +193,9 @@ MPP_RET hal_vpu2_h263d_deinit(void *hal)
|
||||
ctx->regs = NULL;
|
||||
}
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
ret = mpp_device_deinit(ctx->dev_ctx);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret)
|
||||
mpp_err("mpp_device_deinit failed ret: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
@@ -239,7 +235,6 @@ MPP_RET hal_vpu2_h263d_gen_regs(void *hal, HalTaskInfo *syn)
|
||||
MPP_RET hal_vpu2_h263d_start(void *hal, HalTaskInfo *task)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
#ifdef RKPLATFORM
|
||||
hal_h263_ctx *ctx = (hal_h263_ctx *)hal;
|
||||
RK_U32 reg_count = (sizeof(*(Vpu2H263dRegSet_t*)ctx->regs) / sizeof(RK_U32));
|
||||
RK_U32* regs = (RK_U32 *)ctx->regs;
|
||||
@@ -252,8 +247,7 @@ MPP_RET hal_vpu2_h263d_start(void *hal, HalTaskInfo *task)
|
||||
}
|
||||
|
||||
ret = mpp_device_send_reg(ctx->dev_ctx, regs, reg_count);
|
||||
#endif
|
||||
(void)hal;
|
||||
|
||||
(void)task;
|
||||
return ret;
|
||||
}
|
||||
@@ -261,7 +255,6 @@ MPP_RET hal_vpu2_h263d_start(void *hal, HalTaskInfo *task)
|
||||
MPP_RET hal_vpu2_h263d_wait(void *hal, HalTaskInfo *task)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
#ifdef RKPLATFORM
|
||||
hal_h263_ctx *ctx = (hal_h263_ctx *)hal;
|
||||
Vpu2H263dRegSet_t reg_out;
|
||||
RK_U32* regs = (RK_U32 *)®_out;
|
||||
@@ -276,8 +269,7 @@ MPP_RET hal_vpu2_h263d_wait(void *hal, HalTaskInfo *task)
|
||||
mpp_log("reg[%03d]: %08x\n", i, regs[i]);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
(void)hal;
|
||||
|
||||
(void)task;
|
||||
return ret;
|
||||
}
|
||||
|
@@ -53,19 +53,19 @@ MPP_RET hal_h264e_vepu1_init(void *hal, MppHalCfg *cfg)
|
||||
|
||||
h264e_vpu_init_extra_info(ctx->extra_info);
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
MppDevCfg dev_cfg = {
|
||||
.type = MPP_CTX_ENC, /* type */
|
||||
.coding = MPP_VIDEO_CodingAVC, /* coding */
|
||||
.platform = 0, /* platform */
|
||||
.pp_enable = 0, /* pp_enable */
|
||||
};
|
||||
|
||||
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);
|
||||
if (ret != MPP_OK) {
|
||||
if (ret) {
|
||||
mpp_err("mpp_device_init failed. ret: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
ctx->hw_cfg.qp_prev = ctx->cfg->codec.h264.qp_init;
|
||||
mpp_env_get_u32("hal_vpu_h264e_debug", &hal_vpu_h264e_debug, 0);
|
||||
|
||||
@@ -127,12 +127,9 @@ MPP_RET hal_h264e_vepu1_deinit(void *hal)
|
||||
ctx->qp_p = NULL;
|
||||
}
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
ret = mpp_device_deinit(ctx->dev_ctx);
|
||||
if (ret) {
|
||||
if (ret)
|
||||
mpp_err("mpp_device_deinit failed ret: %d", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
h264e_hal_leave();
|
||||
return ret;
|
||||
@@ -432,7 +429,7 @@ MPP_RET hal_h264e_vepu1_start(void *hal, HalTaskInfo *task)
|
||||
H264eHalContext *ctx = (H264eHalContext *)hal;
|
||||
(void)task;
|
||||
h264e_hal_enter();
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
if (ctx->dev_ctx) {
|
||||
RK_U32 *p_regs = (RK_U32 *)ctx->regs;
|
||||
h264e_hal_dbg(H264E_DBG_DETAIL, "vpu client is sending %d regs",
|
||||
@@ -448,8 +445,7 @@ MPP_RET hal_h264e_vepu1_start(void *hal, HalTaskInfo *task)
|
||||
mpp_err("invalid device ctx: %p", ctx->dev_ctx);
|
||||
return MPP_NOK;
|
||||
}
|
||||
#endif
|
||||
(void)ctx;
|
||||
|
||||
h264e_hal_leave();
|
||||
|
||||
return MPP_OK;
|
||||
@@ -491,7 +487,7 @@ static MPP_RET hal_h264e_vpu1_resend(H264eHalContext *ctx, RK_U32 *reg_out, RK_S
|
||||
| VEPU_REG_H264_CHKPT_DISTANCE(hw_cfg->cp_distance_mbs);
|
||||
|
||||
H264E_HAL_SET_REG(p_regs, VEPU_REG_QP_VAL, val);
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
hw_ret = mpp_device_send_reg(ctx->dev_ctx, p_regs, VEPU_H264E_VEPU1_NUM_REGS);
|
||||
if (hw_ret)
|
||||
mpp_err("mpp_device_send_reg failed ret %d", hw_ret);
|
||||
@@ -499,11 +495,11 @@ static MPP_RET hal_h264e_vpu1_resend(H264eHalContext *ctx, RK_U32 *reg_out, RK_S
|
||||
h264e_hal_dbg(H264E_DBG_DETAIL, "mpp_device_send_reg success!");
|
||||
|
||||
hw_ret = mpp_device_wait_reg(ctx->dev_ctx, (RK_U32 *)reg_out, VEPU_H264E_VEPU1_NUM_REGS);
|
||||
#endif
|
||||
if (hw_ret != MPP_OK) {
|
||||
if (hw_ret) {
|
||||
h264e_hal_err("hardware returns error:%d", hw_ret);
|
||||
return MPP_ERR_VPUHW;
|
||||
}
|
||||
|
||||
return MPP_OK;
|
||||
}
|
||||
|
||||
@@ -523,7 +519,6 @@ MPP_RET hal_h264e_vepu1_wait(void *hal, HalTaskInfo *task)
|
||||
|
||||
h264e_hal_enter();
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (ctx->dev_ctx) {
|
||||
RK_S32 hw_ret = mpp_device_wait_reg(ctx->dev_ctx, (RK_U32 *)reg_out,
|
||||
VEPU_H264E_VEPU1_NUM_REGS);
|
||||
@@ -538,7 +533,6 @@ MPP_RET hal_h264e_vepu1_wait(void *hal, HalTaskInfo *task)
|
||||
mpp_err("invalid device ctx: %p", ctx->dev_ctx);
|
||||
return MPP_NOK;
|
||||
}
|
||||
#endif
|
||||
|
||||
hal_h264e_vepu1_set_feedback(fb, reg_out);
|
||||
task->enc.length = fb->out_strm_size;
|
||||
|
@@ -53,7 +53,6 @@ MPP_RET hal_h264e_vepu2_init(void *hal, MppHalCfg *cfg)
|
||||
|
||||
h264e_vpu_init_extra_info(ctx->extra_info);
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
MppDevCfg dev_cfg = {
|
||||
.type = MPP_CTX_ENC, /* type */
|
||||
.coding = MPP_VIDEO_CodingAVC, /* coding */
|
||||
@@ -65,7 +64,7 @@ MPP_RET hal_h264e_vepu2_init(void *hal, MppHalCfg *cfg)
|
||||
mpp_err("mpp_device_init failed. ret: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
ctx->hw_cfg.qp_prev = ctx->cfg->codec.h264.qp_init;
|
||||
mpp_env_get_u32("hal_vpu_h264e_debug", &hal_vpu_h264e_debug, 0);
|
||||
|
||||
@@ -123,12 +122,9 @@ MPP_RET hal_h264e_vepu2_deinit(void *hal)
|
||||
ctx->mad = NULL;
|
||||
}
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
ret = mpp_device_deinit(ctx->dev_ctx);
|
||||
if (ret) {
|
||||
if (ret)
|
||||
mpp_err("mpp_device_deinit failed, ret: %d", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
h264e_hal_leave();
|
||||
return ret;
|
||||
@@ -459,7 +455,7 @@ MPP_RET hal_h264e_vepu2_start(void *hal, HalTaskInfo *task)
|
||||
(void)task;
|
||||
|
||||
h264e_hal_enter();
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
if (ctx->dev_ctx) {
|
||||
RK_U32 *p_regs = (RK_U32 *)ctx->regs;
|
||||
h264e_hal_dbg(H264E_DBG_DETAIL, "vpu client is sending %d regs", VEPU2_H264E_NUM_REGS);
|
||||
@@ -472,9 +468,7 @@ MPP_RET hal_h264e_vepu2_start(void *hal, HalTaskInfo *task)
|
||||
mpp_err("invalid device ctx: %p", ctx->dev_ctx);
|
||||
ret = MPP_NOK;
|
||||
}
|
||||
#else
|
||||
(void)ctx;
|
||||
#endif
|
||||
|
||||
h264e_hal_leave();
|
||||
|
||||
return ret;
|
||||
@@ -518,7 +512,7 @@ static MPP_RET hal_h264e_vpu2_resend(H264eHalContext *ctx, RK_U32 *reg_out, RK_S
|
||||
| VEPU_REG_H264_CHKPT_DISTANCE(hw_cfg->cp_distance_mbs);
|
||||
|
||||
H264E_HAL_SET_REG(p_regs, VEPU_REG_QP_VAL, val);
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
hw_ret = mpp_device_send_reg(ctx->dev_ctx, p_regs, VEPU2_H264E_NUM_REGS);
|
||||
if (hw_ret)
|
||||
mpp_err("mpp_device_send_reg failed ret %d", hw_ret);
|
||||
@@ -526,8 +520,7 @@ static MPP_RET hal_h264e_vpu2_resend(H264eHalContext *ctx, RK_U32 *reg_out, RK_S
|
||||
h264e_hal_dbg(H264E_DBG_DETAIL, "mpp_device_send_reg success!");
|
||||
|
||||
hw_ret = mpp_device_wait_reg(ctx->dev_ctx, (RK_U32 *)reg_out, VEPU2_H264E_NUM_REGS);
|
||||
#endif
|
||||
if (hw_ret != MPP_OK) {
|
||||
if (hw_ret) {
|
||||
h264e_hal_err("hardware returns error:%d", hw_ret);
|
||||
return MPP_ERR_VPUHW;
|
||||
}
|
||||
@@ -549,7 +542,6 @@ MPP_RET hal_h264e_vepu2_wait(void *hal, HalTaskInfo *task)
|
||||
memset(reg_out, 0, sizeof(H264eVpu2RegSet));
|
||||
h264e_hal_enter();
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (ctx->dev_ctx) {
|
||||
RK_S32 hw_ret = mpp_device_wait_reg(ctx->dev_ctx, (RK_U32 *)reg_out,
|
||||
VEPU2_H264E_NUM_REGS);
|
||||
@@ -564,7 +556,6 @@ MPP_RET hal_h264e_vepu2_wait(void *hal, HalTaskInfo *task)
|
||||
mpp_err("invalid device ctx: %p", ctx->dev_ctx);
|
||||
return MPP_NOK;
|
||||
}
|
||||
#endif
|
||||
|
||||
h264e_vpu_set_feedback(fb, reg_out);
|
||||
|
||||
|
@@ -769,7 +769,6 @@ MPP_RET hal_jpegd_vdpu1_init(void *hal, MppHalCfg *cfg)
|
||||
JpegHalCtx->frame_slots = cfg->frame_slots;
|
||||
|
||||
//get vpu socket
|
||||
#ifdef RKPLATFORM
|
||||
MppDevCfg dev_cfg = {
|
||||
.type = MPP_CTX_DEC, /* type */
|
||||
.coding = MPP_VIDEO_CodingMJPEG, /* coding */
|
||||
@@ -781,7 +780,6 @@ MPP_RET hal_jpegd_vdpu1_init(void *hal, MppHalCfg *cfg)
|
||||
mpp_err("mpp_device_init failed. ret: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* allocate regs buffer */
|
||||
if (JpegHalCtx->regs == NULL) {
|
||||
@@ -802,31 +800,25 @@ MPP_RET hal_jpegd_vdpu1_init(void *hal, MppHalCfg *cfg)
|
||||
|
||||
//malloc hw buf
|
||||
if (JpegHalCtx->group == NULL) {
|
||||
#ifdef RKPLATFORM
|
||||
jpegd_dbg_hal("mpp_buffer_group_get_internal used ion in");
|
||||
ret = mpp_buffer_group_get_internal(&JpegHalCtx->group,
|
||||
MPP_BUFFER_TYPE_ION);
|
||||
#else
|
||||
ret = mpp_buffer_group_get_internal(&JpegHalCtx->group,
|
||||
MPP_BUFFER_TYPE_NORMAL);
|
||||
#endif
|
||||
if (MPP_OK != ret) {
|
||||
mpp_err_f("mpp_buffer_group_get failed\n");
|
||||
if (ret) {
|
||||
mpp_err_f("mpp_buffer_group_get failed ret %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
ret = mpp_buffer_get(JpegHalCtx->group, &JpegHalCtx->frame_buf,
|
||||
JPEGD_STREAM_BUFF_SIZE);
|
||||
if (MPP_OK != ret) {
|
||||
mpp_err_f("get buffer failed\n");
|
||||
if (ret) {
|
||||
mpp_err_f("get frame buffer failed ret %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = mpp_buffer_get(JpegHalCtx->group, &JpegHalCtx->pTableBase,
|
||||
JPEGD_BASELINE_TABLE_SIZE);
|
||||
if (MPP_OK != ret) {
|
||||
mpp_err_f("get buffer failed\n");
|
||||
if (ret) {
|
||||
mpp_err_f("get table buffer failed ret %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -854,18 +846,16 @@ MPP_RET hal_jpegd_vdpu1_deinit(void *hal)
|
||||
MPP_RET ret = MPP_OK;
|
||||
JpegdHalCtx *JpegHalCtx = (JpegdHalCtx *)hal;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (JpegHalCtx->dev_ctx) {
|
||||
ret = mpp_device_deinit(JpegHalCtx->dev_ctx);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("mpp_device_deinit failed ret: %d\n", ret);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
if (JpegHalCtx->frame_buf) {
|
||||
ret = mpp_buffer_put(JpegHalCtx->frame_buf);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err_f("put buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -873,7 +863,7 @@ MPP_RET hal_jpegd_vdpu1_deinit(void *hal)
|
||||
|
||||
if (JpegHalCtx->pTableBase) {
|
||||
ret = mpp_buffer_put(JpegHalCtx->pTableBase);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err_f("put buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -881,7 +871,7 @@ MPP_RET hal_jpegd_vdpu1_deinit(void *hal)
|
||||
|
||||
if (JpegHalCtx->group) {
|
||||
ret = mpp_buffer_group_put(JpegHalCtx->group);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err_f("group free buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -913,17 +903,14 @@ MPP_RET hal_jpegd_vdpu1_gen_regs(void *hal, HalTaskInfo *syn)
|
||||
MPP_RET ret = MPP_OK;
|
||||
JpegdHalCtx *JpegHalCtx = (JpegdHalCtx *)hal;
|
||||
JpegdSyntax *syntax = (JpegdSyntax *)syn->dec.syntax.data;
|
||||
#ifdef RKPLATFORM
|
||||
MppBuffer streambuf = NULL;
|
||||
MppBuffer outputBuf = NULL;
|
||||
#endif
|
||||
|
||||
if (syn->dec.valid) {
|
||||
syn->dec.valid = 0;
|
||||
|
||||
jpegd_setup_output_fmt(JpegHalCtx, syntax);
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (JpegHalCtx->set_output_fmt_flag && (NULL != JpegHalCtx->dev_ctx)) {
|
||||
mpp_device_deinit(JpegHalCtx->dev_ctx);
|
||||
MppDevCfg dev_cfg = {
|
||||
@@ -950,7 +937,6 @@ MPP_RET hal_jpegd_vdpu1_gen_regs(void *hal, HalTaskInfo *syn)
|
||||
mpp_buf_slot_get_prop(JpegHalCtx->frame_slots, syn->dec.output,
|
||||
SLOT_BUFFER, &outputBuf);
|
||||
JpegHalCtx->frame_fd = mpp_buffer_get_fd(outputBuf);
|
||||
#endif
|
||||
|
||||
jpegd_setup_pp(JpegHalCtx, syntax);
|
||||
|
||||
@@ -973,16 +959,14 @@ MPP_RET hal_jpegd_vdpu1_start(void *hal, HalTaskInfo *task)
|
||||
MPP_RET ret = MPP_OK;
|
||||
JpegdHalCtx *JpegHalCtx = (JpegdHalCtx *)hal;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
RK_U32 *p_regs = (RK_U32 *)JpegHalCtx->regs;
|
||||
ret = mpp_device_send_reg(JpegHalCtx->dev_ctx, p_regs,
|
||||
sizeof(JpegdIocRegInfo) / sizeof(RK_U32));
|
||||
if (ret != 0) {
|
||||
if (ret) {
|
||||
mpp_err_f("mpp_device_send_reg Failed!!!\n");
|
||||
return MPP_ERR_VPUHW;
|
||||
}
|
||||
#endif
|
||||
(void)JpegHalCtx;
|
||||
|
||||
(void)task;
|
||||
jpegd_dbg_func("exit\n");
|
||||
return ret;
|
||||
@@ -993,10 +977,8 @@ MPP_RET hal_jpegd_vdpu1_wait(void *hal, HalTaskInfo *task)
|
||||
jpegd_dbg_func("enter\n");
|
||||
MPP_RET ret = MPP_OK;
|
||||
JpegdHalCtx *JpegHalCtx = (JpegdHalCtx *)hal;
|
||||
(void)JpegHalCtx;
|
||||
(void)task;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
JpegRegSet *reg_out = NULL;
|
||||
RK_U32 errinfo = 1;
|
||||
MppFrame tmp = NULL;
|
||||
@@ -1056,7 +1038,6 @@ MPP_RET hal_jpegd_vdpu1_wait(void *hal, HalTaskInfo *task)
|
||||
JpegHalCtx->output_yuv_count++;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
jpegd_dbg_func("exit\n");
|
||||
return ret;
|
||||
|
@@ -752,13 +752,13 @@ MPP_RET hal_jpegd_vdpu2_init(void *hal, MppHalCfg *cfg)
|
||||
JpegHalCtx->frame_slots = cfg->frame_slots;
|
||||
|
||||
//get vpu socket
|
||||
#ifdef RKPLATFORM
|
||||
MppDevCfg dev_cfg = {
|
||||
.type = MPP_CTX_DEC, /* type */
|
||||
.coding = MPP_VIDEO_CodingMJPEG, /* coding */
|
||||
.platform = 0, /* platform */
|
||||
.pp_enable = 0, /* pp_enable */
|
||||
};
|
||||
|
||||
ret = mpp_device_init(&JpegHalCtx->dev_ctx, &dev_cfg);
|
||||
if (ret) {
|
||||
mpp_err("mpp_device_init failed. ret: %d\n", ret);
|
||||
@@ -766,7 +766,6 @@ MPP_RET hal_jpegd_vdpu2_init(void *hal, MppHalCfg *cfg)
|
||||
} else {
|
||||
jpegd_dbg_hal("mpp_device_init success. \n");
|
||||
}
|
||||
#endif
|
||||
|
||||
//init regs
|
||||
JpegdIocRegInfo *info = NULL;
|
||||
@@ -785,15 +784,9 @@ MPP_RET hal_jpegd_vdpu2_init(void *hal, MppHalCfg *cfg)
|
||||
|
||||
//malloc hw buf
|
||||
if (JpegHalCtx->group == NULL) {
|
||||
#ifdef RKPLATFORM
|
||||
jpegd_dbg_hal("mpp_buffer_group_get_internal used ion in");
|
||||
ret = mpp_buffer_group_get_internal(&JpegHalCtx->group,
|
||||
MPP_BUFFER_TYPE_ION);
|
||||
#else
|
||||
ret = mpp_buffer_group_get_internal(&JpegHalCtx->group,
|
||||
MPP_BUFFER_TYPE_NORMAL);
|
||||
#endif
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err_f("mpp_buffer_group_get failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -801,14 +794,14 @@ MPP_RET hal_jpegd_vdpu2_init(void *hal, MppHalCfg *cfg)
|
||||
|
||||
ret = mpp_buffer_get(JpegHalCtx->group, &JpegHalCtx->frame_buf,
|
||||
JPEGD_STREAM_BUFF_SIZE);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err_f("get buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = mpp_buffer_get(JpegHalCtx->group, &JpegHalCtx->pTableBase,
|
||||
JPEGD_BASELINE_TABLE_SIZE);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err_f("get buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -837,34 +830,32 @@ MPP_RET hal_jpegd_vdpu2_deinit(void *hal)
|
||||
MPP_RET ret = MPP_OK;
|
||||
JpegdHalCtx *JpegHalCtx = (JpegdHalCtx *)hal;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (JpegHalCtx->dev_ctx) {
|
||||
ret = mpp_device_deinit(JpegHalCtx->dev_ctx);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("mpp_device_deinit failed. ret: %d\n", ret);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
if (JpegHalCtx->frame_buf) {
|
||||
ret = mpp_buffer_put(JpegHalCtx->frame_buf);
|
||||
if (MPP_OK != ret) {
|
||||
mpp_err_f("put buffer failed\n");
|
||||
if (ret) {
|
||||
mpp_err_f("put frame buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
if (JpegHalCtx->pTableBase) {
|
||||
ret = mpp_buffer_put(JpegHalCtx->pTableBase);
|
||||
if (MPP_OK != ret) {
|
||||
mpp_err_f("put buffer failed\n");
|
||||
if (ret) {
|
||||
mpp_err_f("put table buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
if (JpegHalCtx->group) {
|
||||
ret = mpp_buffer_group_put(JpegHalCtx->group);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err_f("group free buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -895,16 +886,13 @@ MPP_RET hal_jpegd_vdpu2_gen_regs(void *hal, HalTaskInfo *syn)
|
||||
MPP_RET ret = MPP_OK;
|
||||
JpegdHalCtx *JpegHalCtx = (JpegdHalCtx *)hal;
|
||||
JpegdSyntax *syntax = (JpegdSyntax *)syn->dec.syntax.data;
|
||||
#ifdef RKPLATFORM
|
||||
MppBuffer streambuf = NULL;
|
||||
MppBuffer outputBuf = NULL;
|
||||
#endif
|
||||
|
||||
if (syn->dec.valid) {
|
||||
syn->dec.valid = 0;
|
||||
jpegd_setup_output_fmt(JpegHalCtx, syntax);
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (JpegHalCtx->set_output_fmt_flag && (NULL != JpegHalCtx->dev_ctx)) {
|
||||
mpp_device_deinit(JpegHalCtx->dev_ctx);
|
||||
MppDevCfg dev_cfg = {
|
||||
@@ -914,7 +902,7 @@ MPP_RET hal_jpegd_vdpu2_gen_regs(void *hal, HalTaskInfo *syn)
|
||||
.pp_enable = 1, /* pp_enable */
|
||||
};
|
||||
ret = mpp_device_init(&JpegHalCtx->dev_ctx, &dev_cfg);
|
||||
if (ret != MPP_OK) {
|
||||
if (ret) {
|
||||
mpp_err("mpp_device_init failed. ret: %d\n", ret);
|
||||
return ret;
|
||||
} else {
|
||||
@@ -931,7 +919,6 @@ MPP_RET hal_jpegd_vdpu2_gen_regs(void *hal, HalTaskInfo *syn)
|
||||
mpp_buf_slot_get_prop(JpegHalCtx->frame_slots, syn->dec.output,
|
||||
SLOT_BUFFER, &outputBuf);
|
||||
JpegHalCtx->frame_fd = mpp_buffer_get_fd(outputBuf);
|
||||
#endif
|
||||
|
||||
jpegd_setup_pp(JpegHalCtx, syntax);
|
||||
|
||||
@@ -953,17 +940,15 @@ MPP_RET hal_jpegd_vdpu2_start(void *hal, HalTaskInfo *task)
|
||||
jpegd_dbg_func("enter\n");
|
||||
MPP_RET ret = MPP_OK;
|
||||
JpegdHalCtx *JpegHalCtx = (JpegdHalCtx *)hal;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
RK_U32 *p_regs = (RK_U32 *)JpegHalCtx->regs;
|
||||
|
||||
ret = mpp_device_send_reg(JpegHalCtx->dev_ctx, p_regs,
|
||||
sizeof(JpegdIocRegInfo) / sizeof(RK_U32));
|
||||
if (ret != 0) {
|
||||
if (ret) {
|
||||
mpp_err_f("mpp_device_send_reg Failed!!!\n");
|
||||
return MPP_ERR_VPUHW;
|
||||
}
|
||||
#endif
|
||||
(void)JpegHalCtx;
|
||||
|
||||
(void)task;
|
||||
jpegd_dbg_func("exit\n");
|
||||
return ret;
|
||||
@@ -974,14 +959,11 @@ MPP_RET hal_jpegd_vdpu2_wait(void *hal, HalTaskInfo *task)
|
||||
jpegd_dbg_func("enter\n");
|
||||
MPP_RET ret = MPP_OK;
|
||||
JpegdHalCtx *JpegHalCtx = (JpegdHalCtx *)hal;
|
||||
(void)JpegHalCtx;
|
||||
(void)task;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
JpegRegSet *reg_out = NULL;
|
||||
RK_U32 errinfo = 1;
|
||||
MppFrame tmp = NULL;
|
||||
RK_U32 reg[184];
|
||||
(void)task;
|
||||
|
||||
ret = mpp_device_wait_reg(JpegHalCtx->dev_ctx, reg,
|
||||
sizeof(reg) / sizeof(RK_U32));
|
||||
@@ -1030,7 +1012,6 @@ MPP_RET hal_jpegd_vdpu2_wait(void *hal, HalTaskInfo *task)
|
||||
JpegHalCtx->output_yuv_count++;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
jpegd_dbg_func("exit\n");
|
||||
return ret;
|
||||
|
@@ -59,19 +59,19 @@ MPP_RET hal_jpege_vepu1_init(void *hal, MppHalCfg *cfg)
|
||||
|
||||
ctx->int_cb = cfg->hal_int_cb;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
MppDevCfg dev_cfg = {
|
||||
.type = MPP_CTX_ENC, /* type */
|
||||
.coding = MPP_VIDEO_CodingMJPEG, /* coding */
|
||||
.platform = 0, /* platform */
|
||||
.pp_enable = 0, /* pp_enable */
|
||||
};
|
||||
|
||||
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);
|
||||
if (ret) {
|
||||
mpp_err("mpp_device_init failed. ret: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
jpege_bits_init(&ctx->bits);
|
||||
mpp_assert(ctx->bits);
|
||||
|
||||
@@ -101,14 +101,12 @@ MPP_RET hal_jpege_vepu1_deinit(void *hal)
|
||||
ctx->bits = NULL;
|
||||
}
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (ctx->dev_ctx) {
|
||||
ret = mpp_device_deinit(ctx->dev_ctx);
|
||||
if (ret) {
|
||||
mpp_err("mpp_device_deinit failed. ret: %d\n", ret);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
mpp_free(ctx->ioctl_info.regs);
|
||||
hal_jpege_dbg_func("leave hal %p\n", hal);
|
||||
@@ -446,7 +444,6 @@ MPP_RET hal_jpege_vepu1_start(void *hal, HalTaskInfo *task)
|
||||
|
||||
hal_jpege_dbg_func("enter hal %p\n", hal);
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
cache = mpp_malloc(RK_U32, reg_num + extra_num);
|
||||
if (!cache) {
|
||||
mpp_err_f("failed to malloc reg cache\n");
|
||||
@@ -461,7 +458,6 @@ MPP_RET hal_jpege_vepu1_start(void *hal, HalTaskInfo *task)
|
||||
}
|
||||
|
||||
mpp_free(cache);
|
||||
#endif
|
||||
|
||||
hal_jpege_dbg_func("leave hal %p\n", hal);
|
||||
(void)ctx;
|
||||
@@ -481,11 +477,9 @@ MPP_RET hal_jpege_vepu1_wait(void *hal, HalTaskInfo *task)
|
||||
|
||||
hal_jpege_dbg_func("enter hal %p\n", hal);
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (ctx->dev_ctx) {
|
||||
if (ctx->dev_ctx)
|
||||
ret = mpp_device_wait_reg(ctx->dev_ctx, regs, sizeof(jpege_vepu1_reg_set) / sizeof(RK_U32));
|
||||
}
|
||||
#endif
|
||||
|
||||
val = regs[1];
|
||||
hal_jpege_dbg_output("hw_status %x\n", val);
|
||||
feedback.hw_status = val & 0x70;
|
||||
|
@@ -58,19 +58,19 @@ MPP_RET hal_jpege_vepu2_init(void *hal, MppHalCfg *cfg)
|
||||
|
||||
ctx->int_cb = cfg->hal_int_cb;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
MppDevCfg dev_cfg = {
|
||||
.type = MPP_CTX_ENC, /* type */
|
||||
.coding = MPP_VIDEO_CodingMJPEG, /* coding */
|
||||
.platform = 0, /* platform */
|
||||
.pp_enable = 0, /* pp_enable */
|
||||
};
|
||||
|
||||
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);
|
||||
if (ret != MPP_OK) {
|
||||
if (ret) {
|
||||
mpp_err_f("failed to open vpu client\n");
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
jpege_bits_init(&ctx->bits);
|
||||
mpp_assert(ctx->bits);
|
||||
|
||||
@@ -99,12 +99,11 @@ MPP_RET hal_jpege_vepu2_deinit(void *hal)
|
||||
ctx->bits = NULL;
|
||||
}
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (ctx->dev_ctx) {
|
||||
mpp_device_deinit(ctx->dev_ctx);
|
||||
ctx->dev_ctx = NULL;
|
||||
}
|
||||
#endif
|
||||
|
||||
mpp_free(ctx->ioctl_info.regs);
|
||||
|
||||
hal_jpege_dbg_func("leave hal %p\n", hal);
|
||||
@@ -424,7 +423,6 @@ MPP_RET hal_jpege_vepu2_start(void *hal, HalTaskInfo *task)
|
||||
|
||||
hal_jpege_dbg_func("enter hal %p\n", hal);
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
cache = mpp_malloc(RK_U32, reg_num + extra_num);
|
||||
if (!cache) {
|
||||
mpp_err_f("failed to malloc reg cache\n");
|
||||
@@ -439,7 +437,6 @@ MPP_RET hal_jpege_vepu2_start(void *hal, HalTaskInfo *task)
|
||||
}
|
||||
|
||||
mpp_free(cache);
|
||||
#endif
|
||||
|
||||
hal_jpege_dbg_func("leave hal %p\n", hal);
|
||||
(void)ctx;
|
||||
@@ -460,11 +457,10 @@ MPP_RET hal_jpege_vepu2_wait(void *hal, HalTaskInfo *task)
|
||||
|
||||
hal_jpege_dbg_func("enter hal %p\n", hal);
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (ctx->dev_ctx) {
|
||||
|
||||
if (ctx->dev_ctx)
|
||||
ret = mpp_device_wait_reg(ctx->dev_ctx, regs, sizeof(jpege_vepu2_reg_set) / sizeof(RK_U32));
|
||||
}
|
||||
#endif
|
||||
|
||||
val = regs[109];
|
||||
hal_jpege_dbg_output("hw_status %x\n", val);
|
||||
feedback.hw_status = val & 0x70;
|
||||
|
@@ -39,33 +39,29 @@ MPP_RET hal_m2vd_vdpu1_init(void *hal, MppHalCfg *cfg)
|
||||
|
||||
ctx->reg_len = M2VD_VDPU1_REG_NUM;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
MppDevCfg dev_cfg = {
|
||||
.type = MPP_CTX_DEC, /* type */
|
||||
.coding = MPP_VIDEO_CodingMPEG2, /* coding */
|
||||
.platform = 0, /* platform */
|
||||
.pp_enable = 0, /* pp_enable */
|
||||
};
|
||||
|
||||
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);
|
||||
if (ret) {
|
||||
mpp_err("mpp_device_init failed. ret: %d\n", ret);
|
||||
ret = MPP_ERR_UNKNOW;
|
||||
goto __ERR_RET;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (ctx->group == NULL) {
|
||||
#ifdef RKPLATFORM
|
||||
ret = mpp_buffer_group_get_internal(&ctx->group, MPP_BUFFER_TYPE_ION);
|
||||
#else
|
||||
ret = mpp_buffer_group_get_internal(&ctx->group, MPP_BUFFER_TYPE_NORMAL);
|
||||
#endif
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("m2v_hal mpp_buffer_group_get failed\n");
|
||||
goto __ERR_RET;
|
||||
}
|
||||
}
|
||||
ret = mpp_buffer_get(ctx->group, &ctx->qp_table, M2VD_BUF_SIZE_QPTAB);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("m2v_hal_qtable_base get buffer failed\n");
|
||||
goto __ERR_RET;
|
||||
}
|
||||
@@ -95,12 +91,11 @@ MPP_RET hal_m2vd_vdpu1_deinit(void *hal)
|
||||
MPP_RET ret = MPP_OK;
|
||||
M2vdHalCtx *p = (M2vdHalCtx *)hal;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (p->dev_ctx) {
|
||||
mpp_device_deinit(p->dev_ctx);
|
||||
p->dev_ctx = NULL;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (p->qp_table) {
|
||||
ret = mpp_buffer_put(p->qp_table);
|
||||
p->qp_table = NULL;
|
||||
@@ -113,7 +108,7 @@ MPP_RET hal_m2vd_vdpu1_deinit(void *hal)
|
||||
if (p->group) {
|
||||
ret = mpp_buffer_group_put(p->group);
|
||||
p->group = NULL;
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("m2v_hal group free buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -159,13 +154,12 @@ MPP_RET hal_m2vd_vdpu1_gen_regs(void *hal, HalTaskInfo *task)
|
||||
MPP_RET ret = MPP_OK;
|
||||
if (task->dec.valid) {
|
||||
void *q_table = NULL;
|
||||
#ifdef RKPLATFORM
|
||||
MppBuffer streambuf = NULL;
|
||||
MppBuffer framebuf = NULL;
|
||||
#endif
|
||||
M2vdHalCtx *ctx = (M2vdHalCtx *)hal;
|
||||
M2VDDxvaParam *dx = (M2VDDxvaParam *)task->dec.syntax.data;
|
||||
M2vdVdpu1Reg_t *p_regs = (M2vdVdpu1Reg_t*) ctx->regs;
|
||||
|
||||
task->dec.valid = 0;
|
||||
q_table = mpp_buffer_get_ptr(ctx->qp_table);
|
||||
memcpy(q_table, dx->qp_tab, M2VD_BUF_SIZE_QPTAB);
|
||||
@@ -220,7 +214,7 @@ MPP_RET hal_m2vd_vdpu1_gen_regs(void *hal, HalTaskInfo *task)
|
||||
p_regs->sw05.intra_vlc_tab = dx->pic_code_ext.intra_vlc_format;
|
||||
p_regs->sw05.frame_pred_dct = dx->pic_code_ext.frame_pred_frame_dct;
|
||||
p_regs->sw06.init_qp = 1;
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
mpp_buf_slot_get_prop(ctx->packet_slots, task->dec.input, SLOT_BUFFER, &streambuf);
|
||||
p_regs->sw12.rlc_vlc_base = mpp_buffer_get_fd(streambuf);
|
||||
p_regs->sw12.rlc_vlc_base |= (dx->bitstream_offset << 10);
|
||||
@@ -247,7 +241,7 @@ MPP_RET hal_m2vd_vdpu1_gen_regs(void *hal, HalTaskInfo *task)
|
||||
p_regs->sw17.refer3_base = mpp_buffer_get_fd(framebuf);
|
||||
|
||||
p_regs->sw40.qtable_base = mpp_buffer_get_fd(ctx->qp_table);
|
||||
#endif
|
||||
|
||||
p_regs->sw48.startmb_x = 0;
|
||||
p_regs->sw48.startmb_y = 0;
|
||||
p_regs->sw03.dec_out_dis = 0;
|
||||
@@ -266,38 +260,35 @@ MPP_RET hal_m2vd_vdpu1_gen_regs(void *hal, HalTaskInfo *task)
|
||||
MPP_RET hal_m2vd_vdpu1_start(void *hal, HalTaskInfo *task)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
#ifdef RKPLATFORM
|
||||
M2vdHalCtx *ctx = (M2vdHalCtx *)hal;
|
||||
RK_U32 *p_regs = (RK_U32 *)ctx->regs;
|
||||
|
||||
ret = mpp_device_send_reg(ctx->dev_ctx, p_regs, ctx->reg_len);
|
||||
if (ret != 0) {
|
||||
if (ret) {
|
||||
mpp_err("mpp_device_send_reg failed.\n");
|
||||
return MPP_ERR_VPUHW;
|
||||
}
|
||||
#endif
|
||||
(void)task;
|
||||
(void)hal;
|
||||
|
||||
(void)task;
|
||||
return ret;
|
||||
}
|
||||
|
||||
MPP_RET hal_m2vd_vdpu1_wait(void *hal, HalTaskInfo *task)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
#ifdef RKPLATFORM
|
||||
M2vdVdpu1Reg_t reg_out;
|
||||
M2vdHalCtx *ctx = (M2vdHalCtx *)hal;
|
||||
|
||||
memset(®_out, 0, sizeof(M2vdVdpu1Reg_t));
|
||||
ret = mpp_device_wait_reg(ctx->dev_ctx, (RK_U32 *)®_out, ctx->reg_len);
|
||||
if (reg_out.sw01.dec_error_int | reg_out.sw01.dec_buffer_int) {
|
||||
if (ctx->int_cb.callBack)
|
||||
ctx->int_cb.callBack(ctx->int_cb.opaque, NULL);
|
||||
}
|
||||
#endif
|
||||
if (ret) {
|
||||
|
||||
if (ret)
|
||||
mpp_log("mpp_device_wait_reg return error:%d", ret);
|
||||
}
|
||||
(void)hal;
|
||||
|
||||
(void)task;
|
||||
|
||||
return ret;
|
||||
|
@@ -42,7 +42,6 @@ MPP_RET hal_m2vd_vdpu2_init(void *hal, MppHalCfg *cfg)
|
||||
|
||||
p->reg_len = M2VD_VDPU2_REG_NUM;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
MppDevCfg dev_cfg = {
|
||||
.type = MPP_CTX_DEC, /* type */
|
||||
.coding = MPP_VIDEO_CodingMPEG2, /* coding */
|
||||
@@ -54,21 +53,17 @@ MPP_RET hal_m2vd_vdpu2_init(void *hal, MppHalCfg *cfg)
|
||||
mpp_err("mpp_device_init failed. ret: %d\n", ret);
|
||||
goto __ERR_RET;
|
||||
}
|
||||
#endif
|
||||
if (p->group == NULL) {
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (p->group == NULL) {
|
||||
ret = mpp_buffer_group_get_internal(&p->group, MPP_BUFFER_TYPE_ION);
|
||||
#else
|
||||
ret = mpp_buffer_group_get_internal(&p->group, MPP_BUFFER_TYPE_NORMAL);
|
||||
#endif
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("m2v_hal mpp_buffer_group_get failed\n");
|
||||
goto __ERR_RET;
|
||||
}
|
||||
}
|
||||
|
||||
ret = mpp_buffer_get(p->group, &p->qp_table, M2VD_BUF_SIZE_QPTAB);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("m2v_hal qtable_base get buffer failed\n");
|
||||
goto __ERR_RET;
|
||||
}
|
||||
@@ -116,19 +111,18 @@ MPP_RET hal_m2vd_vdpu2_deinit(void *hal)
|
||||
m2vh_dbg_func("FUN_I");
|
||||
M2vdHalCtx *p = (M2vdHalCtx *)hal;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (p->dev_ctx) {
|
||||
ret = mpp_device_deinit(p->dev_ctx);
|
||||
p->dev_ctx = NULL;
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("mpp_device_deinit failed ret: %d\n", ret);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
if (p->qp_table) {
|
||||
ret = mpp_buffer_put(p->qp_table);
|
||||
p->qp_table = NULL;
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("m2v_hal qp_table put buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -137,7 +131,7 @@ MPP_RET hal_m2vd_vdpu2_deinit(void *hal)
|
||||
if (p->group) {
|
||||
ret = mpp_buffer_group_put(p->group);
|
||||
p->group = NULL;
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("m2v_hal group free buffer failed\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -201,13 +195,12 @@ MPP_RET hal_m2vd_vdpu2_gen_regs(void *hal, HalTaskInfo *task)
|
||||
MPP_RET ret = MPP_OK;
|
||||
if (task->dec.valid) {
|
||||
void *q_table = NULL;
|
||||
#ifdef RKPLATFORM
|
||||
MppBuffer streambuf = NULL;
|
||||
MppBuffer framebuf = NULL;
|
||||
#endif
|
||||
M2vdHalCtx *ctx = (M2vdHalCtx *)hal;
|
||||
M2VDDxvaParam *dx = (M2VDDxvaParam *)task->dec.syntax.data;
|
||||
M2vdVdpu2Reg *p_regs = ctx->regs;
|
||||
|
||||
task->dec.valid = 0;
|
||||
q_table = mpp_buffer_get_ptr(ctx->qp_table);
|
||||
memcpy(q_table, dx->qp_tab, M2VD_BUF_SIZE_QPTAB);
|
||||
@@ -263,7 +256,7 @@ MPP_RET hal_m2vd_vdpu2_gen_regs(void *hal, HalTaskInfo *task)
|
||||
p_regs->sw122.intra_vlc_tab = dx->pic_code_ext.intra_vlc_format;
|
||||
p_regs->sw122.frame_pred_dct = dx->pic_code_ext.frame_pred_frame_dct;
|
||||
p_regs->sw51.init_qp = 1;
|
||||
#ifdef RKPLATFORM //current strem in frame out config
|
||||
|
||||
mpp_buf_slot_get_prop(ctx->packet_slots, task->dec.input, SLOT_BUFFER, &streambuf);
|
||||
p_regs->sw64.VLC_base = mpp_buffer_get_fd(streambuf);
|
||||
p_regs->sw64.VLC_base |= (dx->bitstream_offset << 10);
|
||||
@@ -292,7 +285,7 @@ MPP_RET hal_m2vd_vdpu2_gen_regs(void *hal, HalTaskInfo *task)
|
||||
p_regs->sw135.ref3 = mpp_buffer_get_fd(framebuf); //just index need map
|
||||
|
||||
p_regs->sw61.slice_table = mpp_buffer_get_fd(ctx->qp_table);
|
||||
#endif
|
||||
|
||||
p_regs->sw52.startmb_x = 0;
|
||||
p_regs->sw52.startmb_y = 0;
|
||||
p_regs->sw57.dec_out_dis = 0;
|
||||
@@ -329,18 +322,18 @@ MPP_RET hal_m2vd_vdpu2_gen_regs(void *hal, HalTaskInfo *task)
|
||||
MPP_RET hal_m2vd_vdpu2_start(void *hal, HalTaskInfo *task)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
#ifdef RKPLATFORM
|
||||
M2vdHalCtx *ctx = (M2vdHalCtx *)hal;
|
||||
RK_U32 *p_regs = (RK_U32 *)ctx->regs;
|
||||
|
||||
m2vh_dbg_func("FUN_I");
|
||||
|
||||
ret = mpp_device_send_reg(ctx->dev_ctx, p_regs, ctx->reg_len);
|
||||
if (ret != 0) {
|
||||
if (ret) {
|
||||
mpp_err("mpp_device_send_reg Failed!!!\n");
|
||||
return MPP_ERR_VPUHW;
|
||||
}
|
||||
#endif
|
||||
|
||||
(void)task;
|
||||
(void)hal;
|
||||
m2vh_dbg_func("FUN_O");
|
||||
return ret;
|
||||
}
|
||||
@@ -348,11 +341,11 @@ MPP_RET hal_m2vd_vdpu2_start(void *hal, HalTaskInfo *task)
|
||||
MPP_RET hal_m2vd_vdpu2_wait(void *hal, HalTaskInfo *task)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
#ifdef RKPLATFORM
|
||||
M2vdVdpu2Reg reg_out;
|
||||
M2vdHalCtx *ctx = (M2vdHalCtx *)hal;
|
||||
|
||||
m2vh_dbg_func("FUN_I");
|
||||
|
||||
memset(®_out, 0, sizeof(M2vdVdpu2Reg));
|
||||
ret = mpp_device_wait_reg(ctx->dev_ctx, (RK_U32 *)®_out, ctx->reg_len);
|
||||
if (ctx->fp_reg_out) {
|
||||
@@ -367,13 +360,14 @@ MPP_RET hal_m2vd_vdpu2_wait(void *hal, HalTaskInfo *task)
|
||||
if (ctx->int_cb.callBack)
|
||||
ctx->int_cb.callBack(ctx->int_cb.opaque, NULL);
|
||||
}
|
||||
|
||||
if (M2VH_DBG_IRQ & m2vh_debug)
|
||||
mpp_log("mpp_device_wait_reg return interrupt:%08x", reg_out.sw55);
|
||||
#endif
|
||||
|
||||
if (ret) {
|
||||
mpp_log("mpp_device_wait_reg return error:%d", ret);
|
||||
}
|
||||
(void)hal;
|
||||
|
||||
(void)task;
|
||||
m2vh_dbg_func("FUN_O");
|
||||
return ret;
|
||||
|
@@ -19,21 +19,16 @@
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#ifdef RKPLATFORM
|
||||
#include <dlfcn.h>
|
||||
#include <unistd.h>
|
||||
#endif
|
||||
|
||||
#include "rk_type.h"
|
||||
#include "mpp_device.h"
|
||||
#include "mpp_log.h"
|
||||
#include "mpp_err.h"
|
||||
#include "mpp_mem.h"
|
||||
#include "mpp_env.h"
|
||||
#include "mpp_device.h"
|
||||
#include "mpp_platform.h"
|
||||
|
||||
//#include "dxva_syntax.h"
|
||||
|
||||
#include "hal_mpg4d_api.h"
|
||||
#include "hal_m4vd_com.h"
|
||||
|
||||
|
@@ -259,19 +259,18 @@ MPP_RET vdpu1_mpg4d_init(void *hal, MppHalCfg *cfg)
|
||||
goto ERR_RET;
|
||||
}
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
MppDevCfg dev_cfg = {
|
||||
.type = MPP_CTX_DEC, /* type */
|
||||
.coding = MPP_VIDEO_CodingMPEG4, /* coding */
|
||||
.platform = 0, /* platform */
|
||||
.pp_enable = 0, /* pp_enable */
|
||||
};
|
||||
|
||||
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);
|
||||
if (ret) {
|
||||
mpp_err_f("mpp_device_init failed. ret: %d\n", ret);
|
||||
goto ERR_RET;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* basic register configuration setup here
|
||||
@@ -354,14 +353,11 @@ MPP_RET vdpu1_mpg4d_deinit(void *hal)
|
||||
ctx->group = NULL;
|
||||
}
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (ctx->dev_ctx) {
|
||||
ret = mpp_device_deinit(ctx->dev_ctx);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret)
|
||||
mpp_err("mpp_device_deinit failed ret: %d\n", ret);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
@@ -410,8 +406,6 @@ MPP_RET vdpu1_mpg4d_gen_regs(void *hal, HalTaskInfo *syn)
|
||||
MPP_RET vdpu1_mpg4d_start(void *hal, HalTaskInfo *task)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal;
|
||||
RK_U32 reg_count = (sizeof(*(M4vdVdpu1Regs_t *)(ctx->regs)) / sizeof(RK_U32));
|
||||
RK_U32* regs = (RK_U32 *)ctx->regs;
|
||||
@@ -424,9 +418,7 @@ MPP_RET vdpu1_mpg4d_start(void *hal, HalTaskInfo *task)
|
||||
}
|
||||
|
||||
ret = mpp_device_send_reg(ctx->dev_ctx, regs, reg_count);
|
||||
#endif
|
||||
(void)ret;
|
||||
(void)hal;
|
||||
|
||||
(void)task;
|
||||
return ret;
|
||||
}
|
||||
@@ -434,7 +426,6 @@ MPP_RET vdpu1_mpg4d_start(void *hal, HalTaskInfo *task)
|
||||
MPP_RET vdpu1_mpg4d_wait(void *hal, HalTaskInfo *task)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
#ifdef RKPLATFORM
|
||||
hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal;
|
||||
M4vdVdpu1Regs_t reg_out;
|
||||
RK_U32* regs = (RK_U32 *)®_out;
|
||||
@@ -449,9 +440,7 @@ MPP_RET vdpu1_mpg4d_wait(void *hal, HalTaskInfo *task)
|
||||
mpp_log("reg[%03d]: %08x\n", i, regs[i]);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
(void)ret;
|
||||
(void)hal;
|
||||
|
||||
(void)task;
|
||||
return ret;
|
||||
}
|
||||
|
@@ -257,19 +257,18 @@ MPP_RET vdpu2_mpg4d_init(void *hal, MppHalCfg *cfg)
|
||||
goto ERR_RET;
|
||||
}
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
MppDevCfg dev_cfg = {
|
||||
.type = MPP_CTX_DEC, /* type */
|
||||
.coding = MPP_VIDEO_CodingMPEG4, /* coding */
|
||||
.platform = 0, /* platform */
|
||||
.pp_enable = 0, /* pp_enable */
|
||||
};
|
||||
|
||||
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);
|
||||
if (ret) {
|
||||
mpp_err_f("mpp_device_init failed. ret: %d\n", ret);
|
||||
goto ERR_RET;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* basic register configuration setup here
|
||||
@@ -352,14 +351,11 @@ MPP_RET vdpu2_mpg4d_deinit(void *hal)
|
||||
ctx->group = NULL;
|
||||
}
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (ctx->dev_ctx) {
|
||||
ret = mpp_device_deinit(ctx->dev_ctx);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret)
|
||||
mpp_err("mpp_device_deinit failed. ret: %d\n", ret);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
@@ -408,8 +404,6 @@ MPP_RET vdpu2_mpg4d_gen_regs(void *hal, HalTaskInfo *syn)
|
||||
MPP_RET vdpu2_mpg4d_start(void *hal, HalTaskInfo *task)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal;
|
||||
RK_U32 reg_count = (sizeof(*(M4vdVdpu2Regs_t *)ctx->regs) / sizeof(RK_U32));
|
||||
RK_U32* regs = (RK_U32 *)ctx->regs;
|
||||
@@ -422,9 +416,7 @@ MPP_RET vdpu2_mpg4d_start(void *hal, HalTaskInfo *task)
|
||||
}
|
||||
|
||||
ret = mpp_device_send_reg(ctx->dev_ctx, regs, reg_count);
|
||||
#endif
|
||||
(void)ret;
|
||||
(void)hal;
|
||||
|
||||
(void)task;
|
||||
return ret;
|
||||
}
|
||||
@@ -432,7 +424,6 @@ MPP_RET vdpu2_mpg4d_start(void *hal, HalTaskInfo *task)
|
||||
MPP_RET vdpu2_mpg4d_wait(void *hal, HalTaskInfo *task)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
#ifdef RKPLATFORM
|
||||
hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal;
|
||||
M4vdVdpu2Regs_t reg_out;
|
||||
RK_U32* regs = (RK_U32 *)®_out;
|
||||
@@ -447,9 +438,7 @@ MPP_RET vdpu2_mpg4d_wait(void *hal, HalTaskInfo *task)
|
||||
mpp_log("reg[%03d]: %08x\n", i, regs[i]);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
(void)ret;
|
||||
(void)hal;
|
||||
|
||||
(void)task;
|
||||
return ret;
|
||||
}
|
||||
|
@@ -51,55 +51,50 @@ MPP_RET hal_vp8d_vdpu1_init(void *hal, MppHalCfg *cfg)
|
||||
ctx->frame_slots = cfg->frame_slots;
|
||||
|
||||
mpp_env_get_u32("vp8h_debug", &vp8h_debug, 0);
|
||||
|
||||
//get vpu socket
|
||||
#ifdef RKPLATFORM
|
||||
MppDevCfg dev_cfg = {
|
||||
.type = MPP_CTX_DEC, /* type */
|
||||
.coding = MPP_VIDEO_CodingVP8, /* coding */
|
||||
.platform = 0, /* platform */
|
||||
.pp_enable = 0, /* pp_enable */
|
||||
};
|
||||
|
||||
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);
|
||||
if (ret) {
|
||||
mpp_err("mpp_device_init failed, ret: %d\n", ret);
|
||||
FUN_T("FUN_OUT");
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (NULL == ctx->regs) {
|
||||
ctx->regs = mpp_calloc_size(void, sizeof(VP8DRegSet_t));
|
||||
if (NULL == ctx->regs) {
|
||||
mpp_err("hal_vp8 reg alloc failed\n");
|
||||
|
||||
FUN_T("FUN_OUT");
|
||||
return MPP_ERR_NOMEM;
|
||||
}
|
||||
}
|
||||
|
||||
if (NULL == ctx->group) {
|
||||
#ifdef RKPLATFORM
|
||||
ret = mpp_buffer_group_get_internal(&ctx->group, MPP_BUFFER_TYPE_ION);
|
||||
#else
|
||||
ret = mpp_buffer_group_get_internal(&ctx->group, MPP_BUFFER_TYPE_NORMAL);
|
||||
#endif
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("hal_vp8 mpp_buffer_group_get failed\n");
|
||||
|
||||
FUN_T("FUN_OUT");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
ret = mpp_buffer_get(ctx->group, &ctx->probe_table, VP8D_PROB_TABLE_SIZE);
|
||||
if (MPP_OK != ret) {
|
||||
mpp_err("hal_vp8 probe_table get buffer failed\n");
|
||||
|
||||
ret = mpp_buffer_get(ctx->group, &ctx->probe_table, VP8D_PROB_TABLE_SIZE);
|
||||
if (ret) {
|
||||
mpp_err("hal_vp8 probe_table get buffer failed\n");
|
||||
FUN_T("FUN_OUT");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = mpp_buffer_get(ctx->group, &ctx->seg_map, VP8D_MAX_SEGMAP_SIZE);
|
||||
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("hal_vp8 seg_map get buffer failed\n");
|
||||
FUN_T("FUN_OUT");
|
||||
return ret;
|
||||
@@ -111,34 +106,33 @@ MPP_RET hal_vp8d_vdpu1_init(void *hal, MppHalCfg *cfg)
|
||||
MPP_RET hal_vp8d_vdpu1_deinit(void *hal)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
|
||||
|
||||
FUN_T("FUN_IN");
|
||||
VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
|
||||
#ifdef RKPLATFORM
|
||||
if (ctx->dev_ctx) {
|
||||
ret = mpp_device_deinit(ctx->dev_ctx);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("mpp_device_deinit failed. ret: %d\n", ret);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
if (ctx->probe_table) {
|
||||
ret = mpp_buffer_put(ctx->probe_table);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("hal_vp8 probe table put buffer failed\n");
|
||||
}
|
||||
}
|
||||
|
||||
if (ctx->seg_map) {
|
||||
ret = mpp_buffer_put(ctx->seg_map);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("hal_vp8 seg map put buffer failed\n");
|
||||
}
|
||||
}
|
||||
|
||||
if (ctx->group) {
|
||||
ret = mpp_buffer_group_put(ctx->group);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("hal_vp8 group free buffer failed\n");
|
||||
}
|
||||
}
|
||||
@@ -185,10 +179,9 @@ static MPP_RET hal_vp8_init_hwcfg(VP8DHalContext_t *ctx)
|
||||
reg->reg3.sw_dec_mode = DEC_MODE_VP8;
|
||||
|
||||
reg->reg1_interrupt.sw_dec_irq = 0;
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
reg->reg10_segment_map_base = mpp_buffer_get_fd(ctx->seg_map);
|
||||
reg->reg40_qtable_base = mpp_buffer_get_fd(ctx->probe_table);
|
||||
#endif
|
||||
|
||||
FUN_T("FUN_OUT");
|
||||
return MPP_OK;
|
||||
@@ -254,23 +247,21 @@ hal_vp8d_dct_partition_cfg(VP8DHalContext_t *ctx, HalTaskInfo *task)
|
||||
RK_U32 i = 0, len = 0, len1 = 0;
|
||||
RK_U32 extraBytesPacked = 0;
|
||||
RK_U32 addr = 0, byte_offset = 0;
|
||||
#ifdef RKPLATFORM
|
||||
RK_U32 fd = 0;
|
||||
MppBuffer streambuf = NULL;
|
||||
#endif
|
||||
VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
|
||||
DXVA_PicParams_VP8 *pic_param = (DXVA_PicParams_VP8 *)task->dec.syntax.data;
|
||||
|
||||
|
||||
FUN_T("FUN_IN");
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
mpp_buf_slot_get_prop(ctx->packet_slots, task->dec.input,
|
||||
SLOT_BUFFER, &streambuf);
|
||||
fd = mpp_buffer_get_fd(streambuf);
|
||||
regs->reg27_bitpl_ctrl_base = fd;
|
||||
regs->reg27_bitpl_ctrl_base |= (pic_param->stream_start_offset << 10);
|
||||
regs->reg5.sw_strm1_start_bit = pic_param->stream_start_bit;
|
||||
#endif
|
||||
|
||||
/* calculate dct partition length here instead */
|
||||
if (pic_param->decMode == VP8HWD_VP8 && !pic_param->frame_type)
|
||||
extraBytesPacked += 7;
|
||||
@@ -437,16 +428,15 @@ MPP_RET hal_vp8d_vdpu1_gen_regs(void* hal, HalTaskInfo *task)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
RK_U32 mb_width = 0, mb_height = 0;
|
||||
#ifdef RKPLATFORM
|
||||
MppBuffer framebuf = NULL;
|
||||
RK_U8 *segmap_ptr = NULL;
|
||||
RK_U8 *probe_ptr = NULL;
|
||||
#endif
|
||||
VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
|
||||
VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
|
||||
DXVA_PicParams_VP8 *pic_param = (DXVA_PicParams_VP8 *)task->dec.syntax.data;
|
||||
|
||||
FUN_T("FUN_IN");
|
||||
|
||||
hal_vp8_init_hwcfg(ctx);
|
||||
mb_width = (pic_param->width + 15) >> 4;
|
||||
mb_height = (pic_param->height + 15) >> 4;
|
||||
@@ -456,7 +446,6 @@ MPP_RET hal_vp8d_vdpu1_gen_regs(void* hal, HalTaskInfo *task)
|
||||
regs->reg4.sw_pic_mb_w_ext = mb_width >> 9;
|
||||
regs->reg4.sw_pic_mb_h_ext = mb_height >> 8;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (!pic_param->frame_type) {
|
||||
segmap_ptr = mpp_buffer_get_ptr(ctx->seg_map);
|
||||
if (NULL != segmap_ptr) {
|
||||
@@ -506,7 +495,6 @@ MPP_RET hal_vp8d_vdpu1_gen_regs(void* hal, HalTaskInfo *task)
|
||||
((pic_param->stVP8Segments.segmentation_enabled
|
||||
+ (pic_param->stVP8Segments.update_mb_segmentation_map << 1)) << 10);
|
||||
|
||||
#endif
|
||||
regs->reg3.sw_pic_inter_e = pic_param->frame_type;
|
||||
regs->reg3.sw_skip_mode = !pic_param->mb_no_coeff_skip;
|
||||
|
||||
@@ -606,37 +594,33 @@ MPP_RET hal_vp8d_vdpu1_gen_regs(void* hal, HalTaskInfo *task)
|
||||
MPP_RET hal_vp8d_vdpu1_start(void *hal, HalTaskInfo *task)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
RK_U32 i = 0;
|
||||
VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
|
||||
VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
|
||||
RK_U8 *p = ctx->regs;
|
||||
|
||||
|
||||
FUN_T("FUN_IN");
|
||||
|
||||
for (i = 0; i < VP8D_REG_NUM; i++) {
|
||||
vp8h_dbg(VP8H_DBG_REG, "vp8d: regs[%02d]=%08X\n", i, *((RK_U32*)p));
|
||||
p += 4;
|
||||
}
|
||||
|
||||
ret = mpp_device_send_reg(ctx->dev_ctx, (RK_U32 *)regs, VP8D_REG_NUM);
|
||||
if (ret != 0) {
|
||||
if (ret) {
|
||||
mpp_err("mpp_device_send_reg Failed!!!\n");
|
||||
return MPP_ERR_VPUHW;
|
||||
}
|
||||
|
||||
FUN_T("FUN_OUT");
|
||||
#endif
|
||||
|
||||
(void)task;
|
||||
(void)hal;
|
||||
return ret;
|
||||
}
|
||||
|
||||
MPP_RET hal_vp8d_vdpu1_wait(void *hal, HalTaskInfo *task)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
#ifdef RKPLATFORM
|
||||
VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
|
||||
VP8DRegSet_t reg_out;
|
||||
|
||||
@@ -645,8 +629,7 @@ MPP_RET hal_vp8d_vdpu1_wait(void *hal, HalTaskInfo *task)
|
||||
|
||||
ret = mpp_device_wait_reg(ctx->dev_ctx, (RK_U32 *)®_out, VP8D_REG_NUM);
|
||||
FUN_T("FUN_OUT");
|
||||
#endif
|
||||
(void)hal;
|
||||
|
||||
(void)task;
|
||||
return ret;
|
||||
}
|
||||
|
@@ -51,14 +51,15 @@ MPP_RET hal_vp8d_vdpu2_init(void *hal, MppHalCfg *cfg)
|
||||
ctx->frame_slots = cfg->frame_slots;
|
||||
|
||||
mpp_env_get_u32("vp8h_debug", &vp8h_debug, 0);
|
||||
|
||||
//get vpu socket
|
||||
#ifdef RKPLATFORM
|
||||
MppDevCfg dev_cfg = {
|
||||
.type = MPP_CTX_DEC, /* type */
|
||||
.coding = MPP_VIDEO_CodingVP8, /* coding */
|
||||
.platform = 0, /* platform */
|
||||
.pp_enable = 0, /* pp_enable */
|
||||
};
|
||||
|
||||
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);
|
||||
if (ret) {
|
||||
mpp_err("mpp_device_init failed. ret: %d\n", ret);
|
||||
@@ -66,7 +67,6 @@ MPP_RET hal_vp8d_vdpu2_init(void *hal, MppHalCfg *cfg)
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif
|
||||
if (NULL == ctx->regs) {
|
||||
ctx->regs = mpp_calloc_size(void, sizeof(VP8DRegSet_t));
|
||||
if (NULL == ctx->regs) {
|
||||
@@ -78,29 +78,23 @@ MPP_RET hal_vp8d_vdpu2_init(void *hal, MppHalCfg *cfg)
|
||||
}
|
||||
|
||||
if (NULL == ctx->group) {
|
||||
#ifdef RKPLATFORM
|
||||
ret = mpp_buffer_group_get_internal(&ctx->group, MPP_BUFFER_TYPE_ION);
|
||||
#else
|
||||
ret = mpp_buffer_group_get_internal(&ctx->group, MPP_BUFFER_TYPE_NORMAL);
|
||||
#endif
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("hal_vp8 mpp_buffer_group_get failed\n");
|
||||
|
||||
FUN_T("FUN_OUT");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
ret = mpp_buffer_get(ctx->group, &ctx->probe_table, VP8D_PROB_TABLE_SIZE);
|
||||
if (MPP_OK != ret) {
|
||||
mpp_err("hal_vp8 probe_table get buffer failed\n");
|
||||
|
||||
ret = mpp_buffer_get(ctx->group, &ctx->probe_table, VP8D_PROB_TABLE_SIZE);
|
||||
if (ret) {
|
||||
mpp_err("hal_vp8 probe_table get buffer failed\n");
|
||||
FUN_T("FUN_OUT");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = mpp_buffer_get(ctx->group, &ctx->seg_map, VP8D_MAX_SEGMAP_SIZE);
|
||||
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("hal_vp8 seg_map get buffer failed\n");
|
||||
FUN_T("FUN_OUT");
|
||||
return ret;
|
||||
@@ -112,35 +106,34 @@ MPP_RET hal_vp8d_vdpu2_init(void *hal, MppHalCfg *cfg)
|
||||
MPP_RET hal_vp8d_vdpu2_deinit(void *hal)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
|
||||
FUN_T("FUN_IN");
|
||||
VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
FUN_T("FUN_IN");
|
||||
|
||||
if (ctx->dev_ctx) {
|
||||
ret = mpp_device_deinit(ctx->dev_ctx);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("mpp_device_deinit failed. ret: %d\n", ret);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
if (ctx->probe_table) {
|
||||
ret = mpp_buffer_put(ctx->probe_table);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("hal_vp8 probe table put buffer failed\n");
|
||||
}
|
||||
}
|
||||
|
||||
if (ctx->seg_map) {
|
||||
ret = mpp_buffer_put(ctx->seg_map);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("hal_vp8 seg map put buffer failed\n");
|
||||
}
|
||||
}
|
||||
|
||||
if (ctx->group) {
|
||||
ret = mpp_buffer_group_put(ctx->group);
|
||||
if (MPP_OK != ret) {
|
||||
if (ret) {
|
||||
mpp_err("hal_vp8 group free buffer failed\n");
|
||||
}
|
||||
}
|
||||
@@ -186,10 +179,8 @@ static MPP_RET hal_vp8_init_hwcfg(VP8DHalContext_t *ctx)
|
||||
reg->reg57_enable_ctrl.sw_dec_clk_gate_e = 1;
|
||||
reg->reg57_enable_ctrl.sw_dec_out_dis = 0;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
reg->reg149_segment_map_base = mpp_buffer_get_fd(ctx->seg_map);
|
||||
reg->reg61_qtable_base = mpp_buffer_get_fd(ctx->probe_table);
|
||||
#endif
|
||||
|
||||
FUN_T("FUN_OUT");
|
||||
return MPP_OK;
|
||||
@@ -254,23 +245,20 @@ static MPP_RET hal_vp8d_dct_partition_cfg(VP8DHalContext_t *ctx,
|
||||
RK_U32 i = 0, len = 0, len1 = 0;
|
||||
RK_U32 extraBytesPacked = 0;
|
||||
RK_U32 addr = 0, byte_offset = 0;
|
||||
#ifdef RKPLATFORM
|
||||
RK_U32 fd = 0;
|
||||
MppBuffer streambuf = NULL;
|
||||
#endif
|
||||
VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
|
||||
DXVA_PicParams_VP8 *pic_param = (DXVA_PicParams_VP8 *)task->dec.syntax.data;
|
||||
|
||||
|
||||
FUN_T("FUN_IN");
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
mpp_buf_slot_get_prop(ctx->packet_slots, task->dec.input, SLOT_BUFFER, &streambuf);
|
||||
fd = mpp_buffer_get_fd(streambuf);
|
||||
regs->reg145_bitpl_ctrl_base = fd;
|
||||
regs->reg145_bitpl_ctrl_base |= (pic_param->stream_start_offset << 10);
|
||||
|
||||
regs->reg122.sw_strm1_start_bit = pic_param->stream_start_bit;
|
||||
#endif
|
||||
|
||||
/* calculate dct partition length here instead */
|
||||
if (pic_param->decMode == VP8HWD_VP8 && !pic_param->frame_type)
|
||||
extraBytesPacked += 7;
|
||||
@@ -436,16 +424,15 @@ MPP_RET hal_vp8d_vdpu2_gen_regs(void* hal, HalTaskInfo *task)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
RK_U32 mb_width = 0, mb_height = 0;
|
||||
#ifdef RKPLATFORM
|
||||
MppBuffer framebuf = NULL;
|
||||
RK_U8 *segmap_ptr = NULL;
|
||||
RK_U8 *probe_ptr = NULL;
|
||||
#endif
|
||||
VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
|
||||
VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
|
||||
DXVA_PicParams_VP8 *pic_param = (DXVA_PicParams_VP8 *)task->dec.syntax.data;
|
||||
|
||||
FUN_T("FUN_IN");
|
||||
|
||||
hal_vp8_init_hwcfg(ctx);
|
||||
mb_width = (pic_param->width + 15) >> 4;
|
||||
mb_height = (pic_param->height + 15) >> 4;
|
||||
@@ -455,7 +442,6 @@ MPP_RET hal_vp8d_vdpu2_gen_regs(void* hal, HalTaskInfo *task)
|
||||
regs->reg120.sw_pic_mb_w_ext = mb_width >> 9;
|
||||
regs->reg120.sw_pic_mb_h_ext = mb_height >> 8;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (!pic_param->frame_type) {
|
||||
segmap_ptr = mpp_buffer_get_ptr(ctx->seg_map);
|
||||
if (NULL != segmap_ptr) {
|
||||
@@ -505,7 +491,6 @@ MPP_RET hal_vp8d_vdpu2_gen_regs(void* hal, HalTaskInfo *task)
|
||||
((pic_param->stVP8Segments.segmentation_enabled +
|
||||
(pic_param->stVP8Segments.update_mb_segmentation_map << 1)) << 10);
|
||||
|
||||
#endif
|
||||
regs->reg57_enable_ctrl.sw_pic_inter_e = pic_param->frame_type;
|
||||
regs->reg50_dec_ctrl.sw_skip_mode = !pic_param->mb_no_coeff_skip;
|
||||
|
||||
@@ -587,37 +572,31 @@ MPP_RET hal_vp8d_vdpu2_gen_regs(void* hal, HalTaskInfo *task)
|
||||
MPP_RET hal_vp8d_vdpu2_start(void *hal, HalTaskInfo *task)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
RK_U32 i = 0;
|
||||
VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
|
||||
VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
|
||||
RK_U8 *p = ctx->regs;
|
||||
|
||||
RK_U32 *p = (RK_U32 *)ctx->regs;
|
||||
|
||||
FUN_T("FUN_IN");
|
||||
|
||||
for (i = 0; i < VP8D_REG_NUM; i++) {
|
||||
vp8h_dbg(VP8H_DBG_REG, "vp8d: regs[%02d]=%08X\n", i, *((RK_U32*)p));
|
||||
p += 4;
|
||||
}
|
||||
for (i = 0; i < VP8D_REG_NUM; i++)
|
||||
vp8h_dbg(VP8H_DBG_REG, "vp8d: regs[%02d]=%08X\n", i, p[i]);
|
||||
|
||||
ret = mpp_device_send_reg(ctx->dev_ctx, (RK_U32 *)regs, VP8D_REG_NUM);
|
||||
if (ret != 0) {
|
||||
if (ret) {
|
||||
mpp_err("mpp_device_send_reg Failed!!!\n");
|
||||
return MPP_ERR_VPUHW;
|
||||
}
|
||||
|
||||
FUN_T("FUN_OUT");
|
||||
#endif
|
||||
|
||||
(void)task;
|
||||
(void)hal;
|
||||
return ret;
|
||||
}
|
||||
|
||||
MPP_RET hal_vp8d_vdpu2_wait(void *hal, HalTaskInfo *task)
|
||||
{
|
||||
MPP_RET ret = MPP_OK;
|
||||
#ifdef RKPLATFORM
|
||||
VP8DRegSet_t reg_out;
|
||||
VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
|
||||
|
||||
@@ -625,8 +604,7 @@ MPP_RET hal_vp8d_vdpu2_wait(void *hal, HalTaskInfo *task)
|
||||
memset(®_out, 0, sizeof(VP8DRegSet_t));
|
||||
ret = mpp_device_wait_reg(ctx->dev_ctx, (RK_U32 *)®_out, VP8D_REG_NUM);
|
||||
FUN_T("FUN_OUT");
|
||||
#endif
|
||||
(void)hal;
|
||||
|
||||
(void)task;
|
||||
return ret;
|
||||
}
|
||||
|
@@ -2,6 +2,4 @@
|
||||
# ----------------------------------------------------------------------------
|
||||
# add mpp_device implement for hardware register transaction
|
||||
# ----------------------------------------------------------------------------
|
||||
if (RKPLATFORM)
|
||||
add_library(mpp_device STATIC mpp_device.c)
|
||||
endif(RKPLATFORM)
|
||||
|
@@ -4,12 +4,8 @@ include_directories(.)
|
||||
# ----------------------------------------------------------------------------
|
||||
# add mpp implement
|
||||
# ----------------------------------------------------------------------------
|
||||
if(RKPLATFORM)
|
||||
set(RKPLAT_VPU_LEGACY vpu.c)
|
||||
endif(RKPLATFORM)
|
||||
|
||||
set (MPP_LEGACY_SRC
|
||||
${RKPLAT_VPU_LEGACY}
|
||||
vpu.c
|
||||
vpu_api.cpp
|
||||
vpu_api_legacy.cpp
|
||||
vpu_mem_legacy.c
|
||||
@@ -37,11 +33,7 @@ set_target_properties(${VPU_SHARED} PROPERTIES VERSION ${MPP_VERSION})
|
||||
set_target_properties(${VPU_SHARED} PROPERTIES SOVERSION ${MPP_ABI_VERSION})
|
||||
endif()
|
||||
|
||||
if(RKPLATFORM)
|
||||
target_link_libraries(${VPU_SHARED} dl ${MPP_SHARED})
|
||||
else()
|
||||
target_link_libraries(${VPU_SHARED} ${MPP_SHARED})
|
||||
endif()
|
||||
|
||||
install(TARGETS ${VPU_STATIC} ${VPU_SHARED}
|
||||
ARCHIVE DESTINATION "${CMAKE_INSTALL_LIBDIR}"
|
||||
|
@@ -19,8 +19,6 @@
|
||||
#include "vpu.h"
|
||||
#include "ppOp.h"
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
namespace android
|
||||
{
|
||||
|
||||
@@ -58,7 +56,6 @@ status_t ppOpRelease(PP_OP_HANDLE hnd)
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
#if BUILD_PPOP_TEST
|
||||
#define SRC_WIDTH (1920)//(1920)
|
||||
|
@@ -17,7 +17,6 @@
|
||||
#ifndef _PPOP_H_
|
||||
#define _PPOP_H_
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
#include <sys/types.h>
|
||||
|
||||
typedef RK_S32 status_t;
|
||||
@@ -111,6 +110,6 @@ status_t ppOpSync(PP_OP_HANDLE hnd);
|
||||
status_t ppOpRelease(PP_OP_HANDLE hnd);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // _PPOP_H_
|
||||
|
||||
|
@@ -23,8 +23,6 @@
|
||||
|
||||
#include "vpu.h"
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
#include <sys/ioctl.h>
|
||||
#include <fcntl.h>
|
||||
#include <errno.h>
|
||||
@@ -254,63 +252,3 @@ RK_S32 VPUClientGetIOMMUStatus()
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
#else
|
||||
int VPUClientInit(VPU_CLIENT_TYPE type)
|
||||
{
|
||||
(void)type;
|
||||
return 0;
|
||||
}
|
||||
|
||||
RK_S32 VPUClientRelease(int socket)
|
||||
{
|
||||
(void)socket;
|
||||
return 0;
|
||||
}
|
||||
|
||||
RK_S32 VPUClientSendReg(int socket, RK_U32 *regs, RK_U32 nregs)
|
||||
{
|
||||
(void)socket;
|
||||
(void)regs;
|
||||
(void)nregs;
|
||||
return 0;
|
||||
}
|
||||
|
||||
RK_S32 VPUClientSendReg2(RK_S32 socket, RK_S32 offset, RK_S32 size, void *param)
|
||||
{
|
||||
(void)socket;
|
||||
(void)offset;
|
||||
(void)size;
|
||||
(void)param;
|
||||
return 0;
|
||||
}
|
||||
|
||||
RK_S32 VPUClientWaitResult(int socket, RK_U32 *regs, RK_U32 nregs, VPU_CMD_TYPE *cmd, RK_S32 *len)
|
||||
{
|
||||
(void)socket;
|
||||
(void)regs;
|
||||
(void)nregs;
|
||||
(void)cmd;
|
||||
(void)len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
RK_S32 VPUClientGetHwCfg(int socket, RK_U32 *cfg, RK_U32 cfg_size)
|
||||
{
|
||||
(void)socket;
|
||||
(void)cfg;
|
||||
(void)cfg_size;
|
||||
return 0;
|
||||
}
|
||||
|
||||
RK_U32 VPUCheckSupportWidth()
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
RK_S32 VPUClientGetIOMMUStatus()
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
@@ -17,10 +17,8 @@
|
||||
#define MODULE_TAG "vpu_api"
|
||||
|
||||
#include <string.h>
|
||||
#ifdef RKPLATFORM
|
||||
#include <dlfcn.h>
|
||||
#include <unistd.h>
|
||||
#endif
|
||||
|
||||
#include "mpp_log.h"
|
||||
#include "mpp_mem.h"
|
||||
@@ -198,7 +196,6 @@ vpu_api_control(VpuCodecContext *ctx, VPU_API_CMD cmdType, void *param)
|
||||
return api->control(ctx, cmdType, param);
|
||||
}
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
static const char *codec_paths[] = {
|
||||
"/vendor/lib/librk_vpuapi.so",
|
||||
"/system/lib/librk_vpuapi.so",
|
||||
@@ -263,24 +260,6 @@ static RK_S32 close_orign_vpu(VpuCodecContext **ctx)
|
||||
}
|
||||
return MPP_NOK;
|
||||
}
|
||||
#else
|
||||
RK_S32 check_orign_vpu()
|
||||
{
|
||||
return (MPP_NOK);
|
||||
}
|
||||
|
||||
RK_S32 open_orign_vpu(VpuCodecContext **ctx)
|
||||
{
|
||||
(void)ctx;
|
||||
return MPP_NOK;
|
||||
}
|
||||
|
||||
RK_S32 close_orign_vpu(VpuCodecContext **ctx)
|
||||
{
|
||||
(void)ctx;
|
||||
return MPP_NOK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* old libvpu path will input a NULL pointer in *ctx
|
||||
@@ -309,14 +288,9 @@ RK_S32 vpu_open_context(VpuCodecContext **ctx)
|
||||
mpp_env_get_u32("use_original", &force_original, 0);
|
||||
mpp_env_get_u32("use_mpp_mode", &force_mpp_mode, 0);
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
/* if there is no original vpuapi library force to mpp path */
|
||||
if (check_orign_vpu())
|
||||
force_mpp_mode = 1;
|
||||
#else
|
||||
/* simulation mode force mpp path */
|
||||
force_mpp_mode = 1;
|
||||
#endif
|
||||
|
||||
if (force_original) {
|
||||
/* force mpp mode here */
|
||||
|
@@ -16,9 +16,7 @@
|
||||
|
||||
#define MODULE_TAG "vpu_api_legacy"
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
#include <fcntl.h>
|
||||
#endif
|
||||
#include "string.h"
|
||||
|
||||
#include "mpp_log.h"
|
||||
@@ -216,8 +214,6 @@ RET:
|
||||
static int is_valid_dma_fd(int fd)
|
||||
{
|
||||
int ret = 1;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
/* detect input file handle */
|
||||
int fs_flag = fcntl(fd, F_GETFL, NULL);
|
||||
int fd_flag = fcntl(fd, F_GETFD, NULL);
|
||||
@@ -225,9 +221,7 @@ static int is_valid_dma_fd(int fd)
|
||||
if (fs_flag == -1 || fd_flag == -1) {
|
||||
ret = 0;
|
||||
}
|
||||
#else
|
||||
(void) fd;
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@@ -211,12 +211,12 @@ void release_vpu_memory_pool_allocator(vpu_display_mem_pool *ipool)
|
||||
RK_S32 VPUMemJudgeIommu()
|
||||
{
|
||||
int ret = 0;
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
if (VPUClientGetIOMMUStatus() > 0) {
|
||||
//mpp_err("media.used.iommu");
|
||||
ret = 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@@ -14,9 +14,7 @@
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
#include <fcntl.h>
|
||||
#endif
|
||||
#include <string.h>
|
||||
|
||||
#include "mpp_env.h"
|
||||
@@ -156,7 +154,6 @@ MppPlatformService::MppPlatformService()
|
||||
vcodec_type(0),
|
||||
vcodec_capability(0)
|
||||
{
|
||||
#ifdef RKPLATFORM
|
||||
/* judge vdpu support version */
|
||||
RK_S32 fd = -1;
|
||||
|
||||
@@ -252,7 +249,6 @@ MppPlatformService::MppPlatformService()
|
||||
vcodec_type &= ~(HAVE_VPU1 | HAVE_VPU2);
|
||||
|
||||
mpp_dbg(MPP_DBG_PLATFORM, "vcodec type %08x\n", vcodec_type);
|
||||
#endif
|
||||
}
|
||||
|
||||
MppPlatformService::~MppPlatformService()
|
||||
@@ -286,13 +282,11 @@ RK_U32 mpp_get_2d_hw_flag(void)
|
||||
{
|
||||
RK_U32 flag = 0;
|
||||
|
||||
#ifdef RKPLATFORM
|
||||
if (!access("/dev/rga", F_OK))
|
||||
flag |= HAVE_RGA;
|
||||
|
||||
if (!access("/dev/iep", F_OK))
|
||||
flag |= HAVE_IEP;
|
||||
#endif
|
||||
|
||||
return flag;
|
||||
}
|
||||
@@ -300,7 +294,7 @@ RK_U32 mpp_get_2d_hw_flag(void)
|
||||
const char *mpp_get_platform_dev_name(MppCtxType type, MppCodingType coding, RK_U32 platform)
|
||||
{
|
||||
const char *dev = NULL;
|
||||
#ifdef RKPLATFORM
|
||||
|
||||
if ((platform & HAVE_RKVDEC) && (type == MPP_CTX_DEC) &&
|
||||
(coding == MPP_VIDEO_CodingAVC ||
|
||||
coding == MPP_VIDEO_CodingHEVC ||
|
||||
@@ -325,11 +319,6 @@ const char *mpp_get_platform_dev_name(MppCtxType type, MppCodingType coding, RK_
|
||||
} else {
|
||||
dev = mpp_find_device(mpp_vpu_dev);
|
||||
}
|
||||
#else
|
||||
(void)type;
|
||||
(void)coding;
|
||||
(void)platform;
|
||||
#endif
|
||||
|
||||
return dev;
|
||||
}
|
||||
@@ -337,7 +326,6 @@ const char *mpp_get_platform_dev_name(MppCtxType type, MppCodingType coding, RK_
|
||||
const char *mpp_get_vcodec_dev_name(MppCtxType type, MppCodingType coding)
|
||||
{
|
||||
const char *dev = NULL;
|
||||
#ifdef RKPLATFORM
|
||||
RockchipSocType soc_type = MppPlatformService::get_instance()->get_soc_type();
|
||||
|
||||
switch (soc_type) {
|
||||
@@ -485,10 +473,6 @@ const char *mpp_get_vcodec_dev_name(MppCtxType type, MppCodingType coding)
|
||||
dev = mpp_get_platform_dev_name(type, coding, vcodec_type);
|
||||
} break;
|
||||
}
|
||||
#else
|
||||
(void)type;
|
||||
(void)coding;
|
||||
#endif
|
||||
|
||||
return dev;
|
||||
}
|
||||
|
Reference in New Issue
Block a user