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[hal_av1d_vdpu]: fix av1 dec err when afbc mode

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Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: Iac850d1155ca1126d16d5206a5b890d3bca04041
This commit is contained in:
Yandong Lin
2022-10-24 20:28:21 +08:00
committed by Herman Chen
parent 2109b2a8d9
commit 6593fd01e6
2 changed files with 30 additions and 10 deletions
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8
mpp/codec/dec/av1/av1d_parser.c
View File

@@ -104,7 +104,6 @@ static MPP_RET get_pixel_format(Av1CodecContext *ctx)
if (pix_fmt == MPP_FMT_BUTT)
return -1;
ctx->pix_fmt = pix_fmt;
s->bit_depth = bit_depth;
return ret;
@@ -606,16 +605,15 @@ static MPP_RET get_current_frame(Av1CodecContext *ctx)
if (MPP_FRAME_FMT_IS_FBC(s->cfg->base.out_fmt)) {
mpp_slots_set_prop(s->slots, SLOTS_HOR_ALIGN, hor_align_16);
if (s->bit_depth == 10) {
if (ctx->pix_fmt == MPP_FMT_YUV420SP)
if (ctx->pix_fmt == MPP_FMT_YUV420SP || ctx->pix_fmt == MPP_FMT_YUV420SP_10BIT)
ctx->pix_fmt = MPP_FMT_YUV420SP_10BIT;
else
mpp_err("422p 10bit no support");
}
mpp_frame_set_fmt(frame->f, ctx->pix_fmt | ((s->cfg->base.out_fmt & (MPP_FRAME_FBC_MASK))));
mpp_frame_set_offset_x(frame->f, 0);
mpp_frame_set_offset_y(frame->f, 8);
if (*compat_ext_fbc_buf_size)
mpp_frame_set_ver_stride(frame->f, MPP_ALIGN(ctx->height, 8) + 16);
mpp_frame_set_offset_y(frame->f, 0);
mpp_frame_set_ver_stride(frame->f, MPP_ALIGN(ctx->height, 8) + 28);
} else
mpp_frame_set_fmt(frame->f, ctx->pix_fmt);

32
mpp/hal/vpu/av1d/hal_av1d_vdpu.c
View File

@@ -2113,19 +2113,38 @@ MPP_RET vdpu_av1d_gen_regs(void *hal, HalTaskInfo *task)
// regs->vdpu_av1d_pp_cfg.swreg337.sw_pp_in_y_stride = hor_stride;
// regs->vdpu_av1d_pp_cfg.swreg337.sw_pp_in_c_stride = hor_stride;
if (ctx->fbc_en) {
RK_U32 vir_left = 0, vir_right = 0, vir_top = 0, vir_bottom = 0;
RK_U32 bypass_filter = !regs->swreg5.sw_superres_is_scaled &&
!regs->swreg5.sw_enable_cdef &&
!regs->swreg14.sw_filt_level0 &&
!regs->swreg15.sw_filt_level1 &&
!regs->swreg18.sw_lr_type;
regs->vdpu_av1d_pp_cfg.swreg329.sw_pp_out_y_stride = dxva->bitdepth > 8 ?
width * 2 : width;
regs->vdpu_av1d_pp_cfg.swreg329.sw_pp_out_c_stride = dxva->bitdepth > 8 ?
width * 2 : width;
regs->swreg58.sw_dec_axi_wd_id_e = 1;
regs->swreg58.sw_dec_axi_rd_id_e = 1;
regs->vdpu_av1d_pp_cfg.swreg320.sw_pp_out_tile_e = 1;
regs->vdpu_av1d_pp_cfg.swreg321.sw_pp_tile_size = 2;
RK_U32 vir_left = 0, vir_right = 0, vir_top = 0, vir_bottom = 0;
vir_left = 0;
if (((vir_left + width) % 16))
vir_right = 16 - ((vir_left + width) % 16);
else
vir_right = 0;
vir_top = 8;
if (!bypass_filter) {
if (16 - (56 % 16))
vir_top = 16 - (56 % 16);
else
vir_top = 0;
} else {
if (((64 - (height % 64))) % 16)
vir_top = 16 - (((64 - (height % 64))) % 16);
else
vir_top = 0;
}
if (((vir_top + height) % 16))
vir_bottom = 16 - ((vir_top + height) % 16);
@@ -2136,6 +2155,9 @@ MPP_RET vdpu_av1d_gen_regs(void *hal, HalTaskInfo *task)
regs->vdpu_av1d_pp_cfg.swreg503.sw_pp0_virtual_left = vir_left;
regs->vdpu_av1d_pp_cfg.swreg503.sw_pp0_virtual_bottom = vir_bottom;
regs->vdpu_av1d_pp_cfg.swreg503.sw_pp0_virtual_right = vir_right;
mpp_frame_set_offset_y(mframe, vir_top);
mpp_frame_set_ver_stride(mframe, vir_top + height + vir_bottom);
regs->vdpu_av1d_pp_cfg.swreg322.sw_pp_out_format = 3;
regs->vdpu_av1d_pp_cfg.swreg326.sw_pp_out_lu_base_lsb = mpp_buffer_get_fd(buffer);
regs->vdpu_av1d_pp_cfg.swreg328.sw_pp_out_ch_base_lsb = mpp_buffer_get_fd(buffer);
regs->vdpu_av1d_pp_cfg.swreg505.sw_pp0_afbc_tile_base_lsb = mpp_buffer_get_fd(buffer);
@@ -2149,9 +2171,9 @@ MPP_RET vdpu_av1d_gen_regs(void *hal, HalTaskInfo *task)
mpp_dev_set_reg_offset(p_hal->dev, 328, y_stride);
}
/*RK_U32 i = 0;
/* RK_U32 i = 0;
for (i = 0; i < sizeof(VdpuAv1dRegSet) / sizeof(RK_U32); i++)
mpp_log("regs[%04d]=%08X\n", i, ((RK_U32 *)regs)[i]);*/
mpp_log("regs[%04d]=%08X\n", i, ((RK_U32 *)regs)[i]); */
__RETURN: