diff --git a/inc/rk_venc_cmd.h b/inc/rk_venc_cmd.h
index 53a85a50..80c30ae6 100644
--- a/inc/rk_venc_cmd.h
+++ b/inc/rk_venc_cmd.h
@@ -418,6 +418,8 @@ typedef enum MppEncHwCfgChange_e {
     MPP_ENC_HW_CFG_CHANGE_AQ_STEP_I     = (1 << 4),
     MPP_ENC_HW_CFG_CHANGE_AQ_STEP_P     = (1 << 5),
     MPP_ENC_HW_CFG_CHANGE_MB_RC         = (1 << 6),
+    MPP_ENC_HW_CFG_CHANGE_CU_MODE_BIAS  = (1 << 8),
+    MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS  = (1 << 9),
     MPP_ENC_HW_CFG_CHANGE_ALL           = (0xFFFFFFFF),
 } MppEncHwCfgChange;
 
@@ -443,6 +445,32 @@ typedef struct MppEncHwCfg_t {
 
     /* vepu580 */
     RK_S32                  extra_buf;
+
+    /*
+     * block mode decision bias config
+     * 0 - intra32x32
+     * 1 - intra16x16
+     * 2 - intra8x8
+     * 3 - intra4x4
+     * 4 - inter64x64
+     * 5 - inter32x32
+     * 6 - inter16x16
+     * 7 - inter8x8
+     * value range 0 ~ 15, default : 8
+     * If the value is smaller then encoder will be more likely to encode corresponding block mode.
+     */
+    RK_S32                  mode_bias[8];
+
+    /*
+     * skip mode bias config
+     * skip_bias_en - enable flag for skip bias config
+     * skip_sad     - sad threshold for skip / non-skip
+     * skip_bias    - tendency for skip, value range 0 ~ 15, default : 8
+     *                If the value is smaller then encoder will be more likely to encode skip block.
+     */
+    RK_S32                  skip_bias_en;
+    RK_S32                  skip_sad;
+    RK_S32                  skip_bias;
 } MppEncHwCfg;
 
 /*
diff --git a/mpp/base/mpp_enc_cfg.cpp b/mpp/base/mpp_enc_cfg.cpp
index 58917d46..13213c4c 100644
--- a/mpp/base/mpp_enc_cfg.cpp
+++ b/mpp/base/mpp_enc_cfg.cpp
@@ -253,6 +253,10 @@ public:
     ENTRY(hw,   aq_step_i,      St,  RK_S32 *,          MPP_ENC_HW_CFG_CHANGE_AQ_STEP_I,        hw, aq_step_i) \
     ENTRY(hw,   aq_step_p,      St,  RK_S32 *,          MPP_ENC_HW_CFG_CHANGE_AQ_STEP_P,        hw, aq_step_p) \
     ENTRY(hw,   mb_rc_disable,  S32, RK_S32,            MPP_ENC_HW_CFG_CHANGE_MB_RC,            hw, mb_rc_disable) \
+    ENTRY(hw,   mode_bias,      St,  RK_S32 *,          MPP_ENC_HW_CFG_CHANGE_CU_MODE_BIAS,     hw, mode_bias) \
+    ENTRY(hw,   skip_bias_en,   S32, RK_S32,            MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS,     hw, skip_bias_en) \
+    ENTRY(hw,   skip_sad,       S32, RK_S32,            MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS,     hw, skip_sad) \
+    ENTRY(hw,   skip_bias,      S32, RK_S32,            MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS,     hw, skip_bias) \
     /* quality fine tuning config */ \
     ENTRY(tune, scene_mode,     S32, MppEncSceneMode,   MPP_ENC_TUNE_CFG_CHANGE_SCENE_MODE,     tune, scene_mode)
 
@@ -383,9 +387,17 @@ MppCfgInfoNode *MppEncCfgService::get_info_root()
 
 static void mpp_enc_cfg_set_default(MppEncCfgSet *cfg)
 {
+    RK_U32 i;
+
     cfg->prep.color = MPP_FRAME_SPC_UNSPECIFIED;
     cfg->prep.colorprim = MPP_FRAME_PRI_UNSPECIFIED;
     cfg->prep.colortrc = MPP_FRAME_TRC_UNSPECIFIED;
+
+    for (i = 0; i < MPP_ARRAY_ELEMS(cfg->hw.mode_bias); i++)
+        cfg->hw.mode_bias[i] = 8;
+
+    cfg->hw.skip_sad  = 8;
+    cfg->hw.skip_bias = 8;
 }
 
 MPP_RET mpp_enc_cfg_init(MppEncCfg *cfg)
diff --git a/mpp/codec/mpp_enc_impl.cpp b/mpp/codec/mpp_enc_impl.cpp
index 01e3e089..1b01c70d 100644
--- a/mpp/codec/mpp_enc_impl.cpp
+++ b/mpp/codec/mpp_enc_impl.cpp
@@ -762,6 +762,15 @@ MPP_RET mpp_enc_proc_hw_cfg(MppEncHwCfg *dst, MppEncHwCfg *src)
         if (change & MPP_ENC_HW_CFG_CHANGE_MB_RC)
             dst->mb_rc_disable = src->mb_rc_disable;
 
+        if (change & MPP_ENC_HW_CFG_CHANGE_CU_MODE_BIAS)
+            memcpy(dst->mode_bias, src->mode_bias, sizeof(dst->mode_bias));
+
+        if (change & MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS) {
+            dst->skip_bias_en = src->skip_bias_en;
+            dst->skip_sad = src->skip_sad;
+            dst->skip_bias = src->skip_bias;
+        }
+
         if (dst->qp_delta_row < 0 || dst->qp_delta_row_i < 0) {
             mpp_err("invalid hw qp delta row [%d:%d]\n",
                     dst->qp_delta_row_i, dst->qp_delta_row);
diff --git a/mpp/hal/rkenc/h264e/hal_h264e_vepu580.c b/mpp/hal/rkenc/h264e/hal_h264e_vepu580.c
index 60e77946..7947eb5b 100644
--- a/mpp/hal/rkenc/h264e/hal_h264e_vepu580.c
+++ b/mpp/hal/rkenc/h264e/hal_h264e_vepu580.c
@@ -265,6 +265,7 @@ static MPP_RET hal_h264e_vepu580_init(void *hal, MppEncHalCfg *cfg)
 
     {   /* setup default hardware config */
         MppEncHwCfg *hw = &cfg->cfg->hw;
+        RK_U32 i;
 
         hw->qp_delta_row_i  = 2;
         hw->qp_delta_row    = 2;
@@ -274,6 +275,12 @@ static MPP_RET hal_h264e_vepu580_init(void *hal, MppEncHalCfg *cfg)
         memcpy(hw->aq_thrd_p, h264_aq_tthd_default, sizeof(hw->aq_thrd_p));
         memcpy(hw->aq_step_i, h264_I_aq_step_default, sizeof(hw->aq_step_i));
         memcpy(hw->aq_step_p, h264_P_aq_step_default, sizeof(hw->aq_step_p));
+
+        for (i = 0; i < MPP_ARRAY_ELEMS(hw->mode_bias); i++)
+            hw->mode_bias[i] = 8;
+
+        hw->skip_sad  = 8;
+        hw->skip_bias = 8;
     }
     mpp_dev_multi_offset_init(&p->offsets, 24);
     p->osd_cfg.reg_cfg = p->offsets;
diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu580.c b/mpp/hal/rkenc/h265e/hal_h265e_vepu580.c
index 5a9658f4..ce05c8a5 100644
--- a/mpp/hal/rkenc/h265e/hal_h265e_vepu580.c
+++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu580.c
@@ -1237,6 +1237,12 @@ MPP_RET hal_h265e_v580_init(void *hal, MppEncHalCfg *cfg)
         memcpy(hw->aq_thrd_p, aq_thd_default, sizeof(hw->aq_thrd_p));
         memcpy(hw->aq_step_i, aq_qp_dealt_default, sizeof(hw->aq_step_i));
         memcpy(hw->aq_step_p, aq_qp_dealt_default, sizeof(hw->aq_step_p));
+
+        for (i = 0; i < MPP_ARRAY_ELEMS(hw->mode_bias); i++)
+            hw->mode_bias[i] = 8;
+
+        hw->skip_sad  = 8;
+        hw->skip_bias = 8;
     }
 
     ctx->tune = vepu580_h265e_tune_init(ctx);