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[vdu34x_hevc]: Fix error ref cfg issue

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when err_intra_mode is true no reconfig error ref pic reg or
ccu may be wait timeout

Change-Id: I25ce12524d831aa8daf8d0b778b81eb5dd4aabcb
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>
This commit is contained in:
sayon.chen
2022-07-15 14:10:28 +08:00
committed by Herman Chen
parent a2627ec998
commit 5f02c4950e
1 changed files with 12 additions and 11 deletions
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23
mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
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@@ -1067,7 +1067,6 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn)
hw_regs->common_addr.reg132_error_ref_base = hw_regs->h265d_addr.reg164_179_ref_base[i]; hw_regs->common_addr.reg132_error_ref_base = hw_regs->h265d_addr.reg164_179_ref_base[i];
reg_cxt->error_index = dxva_cxt->pp.RefPicList[i].Index7Bits; reg_cxt->error_index = dxva_cxt->pp.RefPicList[i].Index7Bits;
hw_regs->common.reg021.error_intra_mode = 0; hw_regs->common.reg021.error_intra_mode = 0;
} }
} else { } else {
hw_regs->h265d_addr.reg164_179_ref_base[i] = valid_ref; hw_regs->h265d_addr.reg164_179_ref_base[i] = valid_ref;
@@ -1091,19 +1090,21 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn)
if (dxva_cxt->pp.RefPicList[i].bPicEntry != 0xff && if (dxva_cxt->pp.RefPicList[i].bPicEntry != 0xff &&
dxva_cxt->pp.RefPicList[i].bPicEntry != 0x7f) { dxva_cxt->pp.RefPicList[i].bPicEntry != 0x7f) {
MppFrame mframe = NULL; if (!hw_regs->common.reg021.error_intra_mode) {
MppFrame mframe = NULL;
mpp_buf_slot_get_prop(reg_cxt->slots, mpp_buf_slot_get_prop(reg_cxt->slots,
dxva_cxt->pp.RefPicList[i].Index7Bits, dxva_cxt->pp.RefPicList[i].Index7Bits,
SLOT_BUFFER, &framebuf); SLOT_BUFFER, &framebuf);
mpp_buf_slot_get_prop(reg_cxt->slots, dxva_cxt->pp.RefPicList[i].Index7Bits, mpp_buf_slot_get_prop(reg_cxt->slots, dxva_cxt->pp.RefPicList[i].Index7Bits,
SLOT_FRAME_PTR, &mframe); SLOT_FRAME_PTR, &mframe);
if (framebuf == NULL || mpp_frame_get_errinfo(mframe)) { if (framebuf == NULL || mpp_frame_get_errinfo(mframe)) {
mv_buf = hal_bufs_get_buf(reg_cxt->cmv_bufs, reg_cxt->error_index); mv_buf = hal_bufs_get_buf(reg_cxt->cmv_bufs, reg_cxt->error_index);
hw_regs->h265d_addr.reg164_179_ref_base[i] = hw_regs->common_addr.reg132_error_ref_base; hw_regs->h265d_addr.reg164_179_ref_base[i] = hw_regs->common_addr.reg132_error_ref_base;
hw_regs->h265d_addr.reg181_196_colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]); hw_regs->h265d_addr.reg181_196_colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
}
} }
} else { } else {
mv_buf = hal_bufs_get_buf(reg_cxt->cmv_bufs, reg_cxt->error_index); mv_buf = hal_bufs_get_buf(reg_cxt->cmv_bufs, reg_cxt->error_index);