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feat[mpp_dec]: add control for select codec device

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Signed-off-by: Rimon Xu <rimon.xu@rock-chips.com>
Change-Id: I55cbbf1e2a2b4693325a27af83ae76020d6f4ac2
This commit is contained in:
Rimon Xu
2024-11-14 17:58:14 +08:00
committed by Herman Chen
parent 45b28c7a32
commit 5a8e1fa682
6 changed files with 16 additions and 2 deletions
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2
inc/rk_mpi_cmd.h
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@@ -108,6 +108,8 @@ typedef enum {
MPP_DEC_SET_ENABLE_MVC, /* enable MVC decoding*/ MPP_DEC_SET_ENABLE_MVC, /* enable MVC decoding*/
MPP_DEC_GET_THUMBNAIL_FRAME_INFO, /* update thumbnail frame info to user, for MPP_FRAME_THUMBNAIL_ONLY mode */ MPP_DEC_GET_THUMBNAIL_FRAME_INFO, /* update thumbnail frame info to user, for MPP_FRAME_THUMBNAIL_ONLY mode */
MPP_DEC_SET_DISABLE_DPB_CHECK, /* disable dpb discontinuous check */ MPP_DEC_SET_DISABLE_DPB_CHECK, /* disable dpb discontinuous check */
/* select codec mode */
MPP_DEC_SET_CODEC_MODE = CMD_MODULE_CODEC | CMD_CTX_ID_DEC | 0x14,
MPP_DEC_CMD_QUERY = CMD_MODULE_CODEC | CMD_CTX_ID_DEC | CMD_DEC_QUERY, MPP_DEC_CMD_QUERY = CMD_MODULE_CODEC | CMD_CTX_ID_DEC | CMD_DEC_QUERY,
/* query decoder runtime information for decode stage */ /* query decoder runtime information for decode stage */

1
mpp/base/mpp_dec_cfg.cpp
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@@ -107,6 +107,7 @@ public:
ENTRY(base, enable_mvc, U32, MPP_DEC_CFG_CHANGE_ENABLE_MVC, base, enable_mvc) \ ENTRY(base, enable_mvc, U32, MPP_DEC_CFG_CHANGE_ENABLE_MVC, base, enable_mvc) \
ENTRY(base, disable_dpb_chk, U32, MPP_DEC_CFG_CHANGE_DISABLE_DPB_CHECK, base, disable_dpb_chk) \ ENTRY(base, disable_dpb_chk, U32, MPP_DEC_CFG_CHANGE_DISABLE_DPB_CHECK, base, disable_dpb_chk) \
ENTRY(base, disable_thread, U32, MPP_DEC_CFG_CHANGE_DISABLE_THREAD, base, disable_thread) \ ENTRY(base, disable_thread, U32, MPP_DEC_CFG_CHANGE_DISABLE_THREAD, base, disable_thread) \
ENTRY(base, codec_mode, U32, MPP_DEC_CFG_CHANGE_CODEC_MODE, base, codec_mode) \
ENTRY(cb, pkt_rdy_cb, Ptr, MPP_DEC_CB_CFG_CHANGE_PKT_RDY, cb, pkt_rdy_cb) \ ENTRY(cb, pkt_rdy_cb, Ptr, MPP_DEC_CB_CFG_CHANGE_PKT_RDY, cb, pkt_rdy_cb) \
ENTRY(cb, pkt_rdy_ctx, Ptr, MPP_DEC_CB_CFG_CHANGE_PKT_RDY, cb, pkt_rdy_ctx) \ ENTRY(cb, pkt_rdy_ctx, Ptr, MPP_DEC_CB_CFG_CHANGE_PKT_RDY, cb, pkt_rdy_ctx) \
ENTRY(cb, pkt_rdy_cmd, S32, MPP_DEC_CB_CFG_CHANGE_PKT_RDY, cb, pkt_rdy_cmd) \ ENTRY(cb, pkt_rdy_cmd, S32, MPP_DEC_CB_CFG_CHANGE_PKT_RDY, cb, pkt_rdy_cmd) \

8
mpp/codec/mpp_dec.cpp
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@@ -541,6 +541,9 @@ MPP_RET mpp_dec_set_cfg(MppDecCfgSet *dst, MppDecCfgSet *src)
if (change & MPP_DEC_CFG_CHANGE_DISABLE_THREAD) if (change & MPP_DEC_CFG_CHANGE_DISABLE_THREAD)
dst_base->disable_thread = src_base->disable_thread; dst_base->disable_thread = src_base->disable_thread;
if (change & MPP_DEC_CFG_CHANGE_CODEC_MODE)
dst_base->codec_mode = src_base->codec_mode;
dst_base->change = change; dst_base->change = change;
src_base->change = 0; src_base->change = 0;
} }
@@ -1067,6 +1070,11 @@ MPP_RET mpp_dec_set_cfg_by_cmd(MppDecCfgSet *set, MpiCmd cmd, void *param)
cfg->change |= MPP_DEC_CFG_CHANGE_DISABLE_DPB_CHECK; cfg->change |= MPP_DEC_CFG_CHANGE_DISABLE_DPB_CHECK;
dec_dbg_func("disable dpb discontinuous check %d\n", cfg->disable_dpb_chk); dec_dbg_func("disable dpb discontinuous check %d\n", cfg->disable_dpb_chk);
} break; } break;
case MPP_DEC_SET_CODEC_MODE : {
cfg->codec_mode = (param) ? (*((RK_U32 *)param)) : (0);
cfg->change |= MPP_DEC_CFG_CHANGE_CODEC_MODE;
dec_dbg_func("force use codec device %d\n", cfg->codec_mode);
} break;
default : { default : {
mpp_err_f("unsupported cfg update cmd %x\n", cmd); mpp_err_f("unsupported cfg update cmd %x\n", cmd);
ret = MPP_NOK; ret = MPP_NOK;

2
mpp/hal/rkdec/h264d/hal_h264d_api.c
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@@ -260,7 +260,7 @@ MPP_RET hal_h264d_init(void *hal, MppHalCfg *cfg)
mpp_err_f("can not found H.264 decoder hardware on platform %x\n", vcodec_type); mpp_err_f("can not found H.264 decoder hardware on platform %x\n", vcodec_type);
return ret; return ret;
} }
mpp_env_get_u32("use_mpp_mode", &mode, MODE_NULL); mpp_env_get_u32("use_mpp_mode", &mode, cfg->cfg->base.codec_mode);
if (MODE_NULL == mode) { if (MODE_NULL == mode) {
MppDecBaseCfg *base = &cfg->cfg->base; MppDecBaseCfg *base = &cfg->cfg->base;

2
mpp/inc/mpp_dec_cfg.h
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@@ -42,6 +42,7 @@ typedef enum MppDecCfgChange_e {
MPP_DEC_CFG_CHANGE_DISABLE_DPB_CHECK = (1 << 20), MPP_DEC_CFG_CHANGE_DISABLE_DPB_CHECK = (1 << 20),
/* reserve high bit for global config */ /* reserve high bit for global config */
MPP_DEC_CFG_CHANGE_DISABLE_THREAD = (1 << 28), MPP_DEC_CFG_CHANGE_DISABLE_THREAD = (1 << 28),
MPP_DEC_CFG_CHANGE_CODEC_MODE = (1 << 29),
MPP_DEC_CFG_CHANGE_ALL = (0xFFFFFFFF), MPP_DEC_CFG_CHANGE_ALL = (0xFFFFFFFF),
} MppDecCfgChange; } MppDecCfgChange;
@@ -81,6 +82,7 @@ typedef struct MppDecBaseCfg_t {
RK_U32 enable_mvc; RK_U32 enable_mvc;
RK_U32 disable_dpb_chk; RK_U32 disable_dpb_chk;
RK_U32 disable_thread; RK_U32 disable_thread;
RK_U32 codec_mode;
} MppDecBaseCfg; } MppDecBaseCfg;
typedef enum MppDecCbCfgChange_e { typedef enum MppDecCbCfgChange_e {

3
mpp/mpp.cpp
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@@ -1271,7 +1271,8 @@ MPP_RET Mpp::control_dec(MpiCmd cmd, MppParam param)
case MPP_DEC_SET_ENABLE_DEINTERLACE : case MPP_DEC_SET_ENABLE_DEINTERLACE :
case MPP_DEC_SET_ENABLE_FAST_PLAY : case MPP_DEC_SET_ENABLE_FAST_PLAY :
case MPP_DEC_SET_ENABLE_MVC : case MPP_DEC_SET_ENABLE_MVC :
case MPP_DEC_SET_DISABLE_DPB_CHECK: { case MPP_DEC_SET_DISABLE_DPB_CHECK :
case MPP_DEC_SET_CODEC_MODE : {
/* /*
* These control may be set before mpp_init * These control may be set before mpp_init
* When this case happen record the config and wait for decoder init * When this case happen record the config and wait for decoder init