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fix[hal_h265e]: Amend 510 tid and sync cache

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Change-Id: I93f96a7da6d3caa183f4991a3a6901a6dc697b44
Signed-off-by: Yanjun Liao <yanjun.liao@rock-chips.com>
This commit is contained in:
Yanjun Liao
2024-05-28 11:47:15 +08:00
parent ae4baaf917
commit 50f108baf2
4 changed files with 12 additions and 3 deletions
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4
mpp/hal/rkenc/h265e/hal_h265e_vepu510.c
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@@ -23,6 +23,7 @@
#include "hal_h265e_debug.h" #include "hal_h265e_debug.h"
#include "hal_h265e_vepu510.h" #include "hal_h265e_vepu510.h"
#include "hal_h265e_vepu510_reg.h" #include "hal_h265e_vepu510_reg.h"
#include "hal_h265e_stream_amend.h"
#include "vepu5xx_common.h" #include "vepu5xx_common.h"
#include "vepu541_common.h" #include "vepu541_common.h"
@@ -2189,10 +2190,13 @@ MPP_RET hal_h265e_v510_ret_task(void *hal, HalEncTask *task)
Vepu510H265eFrmCfg *frm = ctx->frms[task_idx]; Vepu510H265eFrmCfg *frm = ctx->frms[task_idx];
Vepu510H265Fbk *fb = &frm->feedback; Vepu510H265Fbk *fb = &frm->feedback;
EncRcTaskInfo *rc_info = &task->rc_task->info; EncRcTaskInfo *rc_info = &task->rc_task->info;
RK_U32 offset = mpp_packet_get_length(enc_task->packet);
hal_h265e_enter(); hal_h265e_enter();
vepu510_h265_set_feedback(ctx, enc_task); vepu510_h265_set_feedback(ctx, enc_task);
mpp_buffer_sync_partial_begin(enc_task->output, offset, fb->out_strm_size);
hal_h265e_amend_temporal_id(task, fb->out_strm_size);
rc_info->sse = fb->sse_sum; rc_info->sse = fb->sse_sum;
rc_info->lvl64_inter_num = fb->st_lvl64_inter_num; rc_info->lvl64_inter_num = fb->st_lvl64_inter_num;

2
mpp/hal/rkenc/h265e/hal_h265e_vepu540c.c
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@@ -1637,10 +1637,12 @@ MPP_RET hal_h265e_v540c_ret_task(void *hal, HalEncTask *task)
HalEncTask *enc_task = task; HalEncTask *enc_task = task;
vepu540c_h265_fbk *fb = &ctx->feedback; vepu540c_h265_fbk *fb = &ctx->feedback;
EncRcTaskInfo *rc_info = &task->rc_task->info; EncRcTaskInfo *rc_info = &task->rc_task->info;
RK_U32 offset = mpp_packet_get_length(enc_task->packet);
hal_h265e_enter(); hal_h265e_enter();
vepu540c_h265_set_feedback(ctx, enc_task); vepu540c_h265_set_feedback(ctx, enc_task);
mpp_buffer_sync_partial_begin(enc_task->output, offset, fb->out_strm_size);
hal_h265e_amend_temporal_id(task, fb->out_strm_size); hal_h265e_amend_temporal_id(task, fb->out_strm_size);
rc_info->sse = fb->sse_sum; rc_info->sse = fb->sse_sum;

2
mpp/hal/rkenc/h265e/hal_h265e_vepu541.c
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@@ -2059,10 +2059,12 @@ MPP_RET hal_h265e_v541_ret_task(void *hal, HalEncTask *task)
HalEncTask *enc_task = task; HalEncTask *enc_task = task;
vepu541_h265_fbk *fb = &ctx->feedback; vepu541_h265_fbk *fb = &ctx->feedback;
EncRcTaskInfo *rc_info = &task->rc_task->info; EncRcTaskInfo *rc_info = &task->rc_task->info;
RK_U32 offset = mpp_packet_get_length(enc_task->packet);
hal_h265e_enter(); hal_h265e_enter();
vepu541_h265_set_feedback(ctx, enc_task); vepu541_h265_set_feedback(ctx, enc_task);
mpp_buffer_sync_partial_begin(enc_task->output, offset, fb->out_strm_size);
hal_h265e_amend_temporal_id(task, fb->out_strm_size); hal_h265e_amend_temporal_id(task, fb->out_strm_size);
rc_info->sse = fb->sse_sum; rc_info->sse = fb->sse_sum;

7
mpp/hal/rkenc/h265e/hal_h265e_vepu580.c
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@@ -3298,12 +3298,12 @@ MPP_RET hal_h265e_v580_ret_task(void *hal, HalEncTask *task)
Vepu580H265eFrmCfg *frm = ctx->frms[task_idx]; Vepu580H265eFrmCfg *frm = ctx->frms[task_idx];
Vepu580H265Fbk *fb = &frm->feedback; Vepu580H265Fbk *fb = &frm->feedback;
H265eSyntax_new *syn = (H265eSyntax_new *) enc_task->syntax.data; H265eSyntax_new *syn = (H265eSyntax_new *) enc_task->syntax.data;
RK_U32 offset = mpp_packet_get_length(enc_task->packet);
hal_h265e_enter(); hal_h265e_enter();
if (ctx->tile_parall_en) { if (ctx->tile_parall_en) {
RK_U32 i = 0, stream_len = 0; RK_U32 i = 0, stream_len = 0;
RK_U32 offset = mpp_packet_get_length(enc_task->packet);
void* ptr = mpp_packet_get_pos(enc_task->packet); void* ptr = mpp_packet_get_pos(enc_task->packet);
for (i = 0; i < ctx->tile_num; i ++) { for (i = 0; i < ctx->tile_num; i ++) {
@@ -3314,7 +3314,7 @@ MPP_RET hal_h265e_v580_ret_task(void *hal, HalEncTask *task)
MppBuffer buf = frm->hw_tile_stream[i - 1]; MppBuffer buf = frm->hw_tile_stream[i - 1];
RK_U8 *tile1_ptr = mpp_buffer_get_ptr(buf); RK_U8 *tile1_ptr = mpp_buffer_get_ptr(buf);
mpp_buffer_sync_ro_partial_begin(buf, 0, len); mpp_buffer_sync_partial_begin(buf, 0, len);
if (syn->sp.temporal_id && len > 5) if (syn->sp.temporal_id && len > 5)
tile1_ptr[5] = (tile1_ptr[5] & 0xf8) | ((syn->sp.temporal_id + 1) & 0x7); tile1_ptr[5] = (tile1_ptr[5] & 0xf8) | ((syn->sp.temporal_id + 1) & 0x7);
@@ -3325,7 +3325,7 @@ MPP_RET hal_h265e_v580_ret_task(void *hal, HalEncTask *task)
RK_U32 len = fb->out_strm_size; RK_U32 len = fb->out_strm_size;
RK_U8 *stream_ptr = (RK_U8 *) ptr; RK_U8 *stream_ptr = (RK_U8 *) ptr;
mpp_buffer_sync_ro_partial_begin(buf, offset, len); mpp_buffer_sync_partial_begin(buf, offset, len);
if (syn->sp.temporal_id) { if (syn->sp.temporal_id) {
stream_ptr[5] = (stream_ptr[5] & 0xf8) | ((syn->sp.temporal_id + 1) & 0x7); stream_ptr[5] = (stream_ptr[5] & 0xf8) | ((syn->sp.temporal_id + 1) & 0x7);
@@ -3336,6 +3336,7 @@ MPP_RET hal_h265e_v580_ret_task(void *hal, HalEncTask *task)
} }
} else { } else {
vepu580_h265_set_feedback(ctx, enc_task, ctx->tile_num - 1); vepu580_h265_set_feedback(ctx, enc_task, ctx->tile_num - 1);
mpp_buffer_sync_partial_begin(enc_task->output, offset, fb->out_strm_size);
hal_h265e_amend_temporal_id(task, fb->out_strm_size); hal_h265e_amend_temporal_id(task, fb->out_strm_size);
} }