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[jpegd]: adjust register configuration

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1. only if height is 8-pixel aligned but not 16-pixel aligned,
bit 20 of reg148 is enabled.
2. default output buffer size is set to 2*width*height.

Change-Id: Ib23e1530c4c6a6688c3f8e632ba3f0b8e2b3c352
Signed-off-by: timkingh.huang <timkingh.huang@rock-chips.com>
This commit is contained in:
timkingh.huang
2016-11-22 16:15:17 +08:00
parent 6aa0d635c9
commit 49a88d995e
3 changed files with 46 additions and 44 deletions
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8
mpp/codec/dec/jpeg/jpegd_parser.c
View File

@@ -2397,8 +2397,8 @@ MPP_RET jpegd_allocate_frame(JpegParserContext *ctx)
mpp_frame_set_fmt(pCtx->output_frame, fmt); mpp_frame_set_fmt(pCtx->output_frame, fmt);
mpp_frame_set_width(pCtx->output_frame, pCtx->pSyntax->frame.X); mpp_frame_set_width(pCtx->output_frame, pCtx->pSyntax->frame.X);
mpp_frame_set_height(pCtx->output_frame, pCtx->pSyntax->frame.Y); mpp_frame_set_height(pCtx->output_frame, pCtx->pSyntax->frame.Y);
mpp_frame_set_hor_stride(pCtx->output_frame, pCtx->pSyntax->frame.X); mpp_frame_set_hor_stride(pCtx->output_frame, pCtx->pSyntax->frame.hwX);
mpp_frame_set_ver_stride(pCtx->output_frame, pCtx->pSyntax->frame.Y); mpp_frame_set_ver_stride(pCtx->output_frame, pCtx->pSyntax->frame.hwY);
mpp_frame_set_pts(pCtx->output_frame, pCtx->pts); mpp_frame_set_pts(pCtx->output_frame, pCtx->pts);
if (pCtx->eos) if (pCtx->eos)
@@ -2407,9 +2407,9 @@ MPP_RET jpegd_allocate_frame(JpegParserContext *ctx)
mpp_buf_slot_get_unused(pCtx->frame_slots, &pCtx->frame_slot_index); mpp_buf_slot_get_unused(pCtx->frame_slots, &pCtx->frame_slot_index);
JPEGD_INFO_LOG("frame_slot_index:%d, X:%d, Y:%d", pCtx->frame_slot_index, pCtx->pSyntax->frame.X, pCtx->pSyntax->frame.Y); JPEGD_INFO_LOG("frame_slot_index:%d, X:%d, Y:%d", pCtx->frame_slot_index, pCtx->pSyntax->frame.X, pCtx->pSyntax->frame.Y);
value = 3;
mpp_slots_set_prop(pCtx->frame_slots, SLOTS_NUMERATOR, &value);
value = 2; value = 2;
mpp_slots_set_prop(pCtx->frame_slots, SLOTS_NUMERATOR, &value);
value = 1;
mpp_slots_set_prop(pCtx->frame_slots, SLOTS_DENOMINATOR, &value); mpp_slots_set_prop(pCtx->frame_slots, SLOTS_DENOMINATOR, &value);
mpp_buf_slot_set_prop(pCtx->frame_slots, pCtx->frame_slot_index, SLOT_FRAME, pCtx->output_frame); mpp_buf_slot_set_prop(pCtx->frame_slots, pCtx->frame_slot_index, SLOT_FRAME, pCtx->output_frame);
mpp_buf_slot_set_flag(pCtx->frame_slots, pCtx->frame_slot_index, SLOT_CODEC_USE); mpp_buf_slot_set_flag(pCtx->frame_slots, pCtx->frame_slot_index, SLOT_CODEC_USE);

21
mpp/hal/vpu/jpegd/hal_jpegd_reg.c
View File

@@ -1688,8 +1688,16 @@ JpegDecRet jpegd_configure_regs(JpegSyntaxParam *pSyntax, JpegHalContext *pCtx)
reg->reg122.sw_jpeg_filright_e = pSyntax->info.fillRight; reg->reg122.sw_jpeg_filright_e = pSyntax->info.fillRight;
reg->reg148.sw_slice_h = pSyntax->info.sliceHeight; reg->reg148.sw_slice_h = pSyntax->info.sliceHeight;
/* Set bit 20 and bit 21 of reg148 to 1, notifying hardware to decode jpeg including DRI segment */ /* Set bit 21 of reg148 to 1, notifying hardware to decode jpeg including DRI segment */
reg->reg148.sw_resver = 0x003000; reg->reg148.sw_syn_marker_e = 1;
/* tell hardware that height is 8-pixel aligned, but not 16-pixel aligned */
if ((pSyntax->frame.Y % 16) &&
(pSyntax->info.yCbCrMode == JPEGDEC_YUV422 ||
pSyntax->info.yCbCrMode == JPEGDEC_YUV444 ||
pSyntax->info.yCbCrMode == JPEGDEC_YUV411)) {
reg->reg148.sw_jpeg_height8_flag = 1;
}
/* Set JPEG operation mode */ /* Set JPEG operation mode */
if (pSyntax->info.operationType != JPEGDEC_PROGRESSIVE) { if (pSyntax->info.operationType != JPEGDEC_PROGRESSIVE) {
@@ -1698,11 +1706,6 @@ JpegDecRet jpegd_configure_regs(JpegSyntaxParam *pSyntax, JpegHalContext *pCtx)
reg->reg57_enable_ctrl.sw_pjpeg_e = 1; reg->reg57_enable_ctrl.sw_pjpeg_e = 1;
} }
/* Set needed progressive parameters */
if (pSyntax->info.operationType == JPEGDEC_PROGRESSIVE) { // TODO: unsupported so far
JPEGD_INFO_LOG("JPEGDEC_PROGRESSIVE");
}
if (pSyntax->info.operationType == JPEGDEC_BASELINE) { if (pSyntax->info.operationType == JPEGDEC_BASELINE) {
/* write "length amounts" */ /* write "length amounts" */
JPEGD_VERBOSE_LOG("Write VLC length amounts to register\n"); JPEGD_VERBOSE_LOG("Write VLC length amounts to register\n");
@@ -1759,14 +1762,12 @@ JpegDecRet jpegd_configure_regs(JpegSyntaxParam *pSyntax, JpegHalContext *pCtx)
if (pSyntax->info.operationType == JPEGDEC_BASELINE) { if (pSyntax->info.operationType == JPEGDEC_BASELINE) {
/* Luminance output */ /* Luminance output */
JPEGD_INFO_LOG("INTERNAL: Set LUMA OUTPUT data base address\n");
JPEGD_INFO_LOG("Luma virtual: %p, phy_addr: %x\n", pSyntax->asicBuff.outLumaBuffer.vir_addr, JPEGD_INFO_LOG("Luma virtual: %p, phy_addr: %x\n", pSyntax->asicBuff.outLumaBuffer.vir_addr,
pSyntax->asicBuff.outLumaBuffer.phy_addr); pSyntax->asicBuff.outLumaBuffer.phy_addr);
reg->reg63_dec_out_base = pSyntax->asicBuff.outLumaBuffer.phy_addr; reg->reg63_dec_out_base = pSyntax->asicBuff.outLumaBuffer.phy_addr;
/* Chrominance output */ /* Chrominance output */
if (pSyntax->image.sizeChroma) { if (pSyntax->image.sizeChroma) {
JPEGD_INFO_LOG("INTERNAL: Set CHROMA OUTPUT data base address\n");
JPEGD_INFO_LOG("Chroma virtual: %p, phy_addr: %x\n", pSyntax->asicBuff.outChromaBuffer.vir_addr, JPEGD_INFO_LOG("Chroma virtual: %p, phy_addr: %x\n", pSyntax->asicBuff.outChromaBuffer.vir_addr,
pSyntax->asicBuff.outChromaBuffer.phy_addr); pSyntax->asicBuff.outChromaBuffer.phy_addr);
reg->reg131_jpg_ch_out_base = pSyntax->asicBuff.outChromaBuffer.phy_addr; reg->reg131_jpg_ch_out_base = pSyntax->asicBuff.outChromaBuffer.phy_addr;
@@ -1779,10 +1780,8 @@ JpegDecRet jpegd_configure_regs(JpegSyntaxParam *pSyntax, JpegHalContext *pCtx)
} }
pSyntax->info.sliceStartCount = 1; pSyntax->info.sliceStartCount = 1;
//pSyntax->asicRunning = 1;
/* Enable jpeg mode and set slice mode */ /* Enable jpeg mode and set slice mode */
JPEGD_VERBOSE_LOG("Enable jpeg\n");
reg->reg57_enable_ctrl.sw_dec_e = 1; reg->reg57_enable_ctrl.sw_dec_e = 1;
FUN_TEST("Exit"); FUN_TEST("Exit");

61
mpp/hal/vpu/jpegd/hal_jpegd_reg.h
View File

@@ -92,7 +92,7 @@ typedef struct JpegRegSet {
} reg2; } reg2;
struct { struct {
RK_U32 sw_pp_color_coefff : 8; RK_U32 sw_pp_color_coefff : 8;
} reg3; } reg3;
struct { struct {
@@ -182,7 +182,7 @@ typedef struct JpegRegSet {
struct { struct {
RK_U32 sw_pp_out_width : 11; RK_U32 sw_pp_out_width : 11;
RK_U32 sw_reserved_1 : 5; RK_U32 sw_reserved_1 : 5;
RK_U32 sw_pp_out_height : 11; RK_U32 sw_pp_out_height : 11;
} reg35; } reg35;
@@ -266,10 +266,10 @@ typedef struct JpegRegSet {
} reg50_dec_ctrl; } reg50_dec_ctrl;
struct { struct {
RK_U32 sw_stream_len : 24; RK_U32 sw_stream_len : 24;
RK_U32 reserve1 : 1; RK_U32 reserve1 : 1;
RK_U32 sw_init_qp : 6; RK_U32 sw_init_qp : 6;
RK_U32 reserve2 : 1; RK_U32 reserve2 : 1;
} reg51_stream_info; } reg51_stream_info;
struct { struct {
@@ -292,20 +292,20 @@ typedef struct JpegRegSet {
} reg54_endian; } reg54_endian;
struct { struct {
RK_U32 sw_dec_irq : 1; RK_U32 sw_dec_irq : 1;
RK_U32 sw_dec_irq_dis : 1; RK_U32 sw_dec_irq_dis : 1;
RK_U32 reserve0 : 2; RK_U32 reserve0 : 2;
RK_U32 sw_dec_rdy_int : 1; RK_U32 sw_dec_rdy_int : 1;
RK_U32 sw_dec_bus_int : 1; RK_U32 sw_dec_bus_int : 1;
RK_U32 sw_dec_buffer_int : 1; RK_U32 sw_dec_buffer_int : 1;
RK_U32 reserve1 : 1; RK_U32 reserve1 : 1;
RK_U32 sw_dec_aso_int : 1; RK_U32 sw_dec_aso_int : 1;
RK_U32 sw_dec_slice_int : 1; RK_U32 sw_dec_slice_int : 1;
RK_U32 sw_dec_pic_inf : 1; RK_U32 sw_dec_pic_inf : 1;
RK_U32 reserve2 : 1; RK_U32 reserve2 : 1;
RK_U32 sw_dec_error_int: 1; RK_U32 sw_dec_error_int : 1;
RK_U32 sw_dec_timeout : 1; RK_U32 sw_dec_timeout : 1;
RK_U32 reserve3 : 18; RK_U32 reserve3 : 18;
} reg55_Interrupt; } reg55_Interrupt;
struct { struct {
@@ -331,7 +331,7 @@ typedef struct JpegRegSet {
RK_U32 sw_write_mvs_e : 1; RK_U32 sw_write_mvs_e : 1;
RK_U32 sw_sorenson_e : 1; RK_U32 sw_sorenson_e : 1;
RK_U32 sw_fwd_interlace_e : 1; RK_U32 sw_fwd_interlace_e : 1;
RK_U32 sw_pic_topfield_e : 1 ; RK_U32 sw_pic_topfield_e : 1;
RK_U32 sw_pic_inter_e : 1; RK_U32 sw_pic_inter_e : 1;
RK_U32 sw_pic_b_e : 1; RK_U32 sw_pic_b_e : 1;
RK_U32 sw_pic_fieldmode_e : 1; RK_U32 sw_pic_fieldmode_e : 1;
@@ -342,10 +342,10 @@ typedef struct JpegRegSet {
RK_U32 sw_ch_8pix_ileav_e : 1; RK_U32 sw_ch_8pix_ileav_e : 1;
RK_U32 sw_start_code_e : 1; RK_U32 sw_start_code_e : 1;
RK_U32 resever1 : 8; RK_U32 resever1 : 8;
RK_U32 sw_dec_ahb_hlock_e : 1; RK_U32 sw_dec_ahb_hlock_e : 1;
} reg57_enable_ctrl; } reg57_enable_ctrl;
RK_U32 reg58_soft_rest; RK_U32 reg58_soft_rest;
struct { struct {
RK_U32 resever : 2; RK_U32 resever : 2;
@@ -448,7 +448,7 @@ typedef struct JpegRegSet {
struct { struct {
RK_U32 sw_stream1_len : 24; RK_U32 sw_stream1_len : 24;
RK_U32 sw_coeffs_part_am : 4; RK_U32 sw_coeffs_part_am : 4;
RK_U32 sw_resever : 4; RK_U32 sw_reserved : 4;
} reg124; } reg124;
struct { struct {
@@ -516,7 +516,7 @@ typedef struct JpegRegSet {
RK_U32 sw_filt_ref_adj_2 : 7; RK_U32 sw_filt_ref_adj_2 : 7;
RK_U32 sw_filt_ref_adj_1 : 7; RK_U32 sw_filt_ref_adj_1 : 7;
RK_U32 sw_filt_ref_adj_0 : 7; RK_U32 sw_filt_ref_adj_0 : 7;
RK_U32 sw_resver : 4; RK_U32 sw_reserved : 4;
} reg133; } reg133;
struct { struct {
@@ -631,8 +631,11 @@ typedef struct JpegRegSet {
RK_U32 reg_dct_strm1_base[2]; RK_U32 reg_dct_strm1_base[2];
struct { struct {
RK_U32 sw_slice_h : 8; RK_U32 sw_slice_h : 8;
RK_U32 sw_resver : 24; RK_U32 sw_reserved_1 : 12;
RK_U32 sw_jpeg_height8_flag : 1;
RK_U32 sw_syn_marker_e : 1;
RK_U32 sw_reserved_2 : 10;
} reg148; } reg148;
RK_U32 reg149_segment_map_base; RK_U32 reg149_segment_map_base;
@@ -643,21 +646,21 @@ typedef struct JpegRegSet {
RK_U32 sw_dct_start_bit_5 : 6; RK_U32 sw_dct_start_bit_5 : 6;
RK_U32 sw_dct_start_bit_4 : 6; RK_U32 sw_dct_start_bit_4 : 6;
RK_U32 sw_dct_start_bit_3 : 6; RK_U32 sw_dct_start_bit_3 : 6;
RK_U32 sw_resver : 2; RK_U32 sw_reserved : 2;
} reg150; } reg150;
struct { struct {
RK_U32 sw_quant_3 : 11; RK_U32 sw_quant_3 : 11;
RK_U32 sw_quant_2 : 11; RK_U32 sw_quant_2 : 11;
RK_U32 sw_quant_delta_3 : 5; RK_U32 sw_quant_delta_3 : 5;
RK_U32 sw_quant_delta_2 : 5; RK_U32 sw_quant_delta_2 : 5;
} reg151; } reg151;
struct { struct {
RK_U32 sw_quant_5 : 11; RK_U32 sw_quant_5 : 11;
RK_U32 sw_quant_4 : 11; RK_U32 sw_quant_4 : 11;
RK_U32 sw_quant_delta_4 : 5; RK_U32 sw_quant_delta_4 : 5;
RK_U32 sw_resver : 5; RK_U32 sw_reserved : 5;
} reg152; } reg152;
struct { struct {