mirror of
https://github.com/nyanmisaka/mpp.git
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[format]: format coding style
Change-Id: I3d0e081f6636ca8162df4bda68618ec0ba37e7ae Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
This commit is contained in:
@@ -90,13 +90,11 @@ private:
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RK_U32 node_count;
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RK_U32 node_count;
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public:
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public:
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static MppMetaService *get_instance()
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static MppMetaService *get_instance() {
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{
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static MppMetaService instance;
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static MppMetaService instance;
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return &instance;
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return &instance;
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}
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}
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static Mutex *get_lock()
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static Mutex *get_lock() {
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{
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static Mutex lock;
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static Mutex lock;
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return &lock;
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return &lock;
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}
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}
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@@ -741,7 +741,7 @@ H264EncRet H264EncStrmEncode(H264ECtx *pEncInst, const H264EncIn * pEncIn,
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RK_S32 EncAsicCheckHwStatus(asicData_s *asic)
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RK_S32 EncAsicCheckHwStatus(asicData_s *asic)
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{
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{
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RK_S32 ret = ASIC_STATUS_FRAME_READY;
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RK_S32 ret = ASIC_STATUS_FRAME_READY;
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/*
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/*
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RK_U32 status = asic->regs.hw_status;
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RK_U32 status = asic->regs.hw_status;
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if (status & ASIC_STATUS_ERROR) {
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if (status & ASIC_STATUS_ERROR) {
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@@ -753,7 +753,7 @@ RK_S32 EncAsicCheckHwStatus(asicData_s *asic)
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} else {
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} else {
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ret = ASIC_STATUS_BUFF_FULL;
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ret = ASIC_STATUS_BUFF_FULL;
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}
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}
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*/
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*/
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return ret;
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return ret;
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}
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}
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@@ -87,7 +87,7 @@ typedef struct h264e_feedback_t {
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/* for VEPU future extansion */
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/* for VEPU future extansion */
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//TODO: add nal size table feedback
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//TODO: add nal size table feedback
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}h264e_feedback;
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} h264e_feedback;
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typedef struct h264e_control_extra_info_cfg_t {
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typedef struct h264e_control_extra_info_cfg_t {
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@@ -1484,7 +1484,7 @@ static MPP_RET hal_h264e_rkv_allocate_buffers(h264e_hal_context *ctx, h264e_synt
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{
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{
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RK_S32 k = 0;
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RK_S32 k = 0;
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h264e_hal_rkv_buffers *buffers = (h264e_hal_rkv_buffers *)ctx->buffers;
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h264e_hal_rkv_buffers *buffers = (h264e_hal_rkv_buffers *)ctx->buffers;
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RK_U32 num_mbs_oneframe = (syn->pic_luma_width+15)/16 * ((syn->pic_luma_height+15)/16);
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RK_U32 num_mbs_oneframe = (syn->pic_luma_width + 15) / 16 * ((syn->pic_luma_height + 15) / 16);
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RK_U32 frame_size = ((syn->pic_luma_width + 15) & (~15)) * ((syn->pic_luma_height + 15) & (~15)) * 3 / 2;
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RK_U32 frame_size = ((syn->pic_luma_width + 15) & (~15)) * ((syn->pic_luma_height + 15) & (~15)) * 3 / 2;
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h264e_hal_rkv_dpb_ctx *dpb_ctx = (h264e_hal_rkv_dpb_ctx *)ctx->dpb_ctx;
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h264e_hal_rkv_dpb_ctx *dpb_ctx = (h264e_hal_rkv_dpb_ctx *)ctx->dpb_ctx;
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h264e_hal_rkv_frame *frame_buf = dpb_ctx->frame_buf;
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h264e_hal_rkv_frame *frame_buf = dpb_ctx->frame_buf;
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@@ -1498,7 +1498,7 @@ static MPP_RET hal_h264e_rkv_allocate_buffers(h264e_hal_context *ctx, h264e_synt
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}
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}
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}
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}
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if(syn->preproc_en || (test_cfg && test_cfg->preproc)) {
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if (syn->preproc_en || (test_cfg && test_cfg->preproc)) {
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for (k = 0; k < 2; k++) {
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for (k = 0; k < 2; k++) {
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if (MPP_OK != mpp_buffer_get(buffers->hw_buf_grp[H264E_HAL_RKV_BUF_GRP_PP], &buffers->hw_pp_buf[k], frame_size)) {
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if (MPP_OK != mpp_buffer_get(buffers->hw_buf_grp[H264E_HAL_RKV_BUF_GRP_PP], &buffers->hw_pp_buf[k], frame_size)) {
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mpp_err("hw_pp_buf[%d] get failed", k);
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mpp_err("hw_pp_buf[%d] get failed", k);
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@@ -1509,9 +1509,9 @@ static MPP_RET hal_h264e_rkv_allocate_buffers(h264e_hal_context *ctx, h264e_synt
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}
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}
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}
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}
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if(!all_intra_mode) {
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if (!all_intra_mode) {
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for (k = 0; k < 2; k++) {
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for (k = 0; k < 2; k++) {
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if (MPP_OK != mpp_buffer_get(buffers->hw_buf_grp[H264E_HAL_RKV_BUF_GRP_DSP], &buffers->hw_dsp_buf[k], frame_size/16)) {
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if (MPP_OK != mpp_buffer_get(buffers->hw_buf_grp[H264E_HAL_RKV_BUF_GRP_DSP], &buffers->hw_dsp_buf[k], frame_size / 16)) {
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mpp_err("hw_dsp_buf[%d] get failed", k);
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mpp_err("hw_dsp_buf[%d] get failed", k);
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return MPP_ERR_MALLOC;
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return MPP_ERR_MALLOC;
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} else {
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} else {
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@@ -1520,21 +1520,21 @@ static MPP_RET hal_h264e_rkv_allocate_buffers(h264e_hal_context *ctx, h264e_synt
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}
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}
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}
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}
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#if 0 //default setting
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#if 0 //default setting
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RK_U32 num_mei_oneframe = (syn->pic_luma_width+255)/256 * ((syn->pic_luma_height+15)/16);
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RK_U32 num_mei_oneframe = (syn->pic_luma_width + 255) / 256 * ((syn->pic_luma_height + 15) / 16);
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for (k = 0; k < RKV_H264E_LINKTABLE_FRAME_NUM; k++) {
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for (k = 0; k < RKV_H264E_LINKTABLE_FRAME_NUM; k++) {
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if (MPP_OK != mpp_buffer_get(buffers->hw_buf_grp[H264E_HAL_RKV_BUF_GRP_MEI], &buffers->hw_mei_buf[k], num_mei_oneframe*16*4)) {
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if (MPP_OK != mpp_buffer_get(buffers->hw_buf_grp[H264E_HAL_RKV_BUF_GRP_MEI], &buffers->hw_mei_buf[k], num_mei_oneframe * 16 * 4)) {
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mpp_err("hw_mei_buf[%d] get failed", k);
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mpp_err("hw_mei_buf[%d] get failed", k);
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return MPP_ERR_MALLOC;
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return MPP_ERR_MALLOC;
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} else {
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} else {
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h264e_hal_log_detail("hw_mei_buf[%d] %p done, fd %d", k, buffers->hw_mei_buf[k], mpp_buffer_get_fd(buffers->hw_mei_buf[k]));
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h264e_hal_log_detail("hw_mei_buf[%d] %p done, fd %d", k, buffers->hw_mei_buf[k], mpp_buffer_get_fd(buffers->hw_mei_buf[k]));
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}
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}
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}
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}
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#endif
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#endif
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if(syn->roi_en || (test_cfg && test_cfg->roi)) {
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if (syn->roi_en || (test_cfg && test_cfg->roi)) {
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for (k = 0; k < RKV_H264E_LINKTABLE_FRAME_NUM; k++) {
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for (k = 0; k < RKV_H264E_LINKTABLE_FRAME_NUM; k++) {
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if (MPP_OK != mpp_buffer_get(buffers->hw_buf_grp[H264E_HAL_RKV_BUF_GRP_ROI], &buffers->hw_roi_buf[k], num_mbs_oneframe*1)) {
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if (MPP_OK != mpp_buffer_get(buffers->hw_buf_grp[H264E_HAL_RKV_BUF_GRP_ROI], &buffers->hw_roi_buf[k], num_mbs_oneframe * 1)) {
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mpp_err("hw_roi_buf[%d] get failed", k);
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mpp_err("hw_roi_buf[%d] get failed", k);
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return MPP_ERR_MALLOC;
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return MPP_ERR_MALLOC;
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} else {
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} else {
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@@ -1556,9 +1556,9 @@ static MPP_RET hal_h264e_rkv_allocate_buffers(h264e_hal_context *ctx, h264e_synt
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}
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}
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}
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}
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if(syn->osd_mode || (test_cfg && test_cfg->osd)) {
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if (syn->osd_mode || (test_cfg && test_cfg->osd)) {
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for (k = 0; k < RKV_H264E_LINKTABLE_FRAME_NUM; k++) {
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for (k = 0; k < RKV_H264E_LINKTABLE_FRAME_NUM; k++) {
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if (MPP_OK != mpp_buffer_get(buffers->hw_buf_grp[H264E_HAL_RKV_BUF_GRP_REC], &buffers->hw_osd_buf[k], num_mbs_oneframe*256)) {
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if (MPP_OK != mpp_buffer_get(buffers->hw_buf_grp[H264E_HAL_RKV_BUF_GRP_REC], &buffers->hw_osd_buf[k], num_mbs_oneframe * 256)) {
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mpp_err("hw_osd_buf[%d] get failed", buffers->hw_osd_buf[k]);
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mpp_err("hw_osd_buf[%d] get failed", buffers->hw_osd_buf[k]);
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return MPP_ERR_MALLOC;
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return MPP_ERR_MALLOC;
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} else {
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} else {
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@@ -2666,8 +2666,8 @@ static MPP_RET hal_h264e_rkv_validate_syntax(h264e_syntax *syn, h264e_hal_csp_in
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syn->input_cr_addr = syn->input_luma_addr;
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syn->input_cr_addr = syn->input_luma_addr;
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H264E_HAL_VALIDATE_NEQ(syn->input_image_format, "input_image_format", H264E_RKV_CSP_NONE);
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H264E_HAL_VALIDATE_NEQ(syn->input_image_format, "input_image_format", H264E_RKV_CSP_NONE);
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if(syn->frame_coding_type==1) {/* ASIC_INTRA */
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if (syn->frame_coding_type == 1) { /* ASIC_INTRA */
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if(gop_start)
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if (gop_start)
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syn->frame_coding_type = RKVENC_FRAME_TYPE_IDR;
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syn->frame_coding_type = RKVENC_FRAME_TYPE_IDR;
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else
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else
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syn->frame_coding_type = RKVENC_FRAME_TYPE_I;
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syn->frame_coding_type = RKVENC_FRAME_TYPE_I;
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@@ -2682,30 +2682,30 @@ static MPP_RET hal_h264e_rkv_validate_syntax(h264e_syntax *syn, h264e_hal_csp_in
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MPP_RET hal_h264e_rkv_set_rc_regs(h264e_rkv_reg_set *regs, h264e_syntax *syn,
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MPP_RET hal_h264e_rkv_set_rc_regs(h264e_rkv_reg_set *regs, h264e_syntax *syn,
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h264e_hal_rkv_coveragetest_cfg *test)
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h264e_hal_rkv_coveragetest_cfg *test)
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{
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{
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if(test && test->mbrc) {
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if (test && test->mbrc) {
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RK_U32 num_mbs_oneframe = (syn->pic_luma_width+15)/16 * ((syn->pic_luma_height+15)/16);
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RK_U32 num_mbs_oneframe = (syn->pic_luma_width + 15) / 16 * ((syn->pic_luma_height + 15) / 16);
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RK_U32 frame_target_bitrate = (syn->pic_luma_width*syn->pic_luma_height/1920/1080)*10000000/8; //Bytes
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RK_U32 frame_target_bitrate = (syn->pic_luma_width * syn->pic_luma_height / 1920 / 1080) * 10000000 / 8; //Bytes
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RK_U32 frame_target_size = frame_target_bitrate/syn->keyframe_max_interval;
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RK_U32 frame_target_size = frame_target_bitrate / syn->keyframe_max_interval;
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RK_U32 mb_target_size = frame_target_size/num_mbs_oneframe;
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RK_U32 mb_target_size = frame_target_size / num_mbs_oneframe;
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RK_U32 aq_strength = 2;
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RK_U32 aq_strength = 2;
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mpp_log("---- test-mbrc ----");
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mpp_log("---- test-mbrc ----");
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regs->swreg46.rc_en = 1;
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regs->swreg46.rc_en = 1;
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regs->swreg46.rc_mode = 1; //0:frame/slice rc; 1:mbrc
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regs->swreg46.rc_mode = 1; //0:frame/slice rc; 1:mbrc
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regs->swreg46.aqmode_en = 1;
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regs->swreg46.aqmode_en = 1;
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regs->swreg46.aq_strg = (RK_U32)(aq_strength*1.0397*256);
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regs->swreg46.aq_strg = (RK_U32)(aq_strength * 1.0397 * 256);
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regs->swreg46.Reserved = 0x0;
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regs->swreg46.Reserved = 0x0;
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regs->swreg46.rc_ctu_num = (syn->pic_luma_width+15)/16;
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regs->swreg46.rc_ctu_num = (syn->pic_luma_width + 15) / 16;
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regs->swreg47.bits_error0 = ((mb_target_size >> 4) *num_mbs_oneframe / 2) * -192; //sw_bits_error[0];
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regs->swreg47.bits_error0 = ((mb_target_size >> 4) * num_mbs_oneframe / 2) * -192; //sw_bits_error[0];
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regs->swreg47.bits_error1 = ((mb_target_size >> 4) *num_mbs_oneframe / 2) * -144; //sw_bits_error[1];
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regs->swreg47.bits_error1 = ((mb_target_size >> 4) * num_mbs_oneframe / 2) * -144; //sw_bits_error[1];
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regs->swreg48.bits_error2 = ((mb_target_size >> 4) *num_mbs_oneframe / 2) * -96; //sw_bits_error[2];
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regs->swreg48.bits_error2 = ((mb_target_size >> 4) * num_mbs_oneframe / 2) * -96; //sw_bits_error[2];
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regs->swreg48.bits_error3 = ((mb_target_size >> 4) *num_mbs_oneframe / 2) * -16; //sw_bits_error[3];
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regs->swreg48.bits_error3 = ((mb_target_size >> 4) * num_mbs_oneframe / 2) * -16; //sw_bits_error[3];
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regs->swreg49.bits_error4 = ((mb_target_size >> 4) *num_mbs_oneframe / 2) * 16; //sw_bits_error[4];
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regs->swreg49.bits_error4 = ((mb_target_size >> 4) * num_mbs_oneframe / 2) * 16; //sw_bits_error[4];
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regs->swreg49.bits_error5 = ((mb_target_size >> 4) *num_mbs_oneframe / 2) * 96; //sw_bits_error[5];
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regs->swreg49.bits_error5 = ((mb_target_size >> 4) * num_mbs_oneframe / 2) * 96; //sw_bits_error[5];
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regs->swreg50.bits_error6 = ((mb_target_size >> 4) *num_mbs_oneframe / 2) * 144; //sw_bits_error[6];
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regs->swreg50.bits_error6 = ((mb_target_size >> 4) * num_mbs_oneframe / 2) * 144; //sw_bits_error[6];
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regs->swreg50.bits_error7 = ((mb_target_size >> 4) *num_mbs_oneframe / 2) * 192; //sw_bits_error[7];
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regs->swreg50.bits_error7 = ((mb_target_size >> 4) * num_mbs_oneframe / 2) * 192; //sw_bits_error[7];
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regs->swreg51.bits_error8 = ((mb_target_size >> 4) *num_mbs_oneframe / 2) * 256; //sw_bits_error[8];
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regs->swreg51.bits_error8 = ((mb_target_size >> 4) * num_mbs_oneframe / 2) * 256; //sw_bits_error[8];
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regs->swreg52.qp_adjuest0 = -4; //sw_qp_adjuest[0];
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regs->swreg52.qp_adjuest0 = -4; //sw_qp_adjuest[0];
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regs->swreg52.qp_adjuest1 = -3; //sw_qp_adjuest[1];
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regs->swreg52.qp_adjuest1 = -3; //sw_qp_adjuest[1];
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@@ -2743,24 +2743,24 @@ MPP_RET hal_h264e_rkv_set_rc_regs(h264e_rkv_reg_set *regs, h264e_syntax *syn,
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MPP_RET hal_h264e_rkv_set_roi_regs(h264e_rkv_reg_set *regs, h264e_syntax *syn, MppBuffer roi_idx_buf, RK_U32 frame_cnt,
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MPP_RET hal_h264e_rkv_set_roi_regs(h264e_rkv_reg_set *regs, h264e_syntax *syn, MppBuffer roi_idx_buf, RK_U32 frame_cnt,
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h264e_hal_rkv_coveragetest_cfg *test)
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h264e_hal_rkv_coveragetest_cfg *test)
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{
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{
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if(test && test->roi) {
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if (test && test->roi) {
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RK_U32 k = 0;
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RK_U32 k = 0;
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RK_U32 num_mbs_oneframe = (syn->pic_luma_width+15)/16 * ((syn->pic_luma_height+15)/16);
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RK_U32 num_mbs_oneframe = (syn->pic_luma_width + 15) / 16 * ((syn->pic_luma_height + 15) / 16);
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h264e_hal_rkv_roi_cfg *roi_cfg = mpp_calloc(h264e_hal_rkv_roi_cfg, num_mbs_oneframe);
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h264e_hal_rkv_roi_cfg *roi_cfg = mpp_calloc(h264e_hal_rkv_roi_cfg, num_mbs_oneframe);
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mpp_log("---- test-roi ----");
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mpp_log("---- test-roi ----");
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regs->swreg10.roi_enc = 1;
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regs->swreg10.roi_enc = 1;
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regs->swreg29_ctuc_addr= mpp_buffer_get_fd(roi_idx_buf);
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regs->swreg29_ctuc_addr = mpp_buffer_get_fd(roi_idx_buf);
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if(frame_cnt%3==0) {
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if (frame_cnt % 3 == 0) {
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for(k=0; k<4*((syn->pic_luma_width+15)/16); k++) {
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for (k = 0; k < 4 * ((syn->pic_luma_width + 15) / 16); k++) {
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roi_cfg[k].set_qp_y_en = 1;
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roi_cfg[k].set_qp_y_en = 1;
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roi_cfg[k].qp_y = 20;
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roi_cfg[k].qp_y = 20;
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}
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}
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} else if(frame_cnt%3==1) {
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} else if (frame_cnt % 3 == 1) {
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for(k=0; k<4*((syn->pic_luma_width+15)/16); k++) {
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for (k = 0; k < 4 * ((syn->pic_luma_width + 15) / 16); k++) {
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roi_cfg[k].forbit_inter = 1;
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roi_cfg[k].forbit_inter = 1;
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}
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}
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} else { // frame_cnt%3==2
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} else { // frame_cnt%3==2
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for(k=0; k<4*((syn->pic_luma_width+15)/16); k++) {
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for (k = 0; k < 4 * ((syn->pic_luma_width + 15) / 16); k++) {
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roi_cfg[k].set_qp_y_en = 1;
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roi_cfg[k].set_qp_y_en = 1;
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roi_cfg[k].qp_y = 20;
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roi_cfg[k].qp_y = 20;
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roi_cfg[k].forbit_inter = 1;
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roi_cfg[k].forbit_inter = 1;
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@@ -2779,8 +2779,8 @@ MPP_RET hal_h264e_rkv_set_roi_regs(h264e_rkv_reg_set *regs, h264e_syntax *syn, M
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MPP_RET hal_h264e_rkv_set_osd_regs(h264e_rkv_reg_set *regs, h264e_syntax *syn, MppBuffer osd_idx_buf,
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MPP_RET hal_h264e_rkv_set_osd_regs(h264e_rkv_reg_set *regs, h264e_syntax *syn, MppBuffer osd_idx_buf,
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h264e_hal_rkv_coveragetest_cfg *test)
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h264e_hal_rkv_coveragetest_cfg *test)
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{
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{
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if(test && test->osd) {
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if (test && test->osd) {
|
||||||
#define OSD_SIZE_MBS 4 //size of osd in mb
|
#define OSD_SIZE_MBS 4 //size of osd in mb
|
||||||
RK_S32 k = 0;
|
RK_S32 k = 0;
|
||||||
RK_U32 osd_r0_en = 1;
|
RK_U32 osd_r0_en = 1;
|
||||||
RK_U32 osd_r1_en = 1;
|
RK_U32 osd_r1_en = 1;
|
||||||
@@ -2800,13 +2800,13 @@ MPP_RET hal_h264e_rkv_set_osd_regs(h264e_rkv_reg_set *regs, h264e_syntax *syn, M
|
|||||||
RK_U32 osd_r6_inv_en = 0;
|
RK_U32 osd_r6_inv_en = 0;
|
||||||
RK_U32 osd_r7_inv_en = 0;
|
RK_U32 osd_r7_inv_en = 0;
|
||||||
|
|
||||||
RK_U32 osd_size_pixels = 16*OSD_SIZE_MBS*16*OSD_SIZE_MBS;
|
RK_U32 osd_size_pixels = 16 * OSD_SIZE_MBS * 16 * OSD_SIZE_MBS;
|
||||||
mpp_log("---- test-osd ----");
|
mpp_log("---- test-osd ----");
|
||||||
|
|
||||||
|
|
||||||
regs->swreg65.osd_en = (osd_r0_en<<0)+(osd_r1_en<<1)+(osd_r2_en<<2)+(osd_r3_en<<3)+ (osd_r4_en<<4)+(osd_r5_en<<5)+(osd_r6_en<<6)+(osd_r7_en<<7);
|
regs->swreg65.osd_en = (osd_r0_en << 0) + (osd_r1_en << 1) + (osd_r2_en << 2) + (osd_r3_en << 3) + (osd_r4_en << 4) + (osd_r5_en << 5) + (osd_r6_en << 6) + (osd_r7_en << 7);
|
||||||
regs->swreg65.osd_inv = (osd_r0_inv_en<<0)+(osd_r1_inv_en<<1)+(osd_r2_inv_en<<2)+(osd_r3_inv_en<<3)+
|
regs->swreg65.osd_inv = (osd_r0_inv_en << 0) + (osd_r1_inv_en << 1) + (osd_r2_inv_en << 2) + (osd_r3_inv_en << 3) +
|
||||||
(osd_r4_inv_en<<4)+(osd_r5_inv_en<<5)+(osd_r6_inv_en<<6)+(osd_r7_inv_en<<7);
|
(osd_r4_inv_en << 4) + (osd_r5_inv_en << 5) + (osd_r6_inv_en << 6) + (osd_r7_inv_en << 7);
|
||||||
|
|
||||||
regs->swreg65.osd_clk_sel = 1;
|
regs->swreg65.osd_clk_sel = 1;
|
||||||
regs->swreg65.osd_plt_type = 0; //OSD_plt_type;
|
regs->swreg65.osd_plt_type = 0; //OSD_plt_type;
|
||||||
@@ -2819,62 +2819,60 @@ MPP_RET hal_h264e_rkv_set_osd_regs(h264e_rkv_reg_set *regs, h264e_syntax *syn, M
|
|||||||
regs->swreg66.osd_inv_r6 = 0; //OSD_r6_inv_range;
|
regs->swreg66.osd_inv_r6 = 0; //OSD_r6_inv_range;
|
||||||
regs->swreg66.osd_inv_r7 = 0; //OSD_r7_inv_range;
|
regs->swreg66.osd_inv_r7 = 0; //OSD_r7_inv_range;
|
||||||
|
|
||||||
regs->swreg67_osd_pos[0].lt_pos_x = 0*OSD_SIZE_MBS; //OSD_r0_x_lt_pos;
|
regs->swreg67_osd_pos[0].lt_pos_x = 0 * OSD_SIZE_MBS; //OSD_r0_x_lt_pos;
|
||||||
regs->swreg67_osd_pos[0].lt_pos_y = 0*OSD_SIZE_MBS; //OSD_r0_y_lt_pos;
|
regs->swreg67_osd_pos[0].lt_pos_y = 0 * OSD_SIZE_MBS; //OSD_r0_y_lt_pos;
|
||||||
regs->swreg67_osd_pos[0].rd_pos_x = 0*OSD_SIZE_MBS+OSD_SIZE_MBS-1; //OSD_r0_x_rd_pos;
|
regs->swreg67_osd_pos[0].rd_pos_x = 0 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r0_x_rd_pos;
|
||||||
regs->swreg67_osd_pos[0].rd_pos_y = 0*OSD_SIZE_MBS+OSD_SIZE_MBS-1; //OSD_r0_y_rd_pos;
|
regs->swreg67_osd_pos[0].rd_pos_y = 0 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r0_y_rd_pos;
|
||||||
|
|
||||||
regs->swreg67_osd_pos[1].lt_pos_x = 1*OSD_SIZE_MBS; //OSD_r1_x_lt_pos;
|
regs->swreg67_osd_pos[1].lt_pos_x = 1 * OSD_SIZE_MBS; //OSD_r1_x_lt_pos;
|
||||||
regs->swreg67_osd_pos[1].lt_pos_y = 0*OSD_SIZE_MBS; //OSD_r1_y_lt_pos;
|
regs->swreg67_osd_pos[1].lt_pos_y = 0 * OSD_SIZE_MBS; //OSD_r1_y_lt_pos;
|
||||||
regs->swreg67_osd_pos[1].rd_pos_x = 1*OSD_SIZE_MBS+OSD_SIZE_MBS-1; //OSD_r1_x_rd_pos;
|
regs->swreg67_osd_pos[1].rd_pos_x = 1 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r1_x_rd_pos;
|
||||||
regs->swreg67_osd_pos[1].rd_pos_y = 0*OSD_SIZE_MBS+OSD_SIZE_MBS-1; //OSD_r1_y_rd_pos;
|
regs->swreg67_osd_pos[1].rd_pos_y = 0 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r1_y_rd_pos;
|
||||||
|
|
||||||
regs->swreg67_osd_pos[2].lt_pos_x = 2*OSD_SIZE_MBS; //OSD_r2_x_lt_pos;
|
regs->swreg67_osd_pos[2].lt_pos_x = 2 * OSD_SIZE_MBS; //OSD_r2_x_lt_pos;
|
||||||
regs->swreg67_osd_pos[2].lt_pos_y = 0*OSD_SIZE_MBS; //OSD_r2_y_lt_pos;
|
regs->swreg67_osd_pos[2].lt_pos_y = 0 * OSD_SIZE_MBS; //OSD_r2_y_lt_pos;
|
||||||
regs->swreg67_osd_pos[2].rd_pos_x = 2*OSD_SIZE_MBS+OSD_SIZE_MBS-1; //OSD_r2_x_rd_pos;
|
regs->swreg67_osd_pos[2].rd_pos_x = 2 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r2_x_rd_pos;
|
||||||
regs->swreg67_osd_pos[2].rd_pos_y = 0*OSD_SIZE_MBS+OSD_SIZE_MBS-1; //OSD_r2_y_rd_pos;
|
regs->swreg67_osd_pos[2].rd_pos_y = 0 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r2_y_rd_pos;
|
||||||
|
|
||||||
regs->swreg67_osd_pos[3].lt_pos_x = 3*OSD_SIZE_MBS; //OSD_r3_x_lt_pos;
|
regs->swreg67_osd_pos[3].lt_pos_x = 3 * OSD_SIZE_MBS; //OSD_r3_x_lt_pos;
|
||||||
regs->swreg67_osd_pos[3].lt_pos_y = 0*OSD_SIZE_MBS; //OSD_r3_y_lt_pos;
|
regs->swreg67_osd_pos[3].lt_pos_y = 0 * OSD_SIZE_MBS; //OSD_r3_y_lt_pos;
|
||||||
regs->swreg67_osd_pos[3].rd_pos_x = 3*OSD_SIZE_MBS+OSD_SIZE_MBS-1; //OSD_r3_x_rd_pos;
|
regs->swreg67_osd_pos[3].rd_pos_x = 3 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r3_x_rd_pos;
|
||||||
regs->swreg67_osd_pos[3].rd_pos_y = 0*OSD_SIZE_MBS+OSD_SIZE_MBS-1; //OSD_r3_y_rd_pos;
|
regs->swreg67_osd_pos[3].rd_pos_y = 0 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r3_y_rd_pos;
|
||||||
|
|
||||||
regs->swreg67_osd_pos[4].lt_pos_x = 0*OSD_SIZE_MBS; //OSD_r4_x_lt_pos;
|
regs->swreg67_osd_pos[4].lt_pos_x = 0 * OSD_SIZE_MBS; //OSD_r4_x_lt_pos;
|
||||||
regs->swreg67_osd_pos[4].lt_pos_y = 1*OSD_SIZE_MBS; //OSD_r4_y_lt_pos;
|
regs->swreg67_osd_pos[4].lt_pos_y = 1 * OSD_SIZE_MBS; //OSD_r4_y_lt_pos;
|
||||||
regs->swreg67_osd_pos[4].rd_pos_x = 0*OSD_SIZE_MBS+OSD_SIZE_MBS-1; //OSD_r4_x_rd_pos;
|
regs->swreg67_osd_pos[4].rd_pos_x = 0 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r4_x_rd_pos;
|
||||||
regs->swreg67_osd_pos[4].rd_pos_y = 1*OSD_SIZE_MBS+OSD_SIZE_MBS-1; //OSD_r4_x_rd_pos;
|
regs->swreg67_osd_pos[4].rd_pos_y = 1 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r4_x_rd_pos;
|
||||||
|
|
||||||
regs->swreg67_osd_pos[5].lt_pos_x = 1*OSD_SIZE_MBS; //OSD_r5_x_lt_pos;
|
regs->swreg67_osd_pos[5].lt_pos_x = 1 * OSD_SIZE_MBS; //OSD_r5_x_lt_pos;
|
||||||
regs->swreg67_osd_pos[5].lt_pos_y = 1*OSD_SIZE_MBS; //OSD_r5_y_lt_pos;
|
regs->swreg67_osd_pos[5].lt_pos_y = 1 * OSD_SIZE_MBS; //OSD_r5_y_lt_pos;
|
||||||
regs->swreg67_osd_pos[5].rd_pos_x = 1*OSD_SIZE_MBS+OSD_SIZE_MBS-1; //OSD_r5_x_rd_pos;
|
regs->swreg67_osd_pos[5].rd_pos_x = 1 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r5_x_rd_pos;
|
||||||
regs->swreg67_osd_pos[5].rd_pos_y = 1*OSD_SIZE_MBS+OSD_SIZE_MBS-1; //OSD_r5_y_rd_pos;
|
regs->swreg67_osd_pos[5].rd_pos_y = 1 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r5_y_rd_pos;
|
||||||
|
|
||||||
regs->swreg67_osd_pos[6].lt_pos_x = 2*OSD_SIZE_MBS; //OSD_r6_x_lt_pos;
|
regs->swreg67_osd_pos[6].lt_pos_x = 2 * OSD_SIZE_MBS; //OSD_r6_x_lt_pos;
|
||||||
regs->swreg67_osd_pos[6].lt_pos_y = 1*OSD_SIZE_MBS; //OSD_r6_y_lt_pos;
|
regs->swreg67_osd_pos[6].lt_pos_y = 1 * OSD_SIZE_MBS; //OSD_r6_y_lt_pos;
|
||||||
regs->swreg67_osd_pos[6].rd_pos_x = 2*OSD_SIZE_MBS+OSD_SIZE_MBS-1; //OSD_r6_x_rd_pos;
|
regs->swreg67_osd_pos[6].rd_pos_x = 2 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r6_x_rd_pos;
|
||||||
regs->swreg67_osd_pos[6].rd_pos_y = 1*OSD_SIZE_MBS+OSD_SIZE_MBS-1; //OSD_r6_y_rd_pos;
|
regs->swreg67_osd_pos[6].rd_pos_y = 1 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r6_y_rd_pos;
|
||||||
|
|
||||||
regs->swreg67_osd_pos[7].lt_pos_x = 3*OSD_SIZE_MBS; //OSD_r7_x_lt_pos;
|
regs->swreg67_osd_pos[7].lt_pos_x = 3 * OSD_SIZE_MBS; //OSD_r7_x_lt_pos;
|
||||||
regs->swreg67_osd_pos[7].lt_pos_y = 1*OSD_SIZE_MBS; //OSD_r7_y_lt_pos;
|
regs->swreg67_osd_pos[7].lt_pos_y = 1 * OSD_SIZE_MBS; //OSD_r7_y_lt_pos;
|
||||||
regs->swreg67_osd_pos[7].rd_pos_x = 3*OSD_SIZE_MBS+OSD_SIZE_MBS-1; //OSD_r7_x_rd_pos;
|
regs->swreg67_osd_pos[7].rd_pos_x = 3 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r7_x_rd_pos;
|
||||||
regs->swreg67_osd_pos[7].rd_pos_y = 1*OSD_SIZE_MBS+OSD_SIZE_MBS-1; //OSD_r7_y_rd_pos;
|
regs->swreg67_osd_pos[7].rd_pos_y = 1 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r7_y_rd_pos;
|
||||||
|
|
||||||
for(k=0; k<8; k++)
|
for (k = 0; k < 8; k++) {
|
||||||
{
|
if (regs->swreg65.osd_plt_type == 0) //configurable
|
||||||
if(regs->swreg65.osd_plt_type==0) //configurable
|
memset((RK_U8 *)mpp_buffer_get_ptr(osd_idx_buf) + k * osd_size_pixels, 32 * k, osd_size_pixels);
|
||||||
memset((RK_U8 *)mpp_buffer_get_ptr(osd_idx_buf)+k*osd_size_pixels, 32*k, osd_size_pixels);
|
|
||||||
else //fixed mode: only support idx 0~7
|
else //fixed mode: only support idx 0~7
|
||||||
memset((RK_U8 *)mpp_buffer_get_ptr(osd_idx_buf)+k*osd_size_pixels, k, osd_size_pixels);
|
memset((RK_U8 *)mpp_buffer_get_ptr(osd_idx_buf) + k * osd_size_pixels, k, osd_size_pixels);
|
||||||
|
|
||||||
regs->swreg68_indx_addr_i[k] = mpp_buffer_get_fd(osd_idx_buf) | ((k*osd_size_pixels)<<10); //h->param.indx_addr_i[i];
|
regs->swreg68_indx_addr_i[k] = mpp_buffer_get_fd(osd_idx_buf) | ((k * osd_size_pixels) << 10); //h->param.indx_addr_i[i];
|
||||||
mpp_log("regs->swreg68_indx_addr_i[k] 0x%08x", regs->swreg68_indx_addr_i[k]);
|
mpp_log("regs->swreg68_indx_addr_i[k] 0x%08x", regs->swreg68_indx_addr_i[k]);
|
||||||
}
|
}
|
||||||
#if 0 //written in kernel
|
#if 0 //written in kernel
|
||||||
for(k=0; k<256; k++)
|
for (k = 0; k < 256; k++) {
|
||||||
{
|
regs->swreg73_osd_indx_tab_i[k] = k | (0x80 << 8) | (0x80 << 16) | (k << 24);
|
||||||
regs->swreg73_osd_indx_tab_i[k] = k | (0x80<<8) | (0x80<<16) | (k<<24);
|
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
} else {
|
} else {
|
||||||
|
|
||||||
@@ -2890,19 +2888,19 @@ MPP_RET hal_h264e_rkv_set_pp_regs(h264e_rkv_reg_set *regs, h264e_syntax *syn, Mp
|
|||||||
{
|
{
|
||||||
RK_S32 k = 0;
|
RK_S32 k = 0;
|
||||||
RK_S32 stridey, stridec;
|
RK_S32 stridey, stridec;
|
||||||
if(test && test->preproc) {
|
if (test && test->preproc) {
|
||||||
|
|
||||||
RK_U32 h3d_tbl[40] = {
|
RK_U32 h3d_tbl[40] = {
|
||||||
0x0b080400,0x1815120f,0x23201e1b,0x2c2a2725,
|
0x0b080400, 0x1815120f, 0x23201e1b, 0x2c2a2725,
|
||||||
0x33312f2d,0x38373634,0x3d3c3b39,0x403f3e3d,
|
0x33312f2d, 0x38373634, 0x3d3c3b39, 0x403f3e3d,
|
||||||
0x42414140,0x43434342,0x44444444,0x44444444,
|
0x42414140, 0x43434342, 0x44444444, 0x44444444,
|
||||||
0x44444444,0x43434344,0x42424343,0x40414142,
|
0x44444444, 0x43434344, 0x42424343, 0x40414142,
|
||||||
0x3d3e3f40,0x393a3b3c,0x35363738,0x30313334,
|
0x3d3e3f40, 0x393a3b3c, 0x35363738, 0x30313334,
|
||||||
0x2c2d2e2f,0x28292a2b,0x23242526,0x20202122,
|
0x2c2d2e2f, 0x28292a2b, 0x23242526, 0x20202122,
|
||||||
0x191b1d1f,0x14151618,0x0f101112,0x0b0c0d0e,
|
0x191b1d1f, 0x14151618, 0x0f101112, 0x0b0c0d0e,
|
||||||
0x08090a0a,0x06070708,0x05050506,0x03040404,
|
0x08090a0a, 0x06070708, 0x05050506, 0x03040404,
|
||||||
0x02020303,0x01010102,0x00010101,0x00000000,
|
0x02020303, 0x01010102, 0x00010101, 0x00000000,
|
||||||
0x00000000,0x00000000,0x00000000,0x00000000
|
0x00000000, 0x00000000, 0x00000000, 0x00000000
|
||||||
};
|
};
|
||||||
|
|
||||||
mpp_log("---- test-preproc ----");
|
mpp_log("---- test-preproc ----");
|
||||||
@@ -2959,11 +2957,11 @@ MPP_RET hal_h264e_rkv_set_pp_regs(h264e_rkv_reg_set *regs, h264e_syntax *syn, Mp
|
|||||||
regs->swreg21_scr_stbl[3] = (RK_U32)1073741823; //sharp_matrix[3];
|
regs->swreg21_scr_stbl[3] = (RK_U32)1073741823; //sharp_matrix[3];
|
||||||
regs->swreg21_scr_stbl[4] = (RK_U32)1073741823; //sharp_matrix[4];
|
regs->swreg21_scr_stbl[4] = (RK_U32)1073741823; //sharp_matrix[4];
|
||||||
|
|
||||||
for(k=0; k<40; k++)
|
for (k = 0; k < 40; k++)
|
||||||
regs->swreg22_h3d_tbl[k] = h3d_tbl[k];
|
regs->swreg22_h3d_tbl[k] = h3d_tbl[k];
|
||||||
|
|
||||||
|
|
||||||
stridey = (syn->pic_luma_width + 15)&(~15);
|
stridey = (syn->pic_luma_width + 15) & (~15);
|
||||||
stridec = stridey;
|
stridec = stridey;
|
||||||
|
|
||||||
regs->swreg23.src_ystrid = stridey;
|
regs->swreg23.src_ystrid = stridey;
|
||||||
@@ -3026,7 +3024,7 @@ MPP_RET hal_h264e_rkv_gen_regs(void *hal, HalTaskInfo *task)
|
|||||||
h264e_hal_debug_enter();
|
h264e_hal_debug_enter();
|
||||||
hal_h264e_rkv_dump_mpp_syntax_in(syn, ctx);
|
hal_h264e_rkv_dump_mpp_syntax_in(syn, ctx);
|
||||||
|
|
||||||
if (MPP_OK != hal_h264e_rkv_validate_syntax(syn, &src_fmt, ctx->frame_cnt%sps->keyframe_max_interval==0)) {
|
if (MPP_OK != hal_h264e_rkv_validate_syntax(syn, &src_fmt, ctx->frame_cnt % sps->keyframe_max_interval == 0)) {
|
||||||
h264e_hal_log_err("hal_h264e_rkv_validate_syntax failed");
|
h264e_hal_log_err("hal_h264e_rkv_validate_syntax failed");
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -3132,7 +3130,7 @@ MPP_RET hal_h264e_rkv_gen_regs(void *hal, HalTaskInfo *task)
|
|||||||
regs->swreg13.axi_brsp_cke = 0x7f; //syn->swreg13.axi_brsp_cke;
|
regs->swreg13.axi_brsp_cke = 0x7f; //syn->swreg13.axi_brsp_cke;
|
||||||
regs->swreg13.cime_dspw_orsd = 0x0;
|
regs->swreg13.cime_dspw_orsd = 0x0;
|
||||||
|
|
||||||
hal_h264e_rkv_set_pp_regs(regs, syn, bufs->hw_pp_buf[buf2_idx], bufs->hw_pp_buf[1-buf2_idx], ctx->frame_cnt, test_cfg);
|
hal_h264e_rkv_set_pp_regs(regs, syn, bufs->hw_pp_buf[buf2_idx], bufs->hw_pp_buf[1 - buf2_idx], ctx->frame_cnt, test_cfg);
|
||||||
|
|
||||||
regs->swreg24_adr_srcy = syn->input_luma_addr; //syn->addr_cfg.adr_srcy;
|
regs->swreg24_adr_srcy = syn->input_luma_addr; //syn->addr_cfg.adr_srcy;
|
||||||
regs->swreg25_adr_srcu = syn->input_cb_addr; //syn->addr_cfg.adr_srcu;
|
regs->swreg25_adr_srcu = syn->input_cb_addr; //syn->addr_cfg.adr_srcu;
|
||||||
@@ -3146,9 +3144,9 @@ MPP_RET hal_h264e_rkv_gen_regs(void *hal, HalTaskInfo *task)
|
|||||||
regs->swreg31_rfpr_addr = mpp_buffer_get_fd(dpb_ctx->fref[0][0]->hw_buf); //syn->addr_cfg.rfpr_addr;
|
regs->swreg31_rfpr_addr = mpp_buffer_get_fd(dpb_ctx->fref[0][0]->hw_buf); //syn->addr_cfg.rfpr_addr;
|
||||||
//regs->swreg32_cmvw_addr = mpp_buffer_get_fd(bufs->hw_cmv_buf[buf2_idx]);
|
//regs->swreg32_cmvw_addr = mpp_buffer_get_fd(bufs->hw_cmv_buf[buf2_idx]);
|
||||||
|
|
||||||
if(bufs->hw_dsp_buf[buf2_idx])
|
if (bufs->hw_dsp_buf[buf2_idx])
|
||||||
regs->swreg34_dspw_addr = mpp_buffer_get_fd(bufs->hw_dsp_buf[buf2_idx]); //syn->addr_cfg.dspw_addr;
|
regs->swreg34_dspw_addr = mpp_buffer_get_fd(bufs->hw_dsp_buf[buf2_idx]); //syn->addr_cfg.dspw_addr;
|
||||||
if(bufs->hw_dsp_buf[1 - buf2_idx])
|
if (bufs->hw_dsp_buf[1 - buf2_idx])
|
||||||
regs->swreg35_dspr_addr = mpp_buffer_get_fd(bufs->hw_dsp_buf[1 - buf2_idx]); //syn->addr_cfg.dspr_addr;
|
regs->swreg35_dspr_addr = mpp_buffer_get_fd(bufs->hw_dsp_buf[1 - buf2_idx]); //syn->addr_cfg.dspr_addr;
|
||||||
|
|
||||||
regs->swreg36_meiw_addr = 0; //mpp_buffer_get_fd(bufs->hw_mei_buf[mul_buf_idx]);
|
regs->swreg36_meiw_addr = 0; //mpp_buffer_get_fd(bufs->hw_mei_buf[mul_buf_idx]);
|
||||||
@@ -3502,37 +3500,37 @@ static MPP_RET hal_h264e_rkv_set_feedback(h264e_feedback *fb, h264e_rkv_ioctl_ou
|
|||||||
|
|
||||||
fb->hw_status = 0;
|
fb->hw_status = 0;
|
||||||
h264e_hal_log_detail("hw_status: 0x%08x", elem->hw_status);
|
h264e_hal_log_detail("hw_status: 0x%08x", elem->hw_status);
|
||||||
if(elem->hw_status & RKV_H264E_INT_LINKTABLE_FINISH) {
|
if (elem->hw_status & RKV_H264E_INT_LINKTABLE_FINISH) {
|
||||||
h264e_hal_log_err("RKV_H264E_INT_LINKTABLE_FINISH");
|
h264e_hal_log_err("RKV_H264E_INT_LINKTABLE_FINISH");
|
||||||
}
|
}
|
||||||
if(elem->hw_status & RKV_H264E_INT_ONE_FRAME_FINISH) {
|
if (elem->hw_status & RKV_H264E_INT_ONE_FRAME_FINISH) {
|
||||||
h264e_hal_log_detail("RKV_H264E_INT_ONE_FRAME_FINISH");
|
h264e_hal_log_detail("RKV_H264E_INT_ONE_FRAME_FINISH");
|
||||||
}
|
}
|
||||||
if(elem->hw_status & RKV_H264E_INT_ONE_SLICE_FINISH) {
|
if (elem->hw_status & RKV_H264E_INT_ONE_SLICE_FINISH) {
|
||||||
h264e_hal_log_err("RKV_H264E_INT_ONE_SLICE_FINISH");
|
h264e_hal_log_err("RKV_H264E_INT_ONE_SLICE_FINISH");
|
||||||
}
|
}
|
||||||
|
|
||||||
if(elem->hw_status & RKV_H264E_INT_SAFE_CLEAR_FINISH) {
|
if (elem->hw_status & RKV_H264E_INT_SAFE_CLEAR_FINISH) {
|
||||||
h264e_hal_log_err("RKV_H264E_INT_SAFE_CLEAR_FINISH");
|
h264e_hal_log_err("RKV_H264E_INT_SAFE_CLEAR_FINISH");
|
||||||
}
|
}
|
||||||
|
|
||||||
if(elem->hw_status & RKV_H264E_INT_BIT_STREAM_OVERFLOW) {
|
if (elem->hw_status & RKV_H264E_INT_BIT_STREAM_OVERFLOW) {
|
||||||
h264e_hal_log_err("RKV_H264E_INT_BIT_STREAM_OVERFLOW");
|
h264e_hal_log_err("RKV_H264E_INT_BIT_STREAM_OVERFLOW");
|
||||||
fb->hw_status = 1;
|
fb->hw_status = 1;
|
||||||
}
|
}
|
||||||
if(elem->hw_status & RKV_H264E_INT_BUS_WRITE_FULL) {
|
if (elem->hw_status & RKV_H264E_INT_BUS_WRITE_FULL) {
|
||||||
h264e_hal_log_err("RKV_H264E_INT_BUS_WRITE_FULL");
|
h264e_hal_log_err("RKV_H264E_INT_BUS_WRITE_FULL");
|
||||||
fb->hw_status = 1;
|
fb->hw_status = 1;
|
||||||
}
|
}
|
||||||
if(elem->hw_status & RKV_H264E_INT_BUS_WRITE_ERROR) {
|
if (elem->hw_status & RKV_H264E_INT_BUS_WRITE_ERROR) {
|
||||||
h264e_hal_log_err("RKV_H264E_INT_BUS_WRITE_ERROR");
|
h264e_hal_log_err("RKV_H264E_INT_BUS_WRITE_ERROR");
|
||||||
fb->hw_status = 1;
|
fb->hw_status = 1;
|
||||||
}
|
}
|
||||||
if(elem->hw_status & RKV_H264E_INT_BUS_READ_ERROR) {
|
if (elem->hw_status & RKV_H264E_INT_BUS_READ_ERROR) {
|
||||||
h264e_hal_log_err("RKV_H264E_INT_BUS_READ_ERROR");
|
h264e_hal_log_err("RKV_H264E_INT_BUS_READ_ERROR");
|
||||||
fb->hw_status = 1;
|
fb->hw_status = 1;
|
||||||
}
|
}
|
||||||
if(elem->hw_status & RKV_H264E_INT_TIMEOUT_ERROR) {
|
if (elem->hw_status & RKV_H264E_INT_TIMEOUT_ERROR) {
|
||||||
h264e_hal_log_err("RKV_H264E_INT_TIMEOUT_ERROR");
|
h264e_hal_log_err("RKV_H264E_INT_TIMEOUT_ERROR");
|
||||||
fb->hw_status = 1;
|
fb->hw_status = 1;
|
||||||
}
|
}
|
||||||
|
@@ -91,7 +91,7 @@ typedef struct h264e_hal_rkv_coveragetest_cfg_t {
|
|||||||
RK_U32 osd;
|
RK_U32 osd;
|
||||||
RK_U32 mbrc;
|
RK_U32 mbrc;
|
||||||
RK_U32 roi;
|
RK_U32 roi;
|
||||||
}h264e_hal_rkv_coveragetest_cfg;
|
} h264e_hal_rkv_coveragetest_cfg;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
@@ -145,7 +145,7 @@ typedef struct h264e_hal_rkv_roi_cfg_t {
|
|||||||
RK_U8 qp_y : 6;
|
RK_U8 qp_y : 6;
|
||||||
RK_U8 set_qp_y_en : 1;
|
RK_U8 set_qp_y_en : 1;
|
||||||
RK_U8 forbit_inter : 1;
|
RK_U8 forbit_inter : 1;
|
||||||
}h264e_hal_rkv_roi_cfg;
|
} h264e_hal_rkv_roi_cfg;
|
||||||
|
|
||||||
|
|
||||||
typedef struct h264e_hal_rkv_buffers_t {
|
typedef struct h264e_hal_rkv_buffers_t {
|
||||||
|
@@ -87,13 +87,13 @@ static RK_U32 h264e_rkv_revert_csp(h264e_hal_csp_info csp_info)
|
|||||||
RK_U32 aswap = csp_info.aswap;
|
RK_U32 aswap = csp_info.aswap;
|
||||||
MppFrameFormat dst_fmt;
|
MppFrameFormat dst_fmt;
|
||||||
|
|
||||||
switch(fmt) {
|
switch (fmt) {
|
||||||
case H264E_RKV_CSP_YUV420P: {
|
case H264E_RKV_CSP_YUV420P: {
|
||||||
dst_fmt = MPP_FMT_YUV420P;
|
dst_fmt = MPP_FMT_YUV420P;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case H264E_RKV_CSP_YUV420SP: {
|
case H264E_RKV_CSP_YUV420SP: {
|
||||||
dst_fmt = cswap? MPP_FMT_YUV420SP_VU : MPP_FMT_YUV420SP;
|
dst_fmt = cswap ? MPP_FMT_YUV420SP_VU : MPP_FMT_YUV420SP;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case H264E_RKV_CSP_YUV422P: {
|
case H264E_RKV_CSP_YUV422P: {
|
||||||
@@ -101,7 +101,7 @@ static RK_U32 h264e_rkv_revert_csp(h264e_hal_csp_info csp_info)
|
|||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case H264E_RKV_CSP_YUV422SP: {
|
case H264E_RKV_CSP_YUV422SP: {
|
||||||
dst_fmt = cswap? MPP_FMT_YUV422SP_VU : MPP_FMT_YUV422SP;
|
dst_fmt = cswap ? MPP_FMT_YUV422SP_VU : MPP_FMT_YUV422SP;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case H264E_RKV_CSP_YUYV422: {
|
case H264E_RKV_CSP_YUYV422: {
|
||||||
@@ -113,16 +113,16 @@ static RK_U32 h264e_rkv_revert_csp(h264e_hal_csp_info csp_info)
|
|||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case H264E_RKV_CSP_BGR565: {
|
case H264E_RKV_CSP_BGR565: {
|
||||||
dst_fmt = cswap? MPP_FMT_RGB565 : MPP_FMT_BGR565;
|
dst_fmt = cswap ? MPP_FMT_RGB565 : MPP_FMT_BGR565;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case H264E_RKV_CSP_BGR888: {
|
case H264E_RKV_CSP_BGR888: {
|
||||||
dst_fmt = cswap? MPP_FMT_RGB888 : MPP_FMT_BGR888;
|
dst_fmt = cswap ? MPP_FMT_RGB888 : MPP_FMT_BGR888;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case H264E_RKV_CSP_BGRA8888: {
|
case H264E_RKV_CSP_BGRA8888: {
|
||||||
if(aswap)
|
if (aswap)
|
||||||
dst_fmt = cswap? MPP_FMT_ABGR8888 : MPP_FMT_ARGB8888;
|
dst_fmt = cswap ? MPP_FMT_ABGR8888 : MPP_FMT_ARGB8888;
|
||||||
else
|
else
|
||||||
dst_fmt = MPP_FMT_BUTT;
|
dst_fmt = MPP_FMT_BUTT;
|
||||||
|
|
||||||
@@ -135,7 +135,7 @@ static RK_U32 h264e_rkv_revert_csp(h264e_hal_csp_info csp_info)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if(dst_fmt == MPP_FMT_BUTT) {
|
if (dst_fmt == MPP_FMT_BUTT) {
|
||||||
h264e_hal_log_err("revert_csp error, src_fmt %d, dst_fmt %d", fmt, dst_fmt);
|
h264e_hal_log_err("revert_csp error, src_fmt %d, dst_fmt %d", fmt, dst_fmt);
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -147,7 +147,7 @@ static RK_U32 h264e_vpu_revert_csp(RK_U32 csp)
|
|||||||
h264e_hal_vpu_csp fmt = (h264e_hal_vpu_csp)csp;
|
h264e_hal_vpu_csp fmt = (h264e_hal_vpu_csp)csp;
|
||||||
MppFrameFormat dst_fmt;
|
MppFrameFormat dst_fmt;
|
||||||
|
|
||||||
switch(fmt) {
|
switch (fmt) {
|
||||||
case H264E_VPU_CSP_YUV420P: {
|
case H264E_VPU_CSP_YUV420P: {
|
||||||
dst_fmt = MPP_FMT_YUV420P;
|
dst_fmt = MPP_FMT_YUV420P;
|
||||||
break;
|
break;
|
||||||
@@ -227,23 +227,23 @@ static MPP_RET h264e_rkv_test_open_files(h264e_hal_test_cfg test_cfg)
|
|||||||
return MPP_ERR_OPEN_FILE;
|
return MPP_ERR_OPEN_FILE;
|
||||||
}
|
}
|
||||||
|
|
||||||
#if !RKV_H264E_SDK_TEST
|
#if !RKV_H264E_SDK_TEST
|
||||||
sprintf(full_path, "%s", test_cfg.input_syntax_file_path);
|
sprintf(full_path, "%s", test_cfg.input_syntax_file_path);
|
||||||
fp_golden_syntax_in = fopen(full_path, "rb");
|
fp_golden_syntax_in = fopen(full_path, "rb");
|
||||||
if (!fp_golden_syntax_in) {
|
if (!fp_golden_syntax_in) {
|
||||||
mpp_err("%s open error", full_path);
|
mpp_err("%s open error", full_path);
|
||||||
return MPP_ERR_OPEN_FILE;
|
return MPP_ERR_OPEN_FILE;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if 0
|
#if 0
|
||||||
sprintf(full_path, "%s%s", base_path, "mpp_yuv_in.yuv");
|
sprintf(full_path, "%s%s", base_path, "mpp_yuv_in.yuv");
|
||||||
fp_mpp_yuv_in = fopen(full_path, "wb");
|
fp_mpp_yuv_in = fopen(full_path, "wb");
|
||||||
if (!fp_mpp_yuv_in) {
|
if (!fp_mpp_yuv_in) {
|
||||||
mpp_err("%s open error", full_path);
|
mpp_err("%s open error", full_path);
|
||||||
return MPP_ERR_OPEN_FILE;
|
return MPP_ERR_OPEN_FILE;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
return MPP_OK;
|
return MPP_OK;
|
||||||
}
|
}
|
||||||
@@ -1115,7 +1115,7 @@ static MPP_RET get_rkv_syntax_in( h264e_syntax *syn, MppBuffer *hw_in_buf, MppBu
|
|||||||
if (hw_output_strm_buf[buf_idx])
|
if (hw_output_strm_buf[buf_idx])
|
||||||
syn->output_strm_addr = mpp_buffer_get_fd(hw_output_strm_buf[buf_idx]);
|
syn->output_strm_addr = mpp_buffer_get_fd(hw_output_strm_buf[buf_idx]);
|
||||||
|
|
||||||
#if RKV_H264E_SDK_TEST
|
#if RKV_H264E_SDK_TEST
|
||||||
mpp_log("make syntax begin");
|
mpp_log("make syntax begin");
|
||||||
syn->pic_luma_width = cfg->pic_width;
|
syn->pic_luma_width = cfg->pic_width;
|
||||||
syn->pic_luma_height = cfg->pic_height;
|
syn->pic_luma_height = cfg->pic_height;
|
||||||
@@ -1124,7 +1124,7 @@ static MPP_RET get_rkv_syntax_in( h264e_syntax *syn, MppBuffer *hw_in_buf, MppBu
|
|||||||
mpp_log("syn->level_idc %d", syn->level_idc);
|
mpp_log("syn->level_idc %d", syn->level_idc);
|
||||||
mpp_log("syn->profile_idc %d", syn->profile_idc);
|
mpp_log("syn->profile_idc %d", syn->profile_idc);
|
||||||
syn->keyframe_max_interval = 30;
|
syn->keyframe_max_interval = 30;
|
||||||
if(g_frame_cnt==0 || g_frame_cnt%syn->keyframe_max_interval==0) {
|
if (g_frame_cnt == 0 || g_frame_cnt % syn->keyframe_max_interval == 0) {
|
||||||
syn->frame_coding_type = 1; //intra
|
syn->frame_coding_type = 1; //intra
|
||||||
syn->slice_type = 2;
|
syn->slice_type = 2;
|
||||||
} else {
|
} else {
|
||||||
@@ -1152,7 +1152,7 @@ static MPP_RET get_rkv_syntax_in( h264e_syntax *syn, MppBuffer *hw_in_buf, MppBu
|
|||||||
|
|
||||||
|
|
||||||
mpp_log("make syntax end");
|
mpp_log("make syntax end");
|
||||||
#else
|
#else
|
||||||
if (fp_golden_syntax_in) {
|
if (fp_golden_syntax_in) {
|
||||||
FILE *fp = fp_golden_syntax_in;
|
FILE *fp = fp_golden_syntax_in;
|
||||||
char temp[512] = {0};
|
char temp[512] = {0};
|
||||||
@@ -1195,7 +1195,7 @@ static MPP_RET get_rkv_syntax_in( h264e_syntax *syn, MppBuffer *hw_in_buf, MppBu
|
|||||||
} else {
|
} else {
|
||||||
mpp_err("rkv_syntax_in.txt doesn't exits");
|
mpp_err("rkv_syntax_in.txt doesn't exits");
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
syn->output_strm_limit_size = syn->pic_luma_width * syn->pic_luma_height * 1.5;
|
syn->output_strm_limit_size = syn->pic_luma_width * syn->pic_luma_height * 1.5;
|
||||||
|
|
||||||
h264e_hal_debug_leave();
|
h264e_hal_debug_leave();
|
||||||
@@ -1267,7 +1267,7 @@ static MPP_RET h264e_hal_test_parse_options(int arg_num, char **arg_str, h264e_h
|
|||||||
mpp_log("test param parse error: input_yuv_file_path is NULL");
|
mpp_log("test param parse error: input_yuv_file_path is NULL");
|
||||||
return MPP_NOK;
|
return MPP_NOK;
|
||||||
}
|
}
|
||||||
#if RKV_H264E_SDK_TEST
|
#if RKV_H264E_SDK_TEST
|
||||||
if (!cfg->pic_width) {
|
if (!cfg->pic_width) {
|
||||||
mpp_log("test param parse error: pic_width is 0");
|
mpp_log("test param parse error: pic_width is 0");
|
||||||
return MPP_NOK;
|
return MPP_NOK;
|
||||||
@@ -1276,12 +1276,12 @@ static MPP_RET h264e_hal_test_parse_options(int arg_num, char **arg_str, h264e_h
|
|||||||
mpp_log("test param parse error: pic_height is 0");
|
mpp_log("test param parse error: pic_height is 0");
|
||||||
return MPP_NOK;
|
return MPP_NOK;
|
||||||
}
|
}
|
||||||
#else
|
#else
|
||||||
if (!cfg->input_syntax_file_path) {
|
if (!cfg->input_syntax_file_path) {
|
||||||
mpp_log("test param parse error: input_syntax_file_path is NULL");
|
mpp_log("test param parse error: input_syntax_file_path is NULL");
|
||||||
return MPP_NOK;
|
return MPP_NOK;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
if (cfg->hw_mode == 0)
|
if (cfg->hw_mode == 0)
|
||||||
test_device_id = HAL_RKVENC;
|
test_device_id = HAL_RKVENC;
|
||||||
@@ -1293,15 +1293,15 @@ static MPP_RET h264e_hal_test_parse_options(int arg_num, char **arg_str, h264e_h
|
|||||||
}
|
}
|
||||||
|
|
||||||
mpp_log("======== hal converage test cfg (st) =======");
|
mpp_log("======== hal converage test cfg (st) =======");
|
||||||
if(cfg->test.qp)
|
if (cfg->test.qp)
|
||||||
mpp_log("cfg->test.qp %d", cfg->test.qp);
|
mpp_log("cfg->test.qp %d", cfg->test.qp);
|
||||||
if(cfg->test.preproc)
|
if (cfg->test.preproc)
|
||||||
mpp_log("cfg->test.preproc %d", cfg->test.preproc);
|
mpp_log("cfg->test.preproc %d", cfg->test.preproc);
|
||||||
if(cfg->test.osd)
|
if (cfg->test.osd)
|
||||||
mpp_log("cfg->test.osd %d", cfg->test.osd);
|
mpp_log("cfg->test.osd %d", cfg->test.osd);
|
||||||
if(cfg->test.mbrc)
|
if (cfg->test.mbrc)
|
||||||
mpp_log("cfg->test.mbrc %d", cfg->test.mbrc);
|
mpp_log("cfg->test.mbrc %d", cfg->test.mbrc);
|
||||||
if(cfg->test.roi)
|
if (cfg->test.roi)
|
||||||
mpp_log("cfg->test.roi %d", cfg->test.roi);
|
mpp_log("cfg->test.roi %d", cfg->test.roi);
|
||||||
mpp_log("======== hal converage test cfg (ed) =======");
|
mpp_log("======== hal converage test cfg (ed) =======");
|
||||||
|
|
||||||
@@ -1374,7 +1374,7 @@ MPP_RET h264e_hal_vpu_test()
|
|||||||
mpp_packet_init(&extra_info_pkt, (void *)extra_info_buf, H264E_MAX_PACKETED_PARAM_SIZE);
|
mpp_packet_init(&extra_info_pkt, (void *)extra_info_buf, H264E_MAX_PACKETED_PARAM_SIZE);
|
||||||
|
|
||||||
get_vpu_syntax_in(&syntax_data, hw_input_buf, hw_output_strm_buf);
|
get_vpu_syntax_in(&syntax_data, hw_input_buf, hw_output_strm_buf);
|
||||||
if(fp_golden_syntax_in)
|
if (fp_golden_syntax_in)
|
||||||
fseek(fp_golden_syntax_in, 0L, SEEK_SET);
|
fseek(fp_golden_syntax_in, 0L, SEEK_SET);
|
||||||
|
|
||||||
frame_luma_stride = ((syntax_data.pic_luma_width + 15) & (~15)) * ((syntax_data.pic_luma_height + 15) & (~15));
|
frame_luma_stride = ((syntax_data.pic_luma_width + 15) & (~15)) * ((syntax_data.pic_luma_height + 15) & (~15));
|
||||||
@@ -1494,7 +1494,7 @@ MPP_RET h264e_hal_rkv_test(h264e_hal_test_cfg *test_cfg)
|
|||||||
|
|
||||||
|
|
||||||
get_rkv_syntax_in(&syntax_data[0], hw_input_buf_mul, hw_output_strm_buf_mul, test_cfg);
|
get_rkv_syntax_in(&syntax_data[0], hw_input_buf_mul, hw_output_strm_buf_mul, test_cfg);
|
||||||
if(fp_golden_syntax_in)
|
if (fp_golden_syntax_in)
|
||||||
fseek(fp_golden_syntax_in, 0L, SEEK_SET);
|
fseek(fp_golden_syntax_in, 0L, SEEK_SET);
|
||||||
|
|
||||||
|
|
||||||
@@ -1544,7 +1544,7 @@ MPP_RET h264e_hal_rkv_test(h264e_hal_test_cfg *test_cfg)
|
|||||||
}
|
}
|
||||||
ret = get_rkv_h264e_yuv_in_frame(syn, hw_input_buf_mul);
|
ret = get_rkv_h264e_yuv_in_frame(syn, hw_input_buf_mul);
|
||||||
if (ret == MPP_EOS_STREAM_REACHED) {
|
if (ret == MPP_EOS_STREAM_REACHED) {
|
||||||
if(g_frame_cnt == test_cfg->num_frames) {
|
if (g_frame_cnt == test_cfg->num_frames) {
|
||||||
mpp_log("total %d frames are encoded, test is ended", g_frame_cnt);
|
mpp_log("total %d frames are encoded, test is ended", g_frame_cnt);
|
||||||
goto __test_end;
|
goto __test_end;
|
||||||
} else {
|
} else {
|
||||||
@@ -1575,7 +1575,7 @@ MPP_RET h264e_hal_rkv_test(h264e_hal_test_cfg *test_cfg)
|
|||||||
|
|
||||||
if (g_frame_cnt == g_frame_read_cnt)
|
if (g_frame_cnt == g_frame_read_cnt)
|
||||||
hal_h264e_rkv_dump_mpp_strm_out(&ctx, hw_output_strm_buf_mul);
|
hal_h264e_rkv_dump_mpp_strm_out(&ctx, hw_output_strm_buf_mul);
|
||||||
if(g_frame_cnt==test_cfg->num_frames) {
|
if (g_frame_cnt == test_cfg->num_frames) {
|
||||||
mpp_log("test_cfg->num_frames %d reached, end test", test_cfg->num_frames);
|
mpp_log("test_cfg->num_frames %d reached, end test", test_cfg->num_frames);
|
||||||
goto __test_end;
|
goto __test_end;
|
||||||
}
|
}
|
||||||
|
@@ -208,8 +208,7 @@ public:
|
|||||||
VpulibDlsym() :
|
VpulibDlsym() :
|
||||||
rkapi_hdl(NULL),
|
rkapi_hdl(NULL),
|
||||||
rkvpu_open_cxt(NULL),
|
rkvpu_open_cxt(NULL),
|
||||||
rkvpu_close_cxt(NULL)
|
rkvpu_close_cxt(NULL) {
|
||||||
{
|
|
||||||
RK_U32 i;
|
RK_U32 i;
|
||||||
|
|
||||||
for (i = 0; i < MPP_ARRAY_ELEMS(codec_paths); i++) {
|
for (i = 0; i < MPP_ARRAY_ELEMS(codec_paths); i++) {
|
||||||
|
Reference in New Issue
Block a user