From 3d282d82008b09b841b4c5129c81da4f04e98ba9 Mon Sep 17 00:00:00 2001 From: Herman Chen Date: Mon, 11 Jul 2022 17:54:18 +0800 Subject: [PATCH] [hal_vepu580]: Disable split on pass1 process The pass1 work flow MUST NOT output in slice lowdelay mode. Signed-off-by: Herman Chen Change-Id: I26a6b7b90cec88829997ccee061cada6068bc462 --- mpp/hal/rkenc/h264e/hal_h264e_vepu580.c | 5 +++++ mpp/hal/rkenc/h265e/hal_h265e_vepu580.c | 4 ++++ 2 files changed, 9 insertions(+) diff --git a/mpp/hal/rkenc/h264e/hal_h264e_vepu580.c b/mpp/hal/rkenc/h264e/hal_h264e_vepu580.c index 1ddaccb8..27ad2a84 100644 --- a/mpp/hal/rkenc/h264e/hal_h264e_vepu580.c +++ b/mpp/hal/rkenc/h264e/hal_h264e_vepu580.c @@ -695,8 +695,13 @@ static MPP_RET vepu580_h264e_save_pass1_patch(HalVepu580RegSet *regs, HalH264eVe regs->reg_base.rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1); regs->reg_base.rfpw_b_addr = regs->reg_base.rfpw_h_addr; regs->reg_base.enc_pic.rec_fbc_dis = 1; + mpp_dev_multi_offset_update(ctx->offsets, 164, width_align * height_align); + /* NOTE: disable split to avoid lowdelay slice output */ + regs->reg_base.sli_splt.sli_splt = 0; + regs->reg_base.enc_pic.slen_fifo = 0; + return MPP_OK; } diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu580.c b/mpp/hal/rkenc/h265e/hal_h265e_vepu580.c index e8063311..dbfc2875 100644 --- a/mpp/hal/rkenc/h265e/hal_h265e_vepu580.c +++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu580.c @@ -2202,6 +2202,10 @@ static MPP_RET vepu580_h265e_save_pass1_patch(H265eV580RegSet *regs, H265eV580Ha mpp_dev_multi_offset_update(ctx->reg_cfg, 164, width_align * height); + /* NOTE: disable split to avoid lowdelay slice output */ + regs->reg_base.reg0216_sli_splt.sli_splt = 0; + regs->reg_base.reg0192_enc_pic.slen_fifo = 0; + return MPP_OK; }