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feat[vdpu383]: Add vdpu383 av1 module

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Support FBC, tile4x4, 400, 420

Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
Signed-off-by: Johnson Ding <johnson.ding@rock-chips.com>
Change-Id: Ie0c1ab47447c605b96f75313734db8bab46e77c8
This commit is contained in:
Hongjin Li
2023-11-14 14:40:47 +08:00
committed by Herman Chen
parent 7d4f01a0ff
commit 39b68064c8
14 changed files with 3171 additions and 88 deletions
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1
mpp/codec/dec/av1/av1.h
View File

@@ -172,5 +172,6 @@ enum {
#define PROFILE_AV1_HIGH 1 #define PROFILE_AV1_HIGH 1
#define PROFILE_AV1_PROFESSIONAL 2 #define PROFILE_AV1_PROFESSIONAL 2
#define AV1_MAX_TILES 128 #define AV1_MAX_TILES 128
#define INVALID_IDX -1
#endif /*__AV1_H__ */ #endif /*__AV1_H__ */

53
mpp/codec/dec/av1/av1d_cbs.c
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@@ -1226,6 +1226,18 @@ static RK_S32 mpp_av1_segmentation_params(AV1Context *ctx, BitReadCtx_t *gb,
} }
} }
infer(segmentation_id_last_active, 0);
infer(segmentation_id_preskip, 0);
for (i = 0; i < AV1_MAX_SEGMENTS; i++) {
for (j = 0; j < AV1_SEG_LVL_MAX; j++) {
if (current->feature_enabled[i][j]) {
infer(segmentation_id_last_active, i);
if ( j > AV1_SEG_LVL_REF_FRAME)
infer(segmentation_id_preskip, 1);
}
}
}
return 0; return 0;
__BITREAD_ERR: __BITREAD_ERR:
return MPP_ERR_STREAM; return MPP_ERR_STREAM;
@@ -1441,7 +1453,8 @@ static RK_S32 mpp_av1_read_tx_mode(AV1Context *ctx, BitReadCtx_t *gb,
infer(tx_mode, 0); infer(tx_mode, 0);
else { else {
flag(tx_mode); flag(tx_mode);
current->tx_mode = current->tx_mode ? 4 : 3; // current->tx_mode = current->tx_mode ? TX_MODE_SELECT : TX_MODE_LARGEST;
current->tx_mode = current->tx_mode ? 2 : 1;
} }
return 0; return 0;
@@ -1468,6 +1481,9 @@ static RK_S32 mpp_av1_skip_mode_params(AV1Context *ctx, BitReadCtx_t *gb,
RK_S32 skip_mode_allowed; RK_S32 skip_mode_allowed;
RK_S32 err; RK_S32 err;
ctx->skip_ref0 = 0;
ctx->skip_ref1 = 0;
if (current->frame_type == AV1_FRAME_KEY || if (current->frame_type == AV1_FRAME_KEY ||
current->frame_type == AV1_FRAME_INTRA_ONLY || current->frame_type == AV1_FRAME_INTRA_ONLY ||
!current->reference_select || !seq->enable_order_hint) { !current->reference_select || !seq->enable_order_hint) {
@@ -1800,8 +1816,7 @@ static RK_S32 mpp_av1_uncompressed_header(AV1Context *ctx, BitReadCtx_t *gb,
infer(render_width_minus_1, ref->render_width - 1); infer(render_width_minus_1, ref->render_width - 1);
infer(render_height_minus_1, ref->render_height - 1); infer(render_height_minus_1, ref->render_height - 1);
// Section 7.20 return 0;
goto update_refs;
} }
fb(2, frame_type); fb(2, frame_type);
@@ -1940,6 +1955,7 @@ static RK_S32 mpp_av1_uncompressed_header(AV1Context *ctx, BitReadCtx_t *gb,
} }
} }
current->ref_frame_valued = 1;
if (current->frame_type == AV1_FRAME_KEY || if (current->frame_type == AV1_FRAME_KEY ||
current->frame_type == AV1_FRAME_INTRA_ONLY) { current->frame_type == AV1_FRAME_INTRA_ONLY) {
CHECK(mpp_av1_frame_size(ctx, gb, current)); CHECK(mpp_av1_frame_size(ctx, gb, current));
@@ -1951,6 +1967,9 @@ static RK_S32 mpp_av1_uncompressed_header(AV1Context *ctx, BitReadCtx_t *gb,
else else
infer(allow_intrabc, 0); infer(allow_intrabc, 0);
// for (i = 0; i < AV1_REFS_PER_FRAME; i++)
// infer(ref_frame_idx[i], INVALID_IDX);
current->ref_frame_valued = 0;
} else { } else {
if (!seq->enable_order_hint) { if (!seq->enable_order_hint) {
infer(frame_refs_short_signaling, 0); infer(frame_refs_short_signaling, 0);
@@ -2112,34 +2131,6 @@ static RK_S32 mpp_av1_uncompressed_header(AV1Context *ctx, BitReadCtx_t *gb,
seq->color_config.subsampling_y + 1, ctx->bit_depth, seq->color_config.subsampling_y + 1, ctx->bit_depth,
ctx->tile_rows, ctx->tile_cols); ctx->tile_rows, ctx->tile_cols);
update_refs:
for (i = 0; i < AV1_NUM_REF_FRAMES; i++) {
if (current->refresh_frame_flags & (1 << i)) {
ctx->ref_s[i] = (AV1ReferenceFrameState) {
.valid = 1,
.frame_id = current->current_frame_id,
.upscaled_width = ctx->upscaled_width,
.frame_width = ctx->frame_width,
.frame_height = ctx->frame_height,
.render_width = ctx->render_width,
.render_height = ctx->render_height,
.frame_type = current->frame_type,
.subsampling_x = seq->color_config.subsampling_x,
.subsampling_y = seq->color_config.subsampling_y,
.bit_depth = ctx->bit_depth,
.order_hint = ctx->order_hint,
};
memcpy(ctx->ref_s[i].loop_filter_ref_deltas, current->loop_filter_ref_deltas,
sizeof(current->loop_filter_ref_deltas));
memcpy(ctx->ref_s[i].loop_filter_mode_deltas, current->loop_filter_mode_deltas,
sizeof(current->loop_filter_mode_deltas));
memcpy(ctx->ref_s[i].feature_enabled, current->feature_enabled,
sizeof(current->feature_enabled));
memcpy(ctx->ref_s[i].feature_value, current->feature_value,
sizeof(current->feature_value));
}
}
return 0; return 0;
} }

3
mpp/codec/dec/av1/av1d_cbs.h
View File

@@ -194,6 +194,7 @@ typedef struct AV1RawFrameHeader {
RK_U8 frame_refs_short_signaling; RK_U8 frame_refs_short_signaling;
RK_U8 last_frame_idx; RK_U8 last_frame_idx;
RK_U8 golden_frame_idx; RK_U8 golden_frame_idx;
RK_U8 ref_frame_valued;
RK_S8 ref_frame_idx[AV1_REFS_PER_FRAME]; RK_S8 ref_frame_idx[AV1_REFS_PER_FRAME];
RK_U32 delta_frame_id_minus1[AV1_REFS_PER_FRAME]; RK_U32 delta_frame_id_minus1[AV1_REFS_PER_FRAME];
@@ -236,6 +237,8 @@ typedef struct AV1RawFrameHeader {
RK_U8 segmentation_update_data; RK_U8 segmentation_update_data;
RK_U8 feature_enabled[AV1_MAX_SEGMENTS][AV1_SEG_LVL_MAX]; RK_U8 feature_enabled[AV1_MAX_SEGMENTS][AV1_SEG_LVL_MAX];
RK_S16 feature_value[AV1_MAX_SEGMENTS][AV1_SEG_LVL_MAX]; RK_S16 feature_value[AV1_MAX_SEGMENTS][AV1_SEG_LVL_MAX];
RK_U8 segmentation_id_last_active;
RK_U8 segmentation_id_preskip;
RK_U8 delta_q_present; RK_U8 delta_q_present;
RK_U8 delta_q_res; RK_U8 delta_q_res;

27
mpp/codec/dec/av1/av1d_parser.c
View File

@@ -673,6 +673,33 @@ static MPP_RET update_reference_list(Av1CodecContext *ctx)
RK_S32 bwd_buf_idx; RK_S32 bwd_buf_idx;
RK_S32 alt2_buf_idx; RK_S32 alt2_buf_idx;
for (i = 0; i < AV1_NUM_REF_FRAMES; i++) {
if (header->refresh_frame_flags & (1 << i)) {
s->ref_s[i] = (AV1ReferenceFrameState) {
.valid = 1,
.frame_id = header->current_frame_id,
.upscaled_width = s->upscaled_width,
.frame_width = s->frame_width,
.frame_height = s->frame_height,
.render_width = s->render_width,
.render_height = s->render_height,
.frame_type = header->frame_type,
.subsampling_x = s->sequence_header->color_config.subsampling_x,
.subsampling_y = s->sequence_header->color_config.subsampling_y,
.bit_depth = s->bit_depth,
.order_hint = s->order_hint,
};
memcpy(s->ref_s[i].loop_filter_ref_deltas, header->loop_filter_ref_deltas,
sizeof(header->loop_filter_ref_deltas));
memcpy(s->ref_s[i].loop_filter_mode_deltas, header->loop_filter_mode_deltas,
sizeof(header->loop_filter_mode_deltas));
memcpy(s->ref_s[i].feature_enabled, header->feature_enabled,
sizeof(header->feature_enabled));
memcpy(s->ref_s[i].feature_value, header->feature_value,
sizeof(header->feature_value));
}
}
if (!header->show_existing_frame) { if (!header->show_existing_frame) {
lst2_buf_idx = s->raw_frame_header->ref_frame_idx[AV1_REF_FRAME_LAST2 - AV1_REF_FRAME_LAST]; lst2_buf_idx = s->raw_frame_header->ref_frame_idx[AV1_REF_FRAME_LAST2 - AV1_REF_FRAME_LAST];
lst3_buf_idx = s->raw_frame_header->ref_frame_idx[AV1_REF_FRAME_LAST3 - AV1_REF_FRAME_LAST]; lst3_buf_idx = s->raw_frame_header->ref_frame_idx[AV1_REF_FRAME_LAST3 - AV1_REF_FRAME_LAST];

82
mpp/codec/dec/av1/av1d_parser2_syntax.c
View File

@@ -1,17 +1,6 @@
/* SPDX-License-Identifier: Apache-2.0 OR MIT */
/* /*
* Copyright 2021 Rockchip Electronics Co. LTD * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/ */
#define MODULE_TAG "av1d_parser2syntax" #define MODULE_TAG "av1d_parser2syntax"
@@ -41,38 +30,32 @@ static int av1d_fill_picparams(Av1CodecContext *ctx, DXVA_PicParams_AV1 *pp)
pp->max_width = seq->max_frame_width_minus_1 + 1; pp->max_width = seq->max_frame_width_minus_1 + 1;
pp->max_height = seq->max_frame_height_minus_1 + 1; pp->max_height = seq->max_frame_height_minus_1 + 1;
pp->CurrPic.Index7Bits = h->cur_frame.slot_index;
pp->CurrPicTextureIndex = h->cur_frame.slot_index; pp->CurrPicTextureIndex = h->cur_frame.slot_index;
pp->superres_denom = frame_header->use_superres ? frame_header->coded_denom : AV1_SUPERRES_NUM; pp->superres_denom = frame_header->use_superres ? frame_header->coded_denom : AV1_SUPERRES_NUM;
pp->bitdepth = h->bit_depth; pp->bitdepth = h->bit_depth;
pp->seq_profile = seq->seq_profile; pp->seq_profile = seq->seq_profile;
pp->frame_header_size = h->frame_header_size;
/* Tiling info */ /* Tiling info */
pp->tiles.cols = frame_header->tile_cols; pp->tiles.cols = frame_header->tile_cols;
pp->tiles.rows = frame_header->tile_rows; pp->tiles.rows = frame_header->tile_rows;
pp->tiles.context_update_id = frame_header->context_update_tile_id; pp->tiles.context_update_id = frame_header->context_update_tile_id;
{ for (i = 0; i < pp->tiles.cols; i++)
RK_U8 val = 0; pp->tiles.widths[i] = frame_header->width_in_sbs_minus_1[i] + 1;
for (i = 0; i < pp->tiles.cols; i++) {
pp->tiles.widths[i] = val;
val += frame_header->width_in_sbs_minus_1[i] + 1;
}
pp->tiles.widths[i] = val;
val = 0; for (i = 0; i < pp->tiles.rows; i++)
for (i = 0; i < pp->tiles.rows; i++) { pp->tiles.heights[i] = frame_header->height_in_sbs_minus_1[i] + 1;
pp->tiles.heights[i] = val;
val += frame_header->height_in_sbs_minus_1[i] + 1;
}
pp->tiles.heights[i] = val;
}
for (i = 0; i < AV1_MAX_TILES; i++) { for (i = 0; i < AV1_MAX_TILES; i++) {
pp->tiles.tile_offset_start[i] = h->tile_offset_start[i]; pp->tiles.tile_offset_start[i] = h->tile_offset_start[i];
pp->tiles.tile_offset_end[i] = h->tile_offset_end[i]; pp->tiles.tile_offset_end[i] = h->tile_offset_end[i];
} }
pp->tiles.tile_sz_mag = h->raw_frame_header->tile_size_bytes_minus1; pp->tiles.tile_sz_mag = h->raw_frame_header->tile_size_bytes_minus1;
/* Coding tools */ /* Coding tools */
pp->coding.current_operating_point = seq->operating_point_idc[h->operating_point_idc];
pp->coding.use_128x128_superblock = seq->use_128x128_superblock; pp->coding.use_128x128_superblock = seq->use_128x128_superblock;
pp->coding.intra_edge_filter = seq->enable_intra_edge_filter; pp->coding.intra_edge_filter = seq->enable_intra_edge_filter;
pp->coding.interintra_compound = seq->enable_interintra_compound; pp->coding.interintra_compound = seq->enable_interintra_compound;
@@ -109,16 +92,21 @@ static int av1d_fill_picparams(Av1CodecContext *ctx, DXVA_PicParams_AV1 *pp)
pp->format.subsampling_x = seq->color_config.subsampling_x; pp->format.subsampling_x = seq->color_config.subsampling_x;
pp->format.subsampling_y = seq->color_config.subsampling_y; pp->format.subsampling_y = seq->color_config.subsampling_y;
pp->format.mono_chrome = seq->color_config.mono_chrome; pp->format.mono_chrome = seq->color_config.mono_chrome;
pp->coded_lossless = h->cur_frame.coded_lossless; pp->coded_lossless = h->cur_frame.coded_lossless;
pp->all_lossless = h->all_lossless;
/* References */ /* References */
pp->primary_ref_frame = frame_header->primary_ref_frame; pp->primary_ref_frame = frame_header->primary_ref_frame;
pp->order_hint = frame_header->order_hint; pp->order_hint = frame_header->order_hint;
pp->order_hint_bits = seq->enable_order_hint ? seq->order_hint_bits_minus_1 + 1 : 0; pp->order_hint_bits = seq->enable_order_hint ? seq->order_hint_bits_minus_1 + 1 : 0;
pp->ref_frame_valued = frame_header->ref_frame_valued;
for (i = 0; i < AV1_REFS_PER_FRAME; i++)
pp->ref_frame_idx[i] = frame_header->ref_frame_idx[i];
memset(pp->RefFrameMapTextureIndex, 0xFF, sizeof(pp->RefFrameMapTextureIndex)); memset(pp->RefFrameMapTextureIndex, 0xFF, sizeof(pp->RefFrameMapTextureIndex));
for (i = 0; i < AV1_REFS_PER_FRAME; i++) { for (i = 0; i < AV1_NUM_REF_FRAMES; i++) {
int8_t ref_idx = frame_header->ref_frame_idx[i]; // int8_t ref_idx = frame_header->ref_frame_idx[i];
AV1Frame *ref_frame = &h->ref[ref_idx]; AV1Frame *ref_frame = &h->ref[i];
RefInfo *ref_i = ref_frame->ref; RefInfo *ref_i = ref_frame->ref;
if (ref_frame->f) { if (ref_frame->f) {
@@ -149,6 +137,23 @@ static int av1d_fill_picparams(Av1CodecContext *ctx, DXVA_PicParams_AV1 *pp)
pp->frame_refs[i].gamma = h->cur_frame.gm_params[AV1_REF_FRAME_LAST + i].gamma; pp->frame_refs[i].gamma = h->cur_frame.gm_params[AV1_REF_FRAME_LAST + i].gamma;
pp->frame_refs[i].delta = h->cur_frame.gm_params[AV1_REF_FRAME_LAST + i].delta; pp->frame_refs[i].delta = h->cur_frame.gm_params[AV1_REF_FRAME_LAST + i].delta;
} }
for (i = 0; i < AV1_NUM_REF_FRAMES; i++) {
pp->frame_ref_state[i].valid = h->ref_s[i].valid ;
pp->frame_ref_state[i].frame_id = h->ref_s[i].frame_id ;
pp->frame_ref_state[i].upscaled_width = h->ref_s[i].upscaled_width;
pp->frame_ref_state[i].frame_width = h->ref_s[i].frame_width ;
pp->frame_ref_state[i].frame_height = h->ref_s[i].frame_height ;
pp->frame_ref_state[i].render_width = h->ref_s[i].render_width ;
pp->frame_ref_state[i].render_height = h->ref_s[i].render_height ;
pp->frame_ref_state[i].frame_type = h->ref_s[i].frame_type ;
pp->frame_ref_state[i].subsampling_x = h->ref_s[i].subsampling_x ;
pp->frame_ref_state[i].subsampling_y = h->ref_s[i].subsampling_y ;
pp->frame_ref_state[i].bit_depth = h->ref_s[i].bit_depth ;
pp->frame_ref_state[i].order_hint = h->ref_s[i].order_hint ;
}
for (i = 0; i < AV1_NUM_REF_FRAMES; i++)
pp->ref_order_hint[i] = frame_header->ref_order_hint[i];
for (i = 0; i < AV1_NUM_REF_FRAMES; i++) { for (i = 0; i < AV1_NUM_REF_FRAMES; i++) {
AV1Frame *ref_frame = &h->ref[i]; AV1Frame *ref_frame = &h->ref[i];
if (ref_frame->slot_index < 0x7f) if (ref_frame->slot_index < 0x7f)
@@ -179,9 +184,9 @@ static int av1d_fill_picparams(Av1CodecContext *ctx, DXVA_PicParams_AV1 *pp)
pp->loop_filter.frame_restoration_type[1] = remap_lr_type[frame_header->lr_type[1]]; pp->loop_filter.frame_restoration_type[1] = remap_lr_type[frame_header->lr_type[1]];
pp->loop_filter.frame_restoration_type[2] = remap_lr_type[frame_header->lr_type[2]]; pp->loop_filter.frame_restoration_type[2] = remap_lr_type[frame_header->lr_type[2]];
uses_lr = frame_header->lr_type[0] || frame_header->lr_type[1] || frame_header->lr_type[2]; uses_lr = frame_header->lr_type[0] || frame_header->lr_type[1] || frame_header->lr_type[2];
pp->loop_filter.log2_restoration_unit_size[0] = uses_lr ? (1 + frame_header->lr_unit_shift) : 3; pp->loop_filter.log2_restoration_unit_size[0] = uses_lr ? (1 + frame_header->lr_unit_shift) : 0;
pp->loop_filter.log2_restoration_unit_size[1] = uses_lr ? (1 + frame_header->lr_unit_shift - frame_header->lr_uv_shift) : 3; pp->loop_filter.log2_restoration_unit_size[1] = uses_lr ? (1 + frame_header->lr_unit_shift - frame_header->lr_uv_shift) : 0;
pp->loop_filter.log2_restoration_unit_size[2] = uses_lr ? (1 + frame_header->lr_unit_shift - frame_header->lr_uv_shift) : 3; pp->loop_filter.log2_restoration_unit_size[2] = uses_lr ? (1 + frame_header->lr_unit_shift - frame_header->lr_uv_shift) : 0;
/* Quantization */ /* Quantization */
pp->quantization.delta_q_present = frame_header->delta_q_present; pp->quantization.delta_q_present = frame_header->delta_q_present;
@@ -192,12 +197,13 @@ static int av1d_fill_picparams(Av1CodecContext *ctx, DXVA_PicParams_AV1 *pp)
pp->quantization.v_dc_delta_q = frame_header->delta_q_v_dc; pp->quantization.v_dc_delta_q = frame_header->delta_q_v_dc;
pp->quantization.u_ac_delta_q = frame_header->delta_q_u_ac; pp->quantization.u_ac_delta_q = frame_header->delta_q_u_ac;
pp->quantization.v_ac_delta_q = frame_header->delta_q_v_ac; pp->quantization.v_ac_delta_q = frame_header->delta_q_v_ac;
pp->quantization.using_qmatrix = frame_header->using_qmatrix;
pp->quantization.qm_y = frame_header->using_qmatrix ? frame_header->qm_y : 0xFF; pp->quantization.qm_y = frame_header->using_qmatrix ? frame_header->qm_y : 0xFF;
pp->quantization.qm_u = frame_header->using_qmatrix ? frame_header->qm_u : 0xFF; pp->quantization.qm_u = frame_header->using_qmatrix ? frame_header->qm_u : 0xFF;
pp->quantization.qm_v = frame_header->using_qmatrix ? frame_header->qm_v : 0xFF; pp->quantization.qm_v = frame_header->using_qmatrix ? frame_header->qm_v : 0xFF;
/* Cdef parameters */ /* Cdef parameters */
pp->cdef.damping = frame_header->cdef_damping_minus_3; pp->cdef.damping = frame_header->cdef_damping_minus_3 + 3;
pp->cdef.bits = frame_header->cdef_bits; pp->cdef.bits = frame_header->cdef_bits;
for (i = 0; i < 8; i++) { for (i = 0; i < 8; i++) {
pp->cdef.y_strengths[i].primary = frame_header->cdef_y_pri_strength[i]; pp->cdef.y_strengths[i].primary = frame_header->cdef_y_pri_strength[i];
@@ -220,8 +226,11 @@ static int av1d_fill_picparams(Av1CodecContext *ctx, DXVA_PicParams_AV1 *pp)
pp->segmentation.feature_data[i][j] = frame_header->feature_value[i][j]; pp->segmentation.feature_data[i][j] = frame_header->feature_value[i][j];
} }
} }
pp->segmentation.last_active = frame_header->segmentation_id_last_active;
pp->segmentation.last_active = frame_header->segmentation_id_preskip;
/* Film grain */ /* Film grain */
pp->film_grain.matrix_coefficients = seq->color_config.matrix_coefficients;
if (apply_grain) { if (apply_grain) {
pp->film_grain.apply_grain = 1; pp->film_grain.apply_grain = 1;
pp->film_grain.scaling_shift_minus8 = film_grain->grain_scaling_minus_8; pp->film_grain.scaling_shift_minus8 = film_grain->grain_scaling_minus_8;
@@ -234,6 +243,7 @@ static int av1d_fill_picparams(Av1CodecContext *ctx, DXVA_PicParams_AV1 *pp)
pp->film_grain.matrix_coeff_is_identity = (seq->color_config.matrix_coefficients == MPP_FRAME_SPC_RGB); pp->film_grain.matrix_coeff_is_identity = (seq->color_config.matrix_coefficients == MPP_FRAME_SPC_RGB);
pp->film_grain.grain_seed = film_grain->grain_seed; pp->film_grain.grain_seed = film_grain->grain_seed;
pp->film_grain.update_grain = film_grain->update_grain;
pp->film_grain.num_y_points = film_grain->num_y_points; pp->film_grain.num_y_points = film_grain->num_y_points;
for (i = 0; i < film_grain->num_y_points; i++) { for (i = 0; i < film_grain->num_y_points; i++) {
pp->film_grain.scaling_points_y[i][0] = film_grain->point_y_value[i]; pp->film_grain.scaling_points_y[i][0] = film_grain->point_y_value[i];
@@ -266,6 +276,7 @@ static int av1d_fill_picparams(Av1CodecContext *ctx, DXVA_PicParams_AV1 *pp)
} }
pp->upscaled_width = h->upscaled_width; pp->upscaled_width = h->upscaled_width;
pp->frame_to_show_map_idx = frame_header->frame_to_show_map_idx; pp->frame_to_show_map_idx = frame_header->frame_to_show_map_idx;
pp->show_existing_frame = frame_header->show_existing_frame;
pp->frame_tag_size = h->frame_tag_size; pp->frame_tag_size = h->frame_tag_size;
pp->skip_ref0 = h->skip_ref0; pp->skip_ref0 = h->skip_ref0;
pp->skip_ref1 = h->skip_ref1; pp->skip_ref1 = h->skip_ref1;
@@ -274,6 +285,7 @@ static int av1d_fill_picparams(Av1CodecContext *ctx, DXVA_PicParams_AV1 *pp)
pp->cdfs = h->cdfs; pp->cdfs = h->cdfs;
pp->cdfs_ndvc = h->cdfs_ndvc; pp->cdfs_ndvc = h->cdfs_ndvc;
pp->tile_cols_log2 = frame_header->tile_cols_log2; pp->tile_cols_log2 = frame_header->tile_cols_log2;
pp->tile_rows_log2 = frame_header->tile_rows_log2;
// XXX: Setting the StatusReportFeedbackNumber breaks decoding on some drivers (tested on NVIDIA 457.09) // XXX: Setting the StatusReportFeedbackNumber breaks decoding on some drivers (tested on NVIDIA 457.09)
// Status Reporting is not used by FFmpeg, hence not providing a number does not cause any issues // Status Reporting is not used by FFmpeg, hence not providing a number does not cause any issues
//pp->StatusReportFeedbackNumber = 1 + DXVA_CONTEXT_REPORT_ID(avctx, ctx)++; //pp->StatusReportFeedbackNumber = 1 + DXVA_CONTEXT_REPORT_ID(avctx, ctx)++;

34
mpp/common/av1d_syntax.h
View File

@@ -54,8 +54,10 @@ typedef struct _DXVA_PicParams_AV1 {
USHORT superres_denom ; USHORT superres_denom ;
USHORT bitdepth ; USHORT bitdepth ;
USHORT seq_profile ; USHORT seq_profile ;
USHORT frame_header_size ;
union { union {
struct { struct {
UINT32 current_operating_point : 12;
UINT32 use_128x128_superblock : 1; UINT32 use_128x128_superblock : 1;
UINT32 intra_edge_filter : 1; UINT32 intra_edge_filter : 1;
UINT32 interintra_compound : 1; UINT32 interintra_compound : 1;
@@ -83,6 +85,7 @@ typedef struct _DXVA_PicParams_AV1 {
UINT32 enable_ref_frame_mvs : 1; UINT32 enable_ref_frame_mvs : 1;
UINT32 reference_frame_update : 1; UINT32 reference_frame_update : 1;
UINT32 error_resilient_mode : 1; UINT32 error_resilient_mode : 1;
UINT32 film_grain_params_present : 1;
} coding; } coding;
}; };
@@ -135,6 +138,7 @@ typedef struct _DXVA_PicParams_AV1 {
CHAR v_dc_delta_q ; CHAR v_dc_delta_q ;
CHAR u_ac_delta_q ; CHAR u_ac_delta_q ;
CHAR v_ac_delta_q ; CHAR v_ac_delta_q ;
CHAR using_qmatrix ;
UCHAR qm_y ; UCHAR qm_y ;
UCHAR qm_u ; UCHAR qm_u ;
UCHAR qm_v ; UCHAR qm_v ;
@@ -161,6 +165,8 @@ typedef struct _DXVA_PicParams_AV1 {
UCHAR temporal_update ; UCHAR temporal_update ;
UCHAR feature_mask[8] ; UCHAR feature_mask[8] ;
INT feature_data[8][8]; INT feature_data[8][8];
UCHAR last_active ;
UCHAR preskip ;
} segmentation; } segmentation;
struct { struct {
@@ -172,6 +178,7 @@ typedef struct _DXVA_PicParams_AV1 {
UCHAR grain_scale_shift ; UCHAR grain_scale_shift ;
UCHAR overlap_flag ; UCHAR overlap_flag ;
UCHAR clip_to_restricted_range ; UCHAR clip_to_restricted_range ;
UCHAR matrix_coefficients ;
UCHAR matrix_coeff_is_identity ; UCHAR matrix_coeff_is_identity ;
UCHAR num_y_points ; UCHAR num_y_points ;
UCHAR num_cb_points ; UCHAR num_cb_points ;
@@ -188,10 +195,15 @@ typedef struct _DXVA_PicParams_AV1 {
UCHAR cr_luma_mult ; UCHAR cr_luma_mult ;
USHORT grain_seed ; USHORT grain_seed ;
USHORT update_grain ;
USHORT cb_offset ; USHORT cb_offset ;
USHORT cr_offset ; USHORT cr_offset ;
} film_grain; } film_grain;
UINT32 ref_frame_valued;
UINT32 ref_frame_idx[7];
UINT32 ref_order_hint[8];
struct { struct {
UINT32 width; UINT32 width;
UINT32 height; UINT32 height;
@@ -210,13 +222,32 @@ typedef struct _DXVA_PicParams_AV1 {
UCHAR wmtype; UCHAR wmtype;
RK_S32 wmmat[6]; RK_S32 wmmat[6];
USHORT alpha, beta, gamma, delta; USHORT alpha, beta, gamma, delta;
} frame_refs[7]; } frame_refs[8];
struct {
RK_S32 valid; // RefValid
RK_S32 frame_id; // RefFrameId
RK_S32 upscaled_width; // RefUpscaledWidth
RK_S32 frame_width; // RefFrameWidth
RK_S32 frame_height; // RefFrameHeight
RK_S32 render_width; // RefRenderWidth
RK_S32 render_height; // RefRenderHeight
RK_S32 frame_type; // RefFrameType
RK_S32 subsampling_x; // RefSubsamplingX
RK_S32 subsampling_y; // RefSubsamplingY
RK_S32 bit_depth; // RefBitDepth
RK_S32 order_hint; // RefOrderHint
} frame_ref_state[8];
RK_U8 ref_frame_sign_bias[8];
UCHAR coded_lossless; UCHAR coded_lossless;
RK_S32 all_lossless;
UCHAR interp_filter; UCHAR interp_filter;
UCHAR RefFrameMapTextureIndex[7]; UCHAR RefFrameMapTextureIndex[7];
UINT32 upscaled_width; UINT32 upscaled_width;
UINT32 frame_to_show_map_idx; UINT32 frame_to_show_map_idx;
UINT32 show_existing_frame;
UINT32 frame_tag_size; UINT32 frame_tag_size;
UINT32 offset_to_dct_parts; UINT32 offset_to_dct_parts;
UCHAR skip_ref0; UCHAR skip_ref0;
@@ -225,6 +256,7 @@ typedef struct _DXVA_PicParams_AV1 {
void *cdfs; void *cdfs;
void *cdfs_ndvc; void *cdfs_ndvc;
RK_U8 tile_cols_log2; RK_U8 tile_cols_log2;
RK_U8 tile_rows_log2;
} DXVA_PicParams_AV1, *LPDXVA_PicParams_AV1; } DXVA_PicParams_AV1, *LPDXVA_PicParams_AV1;
typedef struct _DXVA_Slice_AV1_Short { typedef struct _DXVA_Slice_AV1_Short {

5
mpp/hal/vpu/av1d/CMakeLists.txt
View File

@@ -1,5 +1,7 @@
# vim: syntax=cmake # vim: syntax=cmake
# hal jpeg reg # hal av1 reg
include_directories(../../rkdec/inc)
set(HAL_AV1D_HDR set(HAL_AV1D_HDR
hal_av1d_common.h hal_av1d_common.h
@@ -8,6 +10,7 @@ set(HAL_AV1D_HDR
set(HAL_AV1D_SRC set(HAL_AV1D_SRC
hal_av1d_api.c hal_av1d_api.c
hal_av1d_vdpu.c hal_av1d_vdpu.c
hal_av1d_vdpu383.c
film_grain_noise_table.c film_grain_noise_table.c
) )

14
mpp/hal/vpu/av1d/av1d_common.h
View File

@@ -29,6 +29,10 @@
#define AV1_MAX_TILE_COL 64 #define AV1_MAX_TILE_COL 64
#define AV1_MAX_TILE_ROW 64 #define AV1_MAX_TILE_ROW 64
// Pixels per Mode Info (MI) unit
#define MI_SIZE_LOG2 2
#define MI_SIZE (1 << MI_SIZE_LOG2)
#define AV1_MIN_COMP_BASIS 8 #define AV1_MIN_COMP_BASIS 8
#define AV1_MAX_CODED_FRAME_SIZE \ #define AV1_MAX_CODED_FRAME_SIZE \
(8192 * 4352 * 10 * 6 / 32 / AV1_MIN_COMP_BASIS) /* approx 8 MB */ (8192 * 4352 * 10 * 6 / 32 / AV1_MIN_COMP_BASIS) /* approx 8 MB */
@@ -214,6 +218,14 @@ typedef RK_U8 av1_coeff_probs[REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS]
typedef RK_U16 av1_cdf; typedef RK_U16 av1_cdf;
// Frame Restoration types (section 6.10.15)
enum {
AV1_RESTORE_NONE = 0,
AV1_RESTORE_WIENER = 1,
AV1_RESTORE_SGRPROJ = 2,
AV1_RESTORE_SWITCHABLE = 3,
};
enum BlockSizeType { enum BlockSizeType {
BLOCK_SIZE_AB4X4, BLOCK_SIZE_AB4X4,
BLOCK_SIZE_SB4X8, BLOCK_SIZE_SB4X8,
@@ -263,6 +275,8 @@ enum PartitionType {
enum FrameType { enum FrameType {
KEY_FRAME = 0, KEY_FRAME = 0,
INTER_FRAME = 1, INTER_FRAME = 1,
INTRA_ONLY_FRAME = 2, // replaces intra-only
S_FRAME = 3,
NUM_FRAME_TYPES, NUM_FRAME_TYPES,
}; };

11
mpp/hal/vpu/av1d/hal_av1d_api.c
View File

@@ -31,6 +31,7 @@
#include "hal_av1d_vdpu_reg.h" #include "hal_av1d_vdpu_reg.h"
#include "hal_av1d_vdpu.h" #include "hal_av1d_vdpu.h"
#include "hal_av1d_vdpu383.h"
#include "hal_av1d_common.h" #include "hal_av1d_common.h"
RK_U32 hal_av1d_debug = 0; RK_U32 hal_av1d_debug = 0;
@@ -40,7 +41,8 @@ MPP_RET hal_av1d_init(void *hal, MppHalCfg *cfg)
MPP_RET ret = MPP_OK; MPP_RET ret = MPP_OK;
Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
RK_U32 vcodec_type = mpp_get_vcodec_type(); RK_U32 vcodec_type = mpp_get_vcodec_type();
MppClientType type = VPU_CLIENT_AV1DEC; MppClientType type = VPU_CLIENT_RKVDEC;
RK_U32 hw_id = 0;
INP_CHECK(ret, NULL == p_hal); INP_CHECK(ret, NULL == p_hal);
memset(p_hal, 0, sizeof(Av1dHalCtx)); memset(p_hal, 0, sizeof(Av1dHalCtx));
@@ -52,7 +54,12 @@ MPP_RET hal_av1d_init(void *hal, MppHalCfg *cfg)
return ret; return ret;
} }
p_hal->api = &hal_av1d_vdpu; hw_id = mpp_get_client_hw_id(type);
if (hw_id == HWID_VDPU383) {
p_hal->api = &hal_av1d_vdpu383;
} else {
p_hal->api = &hal_av1d_vdpu;
}
//!< callback function to parser module //!< callback function to parser module
p_hal->dec_cb = cfg->dec_cb; p_hal->dec_cb = cfg->dec_cb;

3
mpp/hal/vpu/av1d/hal_av1d_common.h
View File

@@ -34,7 +34,6 @@
extern RK_U32 hal_av1d_debug; extern RK_U32 hal_av1d_debug;
#define AV1D_DBG(level, fmt, ...)\ #define AV1D_DBG(level, fmt, ...)\
do {\ do {\
if (level & hal_av1d_debug)\ if (level & hal_av1d_debug)\
@@ -191,4 +190,4 @@ typedef struct av1d_hal_ctx_t {
RK_U32 fast_mode; RK_U32 fast_mode;
} Av1dHalCtx; } Av1dHalCtx;
#endif /*__HAL_AV1D_GLOBAL_H__*/ #endif /* __HAL_AV1D_GLOBAL_H__ */

32
mpp/hal/vpu/av1d/hal_av1d_vdpu.c
View File

@@ -676,7 +676,7 @@ static void set_ref_sign_bias(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val)
#define MAX_FRAME_DISTANCE 31 #define MAX_FRAME_DISTANCE 31
#define MAX_ACTIVE_REFS AV1_ACTIVE_REFS_EX #define MAX_ACTIVE_REFS AV1_ACTIVE_REFS_EX
RK_S32 GetRelativeDist(DXVA_PicParams_AV1 *dxva, RK_S32 a, RK_S32 b) static RK_S32 GetRelativeDist(DXVA_PicParams_AV1 *dxva, RK_S32 a, RK_S32 b)
{ {
if (!dxva->order_hint_bits) return 0; if (!dxva->order_hint_bits) return 0;
const RK_S32 bits = dxva->order_hint_bits - 1; const RK_S32 bits = dxva->order_hint_bits - 1;
@@ -733,7 +733,7 @@ RK_S32 GetRelativeDist(DXVA_PicParams_AV1 *dxva, RK_S32 a, RK_S32 b)
} }
void set_frame_sign_bias(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) static void set_frame_sign_bias(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
{ {
RK_U32 i = 0; RK_U32 i = 0;
VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx; VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;
@@ -757,7 +757,7 @@ void set_frame_sign_bias(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
} }
} }
void vdpu_av1d_set_prob(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) static void vdpu_av1d_set_prob(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
{ {
VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx; VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;
const int mv_cdf_offset = offsetof(AV1CDFs, mv_cdf); const int mv_cdf_offset = offsetof(AV1CDFs, mv_cdf);
@@ -776,7 +776,7 @@ void vdpu_av1d_set_prob(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
regs->addr_cfg.swreg173.sw_prob_tab_base_lsb = mpp_buffer_get_fd(reg_ctx->prob_tbl_base); regs->addr_cfg.swreg173.sw_prob_tab_base_lsb = mpp_buffer_get_fd(reg_ctx->prob_tbl_base);
} }
void vdpu_av1d_set_reference_frames(Av1dHalCtx *p_hal, VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva) static void vdpu_av1d_set_reference_frames(Av1dHalCtx *p_hal, VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva)
{ {
RK_U32 tmp1, tmp2, i; RK_U32 tmp1, tmp2, i;
RK_U32 cur_height, cur_width; RK_U32 cur_height, cur_width;
@@ -1097,7 +1097,7 @@ void vdpu_av1d_set_reference_frames(Av1dHalCtx *p_hal, VdpuAv1dRegCtx *ctx, DXVA
} }
#undef MAX_FRAME_DISTANCE #undef MAX_FRAME_DISTANCE
void vdpu_av1d_superres_params(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) static void vdpu_av1d_superres_params(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
{ {
// Compute and store scaling paramers needed for superres // Compute and store scaling paramers needed for superres
#define SUPERRES_SCALE_BITS 3 #define SUPERRES_SCALE_BITS 3
@@ -1209,7 +1209,7 @@ end:
} }
void vdpu_av1d_set_picture_dimensions(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) static void vdpu_av1d_set_picture_dimensions(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
{ {
/* Write dimensions for the current picture /* Write dimensions for the current picture
(This is needed when scaling is used) */ (This is needed when scaling is used) */
@@ -1227,7 +1227,7 @@ void vdpu_av1d_set_picture_dimensions(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxv
vdpu_av1d_superres_params(p_hal, dxva); vdpu_av1d_superres_params(p_hal, dxva);
} }
void vdpu_av1d_set_segmentation(VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva) static void vdpu_av1d_set_segmentation(VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva)
{ {
RK_U32 segval[MAX_MB_SEGMENTS][SEG_AV1_LVL_MAX]; RK_U32 segval[MAX_MB_SEGMENTS][SEG_AV1_LVL_MAX];
VdpuAv1dRegSet *regs = ctx->regs; VdpuAv1dRegSet *regs = ctx->regs;
@@ -1391,7 +1391,7 @@ void vdpu_av1d_set_segmentation(VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva)
regs->swreg27.sw_global_mv_seg7 = segval[7][SEG_AV1_LVL_GLOBALMV]; regs->swreg27.sw_global_mv_seg7 = segval[7][SEG_AV1_LVL_GLOBALMV];
} }
void vdpu_av1d_set_loopfilter(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) static void vdpu_av1d_set_loopfilter(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
{ {
VdpuAv1dRegCtx *ctx = p_hal->reg_ctx; VdpuAv1dRegCtx *ctx = p_hal->reg_ctx;
VdpuAv1dRegSet *regs = ctx->regs; VdpuAv1dRegSet *regs = ctx->regs;
@@ -1427,7 +1427,7 @@ void vdpu_av1d_set_loopfilter(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
mpp_dev_set_reg_offset(p_hal->dev, 183, ctx->filt_info[DB_CTRL_COL].offset); mpp_dev_set_reg_offset(p_hal->dev, 183, ctx->filt_info[DB_CTRL_COL].offset);
} }
void vdpu_av1d_set_global_model(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) static void vdpu_av1d_set_global_model(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
{ {
VdpuAv1dRegCtx *ctx = p_hal->reg_ctx; VdpuAv1dRegCtx *ctx = p_hal->reg_ctx;
VdpuAv1dRegSet *regs = ctx->regs; VdpuAv1dRegSet *regs = ctx->regs;
@@ -1469,7 +1469,7 @@ void vdpu_av1d_set_global_model(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
regs->addr_cfg.swreg83.sw_global_model_base_lsb = mpp_buffer_get_fd(ctx->global_model); regs->addr_cfg.swreg83.sw_global_model_base_lsb = mpp_buffer_get_fd(ctx->global_model);
} }
void vdpu_av1d_set_tile_info_regs(VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva) static void vdpu_av1d_set_tile_info_regs(VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva)
{ {
int transpose = ctx->tile_transpose; int transpose = ctx->tile_transpose;
VdpuAv1dRegSet *regs = ctx->regs; VdpuAv1dRegSet *regs = ctx->regs;
@@ -1518,7 +1518,7 @@ static int check_tile_width(DXVA_PicParams_AV1 *dxva, RK_S32 width, RK_S32 leftm
return valid; return valid;
} }
void vdpu_av1d_set_tile_info_mem(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) static void vdpu_av1d_set_tile_info_mem(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
{ {
VdpuAv1dRegCtx *ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx; VdpuAv1dRegCtx *ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;
@@ -1589,7 +1589,7 @@ void vdpu_av1d_set_tile_info_mem(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
mpp_buffer_sync_end(ctx->tile_info); mpp_buffer_sync_end(ctx->tile_info);
} }
void vdpu_av1d_set_cdef(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) static void vdpu_av1d_set_cdef(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
{ {
RK_U32 luma_pri_strength = 0; RK_U32 luma_pri_strength = 0;
RK_U16 luma_sec_strength = 0; RK_U16 luma_sec_strength = 0;
@@ -1621,7 +1621,7 @@ void vdpu_av1d_set_cdef(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
mpp_dev_set_reg_offset(p_hal->dev, 85, ctx->filt_info[CDEF_COL].offset); mpp_dev_set_reg_offset(p_hal->dev, 85, ctx->filt_info[CDEF_COL].offset);
} }
void vdpu_av1d_set_lr(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) static void vdpu_av1d_set_lr(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
{ {
VdpuAv1dRegCtx *ctx = p_hal->reg_ctx; VdpuAv1dRegCtx *ctx = p_hal->reg_ctx;
VdpuAv1dRegSet *regs = ctx->regs; VdpuAv1dRegSet *regs = ctx->regs;
@@ -1639,8 +1639,8 @@ void vdpu_av1d_set_lr(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
mpp_dev_set_reg_offset(p_hal->dev, 91, ctx->filt_info[LR_COL].offset); mpp_dev_set_reg_offset(p_hal->dev, 91, ctx->filt_info[LR_COL].offset);
} }
void init_scaling_function(RK_U8 scaling_points[][2], RK_U8 num_points, static void init_scaling_function(RK_U8 scaling_points[][2], RK_U8 num_points,
RK_U8 scaling_lut[]) RK_U8 scaling_lut[])
{ {
RK_S32 i, point; RK_S32 i, point;
@@ -1668,7 +1668,7 @@ void init_scaling_function(RK_U8 scaling_points[][2], RK_U8 num_points,
scaling_lut[i] = scaling_points[num_points - 1][1]; scaling_lut[i] = scaling_points[num_points - 1][1];
} }
void vdpu_av1d_set_fgs(VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva) static void vdpu_av1d_set_fgs(VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva)
{ {
VdpuAv1dRegSet *regs = ctx->regs; VdpuAv1dRegSet *regs = ctx->regs;
RK_S32 ar_coeffs_y[24]; RK_S32 ar_coeffs_y[24];

2601
mpp/hal/vpu/av1d/hal_av1d_vdpu383.c Normal file
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File diff suppressed because it is too large Load Diff

22
mpp/hal/vpu/av1d/hal_av1d_vdpu383.h Normal file
View File

@@ -0,0 +1,22 @@
/* SPDX-License-Identifier: Apache-2.0 OR MIT */
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*/
#ifndef __HAL_AV1D_VDPU383_H__
#define __HAL_AV1D_VDPU383_H__
#include "mpp_hal.h"
#include "vdpu383.h"
#ifdef __cplusplus
extern "C" {
#endif
extern const MppHalApi hal_av1d_vdpu383;
#ifdef __cplusplus
}
#endif
#endif /* __HAL_AV1D_VDPU383_H__ */

371
mpp/hal/vpu/av1d/hal_av1d_vdpu383_reg.h Normal file
View File

@@ -0,0 +1,371 @@
/* SPDX-License-Identifier: Apache-2.0 OR MIT */
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*/
#ifndef __HAL_AV1D_VDPU383_REG_H__
#define __HAL_AV1D_VDPU383_REG_H__
#include "rk_type.h"
#include "vdpu383_com.h"
typedef struct Vdpu383RegComPktAddr_t {
/* SWREG128_STRM_BASE */
RK_U32 reg128_strm_base;
/* SWREG129_RPS_BASE */
RK_U32 reg129_rps_base;
/* SWREG130_CABACTBL_BASE */
RK_U32 reg130_cabactbl_base;
/* SWREG131_GBL_BASE */
RK_U32 reg131_gbl_base;
/* SWREG132_SCANLIST_ADDR */
RK_U32 reg132_scanlist_addr;
/* SWREG133_SCALE_DOWN_TILE_BASE */
RK_U32 reg133_scale_down_tile_base;
/* SWREG134_SCALE_DOWN_TILE_BASE */
RK_U32 reg134_fgs_base;
} Vdpu383RegComPktAddr;
typedef struct Vdpu383RegRcbParas_t {
/* SWREG140_RCB_STRMD_ROW_OFFSET */
RK_U32 reg140_rcb_strmd_row_offset;
/* SWREG141_RCB_STRMD_ROW_LEN */
RK_U32 reg141_rcb_strmd_row_len;
/* SWREG142_RCB_STRMD_TILE_ROW_OFFSET */
RK_U32 reg142_rcb_strmd_tile_row_offset;
/* SWREG143_RCB_STRMD_TILE_ROW_LEN */
RK_U32 reg143_rcb_strmd_tile_row_len;
/* SWREG144_RCB_INTER_ROW_OFFSET */
RK_U32 reg144_rcb_inter_row_offset;
/* SWREG145_RCB_INTER_ROW_LEN */
RK_U32 reg145_rcb_inter_row_len;
/* SWREG146_RCB_INTER_TILE_ROW_OFFSET */
RK_U32 reg146_rcb_inter_tile_row_offset;
/* SWREG147_RCB_INTER_TILE_ROW_LEN */
RK_U32 reg147_rcb_inter_tile_row_len;
/* SWREG148_RCB_INTRA_ROW_OFFSET */
RK_U32 reg148_rcb_intra_row_offset;
/* SWREG149_RCB_INTRA_ROW_LEN */
RK_U32 reg149_rcb_intra_row_len;
/* SWREG150_RCB_INTRA_TILE_ROW_OFFSET */
RK_U32 reg150_rcb_intra_tile_row_offset;
/* SWREG151_RCB_INTRA_TILE_ROW_LEN */
RK_U32 reg151_rcb_intra_tile_row_len;
/* SWREG152_RCB_FILTERD_ROW_OFFSET */
RK_U32 reg152_rcb_filterd_row_offset;
/* SWREG153_RCB_FILTERD_ROW_LEN */
RK_U32 reg153_rcb_filterd_row_len;
/* SWREG154_RCB_FILTERD_PROTECT_ROW_OFFSET */
RK_U32 reg154_rcb_filterd_protect_row_offset;
/* SWREG155_RCB_FILTERD_PROTECT_ROW_LEN */
RK_U32 reg155_rcb_filterd_protect_row_len;
/* SWREG156_RCB_FILTERD_TILE_ROW_OFFSET */
RK_U32 reg156_rcb_filterd_tile_row_offset;
/* SWREG157_RCB_FILTERD_TILE_ROW_LEN */
RK_U32 reg157_rcb_filterd_tile_row_len;
/* SWREG158_RCB_FILTERD_TILE_COL_OFFSET */
RK_U32 reg158_rcb_filterd_tile_col_offset;
/* SWREG159_RCB_FILTERD_TILE_COL_LEN */
RK_U32 reg159_rcb_filterd_tile_col_len;
/* SWREG160_RCB_FILTERD_AV1_UPSCALE_TILE_COL_OFFSET */
RK_U32 reg160_rcb_filterd_av1_upscale_tile_col_offset;
/* SWREG161_RCB_FILTERD_AV1_UPSCALE_TILE_COL_LEN */
RK_U32 reg161_rcb_filterd_av1_upscale_tile_col_len;
} Vdpu383RegRcbParas;
typedef struct Vdpu383RegAv1dParas_t {
struct SWREG64_H26X_PARA {
RK_U32 reserve0 : 4;
RK_U32 unused_bits : 28;
} reg64;
/* SWREG65_STREAM_PARAM_SET */
RK_U32 reg65_strm_start_bit;
/* SWREG66_STREAM_LEN */
RK_U32 reg66_stream_len;
/* SWREG67_GLOBAL_LEN */
RK_U32 reg67_global_len;
/* SWREG68_HOR_STRIDE */
RK_U32 reg68_hor_virstride;
/* SWREG69_RASTER_UV_HOR_STRIDE */
RK_U32 reg69_raster_uv_hor_virstride;
/* SWREG70_Y_STRIDE */
RK_U32 reg70_y_virstride;
/* SWREG71_SCL_Y_HOR_VIRSTRIDE */
RK_U32 reg71_scl_ref_hor_virstride;
/* SWREG72_SCL_UV_HOR_VIRSTRIDE */
RK_U32 reg72_scl_ref_raster_uv_hor_virstride;
/* SWREG73_SCL_Y_VIRSTRIDE */
RK_U32 reg73_scl_ref_virstride;
/* SWREG74_FGS_Y_HOR_VIRSTRIDE */
RK_U32 reg74_fgs_ref_hor_virstride;
RK_U32 reserve_reg75_79[5];
/* SWREG80_ERROR_REF_Y_HOR_VIRSTRIDE */
RK_U32 reg80_error_ref_hor_virstride;
/* SWREG81_ERROR_REF_UV_HOR_VIRSTRIDE */
RK_U32 reg81_error_ref_raster_uv_hor_virstride;
/* SWREG82_ERROR_REF_Y_VIRSTRIDE */
RK_U32 reg82_error_ref_virstride;
/* SWREG83_REF0_Y_HOR_VIRSTRIDE */
RK_U32 reg83_ref0_hor_virstride;
/* SWREG84_REF0_UV_HOR_VIRSTRIDE */
RK_U32 reg84_ref0_raster_uv_hor_virstride;
/* SWREG85_REF0_Y_VIRSTRIDE */
RK_U32 reg85_ref0_virstride;
/* SWREG86_REF1_Y_HOR_VIRSTRIDE */
RK_U32 reg86_ref1_hor_virstride;
/* SWREG87_REF1_UV_HOR_VIRSTRIDE */
RK_U32 reg87_ref1_raster_uv_hor_virstride;
/* SWREG88_REF1_Y_VIRSTRIDE */
RK_U32 reg88_ref1_virstride;
/* SWREG89_REF2_Y_HOR_VIRSTRIDE */
RK_U32 reg89_ref2_hor_virstride;
/* SWREG90_REF2_UV_HOR_VIRSTRIDE */
RK_U32 reg90_ref2_raster_uv_hor_virstride;
/* SWREG91_REF2_Y_VIRSTRIDE */
RK_U32 reg91_ref2_virstride;
/* SWREG92_REF3_Y_HOR_VIRSTRIDE */
RK_U32 reg92_ref3_hor_virstride;
/* SWREG93_REF3_UV_HOR_VIRSTRIDE */
RK_U32 reg93_ref3_raster_uv_hor_virstride;
/* SWREG94_REF3_Y_VIRSTRIDE */
RK_U32 reg94_ref3_virstride;
/* SWREG95_REF4_Y_HOR_VIRSTRIDE */
RK_U32 reg95_ref4_hor_virstride;
/* SWREG96_REF4_UV_HOR_VIRSTRIDE */
RK_U32 reg96_ref4_raster_uv_hor_virstride;
/* SWREG97_REF4_Y_VIRSTRIDE */
RK_U32 reg97_ref4_virstride;
/* SWREG98_REF5_Y_HOR_VIRSTRIDE */
RK_U32 reg98_ref5_hor_virstride;
/* SWREG99_REF5_UV_HOR_VIRSTRIDE */
RK_U32 reg99_ref5_raster_uv_hor_virstride;
/* SWREG100_REF5_Y_VIRSTRIDE */
RK_U32 reg100_ref5_virstride;
/* SWREG101_REF6_Y_HOR_VIRSTRIDE */
RK_U32 reg101_ref6_hor_virstride;
/* SWREG102_REF6_UV_HOR_VIRSTRIDE */
RK_U32 reg102_ref6_raster_uv_hor_virstride;
/* SWREG103_REF6_Y_VIRSTRIDE */
RK_U32 reg103_ref6_virstride;
/* SWREG104_REF7_Y_HOR_VIRSTRIDE */
RK_U32 reg104_ref7_hor_virstride;
/* SWREG105_REF7_UV_HOR_VIRSTRIDE */
RK_U32 reg105_ref7_raster_uv_hor_virstride;
/* SWREG106_REF7_Y_VIRSTRIDE */
RK_U32 reg106_ref7_virstride;
} Vdpu383RegAv1dParas;
typedef struct Vdpu383RegAv1dAddr_t {
/* SWREG168_DECOUT_BASE */
RK_U32 reg168_decout_base;
/* SWREG169_ERROR_REF_BASE */
RK_U32 reg169_error_ref_base;
/* SWREG170_REF0_BASE */
// RK_U32 reg170_refer0_base;
RK_U32 reg170_av1_last_base;
/* SWREG171_REF1_BASE */
// RK_U32 reg171_refer1_base;
RK_U32 reg171_av1golden_base;
/* SWREG172_REF2_BASE */
// RK_U32 reg172_refer2_base;
RK_U32 reg172_av1alfter_base;
/* SWREG173_REF3_BASE */
RK_U32 reg173_refer3_base;
/* SWREG174_REF4_BASE */
RK_U32 reg174_refer4_base;
/* SWREG175_REF5_BASE */
RK_U32 reg175_refer5_base;
/* SWREG176_REF6_BASE */
RK_U32 reg176_refer6_base;
/* SWREG177_REF7_BASE */
RK_U32 reg177_refer7_base;
/* SWREG178_H26X_REF8_BASE */
// RK_U32 reg178_refer8_base;
RK_U32 reg178_av1_coef_rd_base;
/* SWREG179_H26X_REF9_BASE */
// RK_U32 reg179_refer9_base;
RK_U32 reg179_av1_coef_wr_base;
/* SWREG180_H26X_REF10_BASE */
// RK_U32 reg180_refer10_base;
/* SWREG181_H26X_REF11_BASE */
// RK_U32 reg181_refer11_base;
// RK_U32 reg181_av1segidlast_base;
/* SWREG182_H26X_REF12_BASE */
// RK_U32 reg182_refer12_base;
// RK_U32 reg182_av1segidcur_base;
/* SWREG183_H26X_REF13_BASE */
// RK_U32 reg183_refer13_base;
// RK_U32 reg183_kf_prob_base;
RK_U32 reserve_reg180_183[4];
/* SWREG184_H26X_REF14_BASE */
// RK_U32 reg184_refer14_base;
RK_U32 reg184_av1_noncoef_rd_base;
/* SWREG185_H26X_REF15_BASE */
// RK_U32 reg185_refer15_base;
RK_U32 reg185_av1_noncoef_wr_base;
RK_U32 reserve_reg186_191[6];
/* SWREG192_PAYLOAD_ST_CUR_BASE */
RK_U32 reg192_payload_st_cur_base;
/* SWREG193_FBC_PAYLOAD_OFFSET */
RK_U32 reg193_fbc_payload_offset;
/* SWREG194_PAYLOAD_ST_ERROR_REF_BASE */
RK_U32 reg194_payload_st_error_ref_base;
/* SWREG195_PAYLOAD_ST_REF0_BASE */
RK_U32 reg195_payload_st_ref0_base;
/* SWREG196_PAYLOAD_ST_REF1_BASE */
RK_U32 reg196_payload_st_ref1_base;
/* SWREG197_PAYLOAD_ST_REF2_BASE */
RK_U32 reg197_payload_st_ref2_base;
/* SWREG198_PAYLOAD_ST_REF3_BASE */
RK_U32 reg198_payload_st_ref3_base;
/* SWREG199_PAYLOAD_ST_REF4_BASE */
RK_U32 reg199_payload_st_ref4_base;
/* SWREG200_PAYLOAD_ST_REF5_BASE */
RK_U32 reg200_payload_st_ref5_base;
/* SWREG201_PAYLOAD_ST_REF6_BASE */
RK_U32 reg201_payload_st_ref6_base;
/* SWREG202_PAYLOAD_ST_REF7_BASE */
RK_U32 reg202_payload_st_ref7_base;
/* SWREG203_PAYLOAD_ST_REF8_BASE */
RK_U32 reg203_payload_st_ref8_base;
/* SWREG204_PAYLOAD_ST_REF9_BASE */
RK_U32 reg204_payload_st_ref9_base;
/* SWREG205_PAYLOAD_ST_REF10_BASE */
RK_U32 reg205_payload_st_ref10_base;
/* SWREG206_PAYLOAD_ST_REF11_BASE */
RK_U32 reg206_payload_st_ref11_base;
/* SWREG207_PAYLOAD_ST_REF12_BASE */
RK_U32 reg207_payload_st_ref12_base;
/* SWREG208_PAYLOAD_ST_REF13_BASE */
RK_U32 reg208_payload_st_ref13_base;
/* SWREG209_PAYLOAD_ST_REF14_BASE */
RK_U32 reg209_payload_st_ref14_base;
/* SWREG210_PAYLOAD_ST_REF15_BASE */
RK_U32 reg210_payload_st_ref15_base;
RK_U32 reserve_reg211_215[5];
/* SWREG216_COLMV_CUR_BASE */
RK_U32 reg216_colmv_cur_base;
/* SWREG217_232_COLMV_REF0_BASE */
RK_U32 reg217_232_colmv_ref_base[16];
} Vdpu383RegAv1dAddr;
typedef struct Vdpu383Av1dRegSet_t {
Vdpu383RegVersion reg_version;
Vdpu383CtrlReg ctrl_regs; /* 8-30 */
Vdpu383RegComPktAddr com_pkt_addr; /* 128-133 */
Vdpu383RegRcbParas rcb_paras; /* 140-161 */
Vdpu383RegAv1dParas av1d_paras; /* 64-106 */
Vdpu383RegAv1dAddr av1d_addrs; /* 168-185(ref) */
/* 192-210(fbc) */
/* 216-232(col mv) */
} Vdpu383Av1dRegSet;
#endif /* __HAL_AV1D_VDPU383_REG_H__ */