From 381a9d3e3bfaf668ee5b5ea829fbd53f4cd46ff6 Mon Sep 17 00:00:00 2001 From: "sliver.chen" Date: Mon, 22 Jan 2018 19:42:14 +0800 Subject: [PATCH] [jpege]: add vpu1 and vpu2 jpeg encode rgb fmt support Modify some register params to support 32-bit rgb fmt,including vepu1 and vepu2. Change-Id: I265ad77eb02f95cc51de3bc51a340b56cdebb702 Signed-off-by: sliver.chen --- mpp/hal/vpu/jpege/hal_jpege_vepu1.c | 45 ++++++++++++++++++++++++----- mpp/hal/vpu/jpege/hal_jpege_vepu2.c | 42 ++++++++++++++++++++++----- 2 files changed, 73 insertions(+), 14 deletions(-) diff --git a/mpp/hal/vpu/jpege/hal_jpege_vepu1.c b/mpp/hal/vpu/jpege/hal_jpege_vepu1.c index 4553699c..10e92cc9 100644 --- a/mpp/hal/vpu/jpege/hal_jpege_vepu1.c +++ b/mpp/hal/vpu/jpege/hal_jpege_vepu1.c @@ -167,6 +167,9 @@ MPP_RET hal_jpege_vepu1_gen_regs(void *hal, HalTaskInfo *task) RK_S32 bitpos; RK_S32 bytepos; RK_U32 deflt_cfg; + RK_U32 r_mask = 0; + RK_U32 g_mask = 0; + RK_U32 b_mask = 0; syntax->width = width; syntax->height = height; @@ -200,34 +203,61 @@ MPP_RET hal_jpege_vepu1_gen_regs(void *hal, HalTaskInfo *task) ((16 & (63)) << 8) | ((0 & (1)) << 6) | ((0 & (1)) << 5) | - ((0 & (1)) << 4) | + ((1 & (1)) << 4) | ((1 & (1)) << 3) | ((1 & (1)) << 1); switch (fmt) { case MPP_FMT_YUV420P : { val32 = 0; + r_mask = 0; + g_mask = 0; + b_mask = 0; } break; case MPP_FMT_YUV420SP : { val32 = 1; + r_mask = 0; + g_mask = 0; + b_mask = 0; } break; case MPP_FMT_YUV422_YUYV : { val32 = 2; + r_mask = 0; + g_mask = 0; + b_mask = 0; } break; case MPP_FMT_YUV422_UYVY : { val32 = 3; + r_mask = 0; + g_mask = 0; + b_mask = 0; } break; case MPP_FMT_RGB565 : { val32 = 4; + r_mask = 4; + g_mask = 10; + b_mask = 15; } break; case MPP_FMT_RGB444 : { val32 = 5; + r_mask = 3; + g_mask = 7; + b_mask = 11; } break; case MPP_FMT_RGB888 : { - val32 = 6; + val32 = 7; + r_mask = 7; + g_mask = 15; + b_mask = 23; + } break; + case MPP_FMT_BGR888 : { + val32 = 7; + r_mask = 23; + g_mask = 15; + b_mask = 7; } break; case MPP_FMT_RGB101010 : { - val32 = 7; + val32 = 8; } break; default : { mpp_err_f("invalid input format %d\n", fmt); @@ -352,9 +382,9 @@ MPP_RET hal_jpege_vepu1_gen_regs(void *hal, HalTaskInfo *task) regs[53] = coeffA | (coeffB << 16); regs[54] = coeffC | (coeffE << 16); - regs[55] = (0 << 26) | - (0 << 21) | - (0 << 16) | coeffF; + regs[55] = ((r_mask & 0x1f) << 26) | + ((g_mask & 0x1f) << 21) | + ((b_mask & 0x1f) << 16) | coeffF; } regs[14] |= 0x001; @@ -487,7 +517,8 @@ MPP_RET hal_jpege_vepu1_control(void *hal, RK_S32 cmd, void *param) if (cfg->format != MPP_FMT_YUV420SP && cfg->format != MPP_FMT_YUV420P && - cfg->format != MPP_FMT_RGB888) { + cfg->format != MPP_FMT_RGB888 && + cfg->format != MPP_FMT_BGR888) { mpp_err("jpege: invalid format %d is not supportted\n", cfg->format); ret = MPP_NOK; } diff --git a/mpp/hal/vpu/jpege/hal_jpege_vepu2.c b/mpp/hal/vpu/jpege/hal_jpege_vepu2.c index 17f43b33..299fe6e2 100644 --- a/mpp/hal/vpu/jpege/hal_jpege_vepu2.c +++ b/mpp/hal/vpu/jpege/hal_jpege_vepu2.c @@ -165,6 +165,9 @@ MPP_RET hal_jpege_vepu2_gen_regs(void *hal, HalTaskInfo *task) RK_U32 val32; RK_S32 bitpos; RK_S32 bytepos; + RK_U32 r_mask = 0; + RK_U32 g_mask = 0; + RK_U32 b_mask = 0; syntax->width = width; syntax->height = height; @@ -233,27 +236,49 @@ MPP_RET hal_jpege_vepu2_gen_regs(void *hal, HalTaskInfo *task) switch (fmt) { case MPP_FMT_YUV420P : { val32 = 0; + r_mask = g_mask = b_mask = 0; } break; case MPP_FMT_YUV420SP : { val32 = 1; + r_mask = g_mask = b_mask = 0; } break; case MPP_FMT_YUV422_YUYV : { val32 = 2; + r_mask = g_mask = b_mask = 0; } break; case MPP_FMT_YUV422_UYVY : { val32 = 3; + r_mask = g_mask = b_mask = 0; } break; case MPP_FMT_RGB565 : { val32 = 4; + r_mask = 15; + g_mask = 10; + b_mask = 4; } break; case MPP_FMT_RGB444 : { - val32 = 5; + val32 = 6; + r_mask = 11; + g_mask = 7; + b_mask = 3; } break; case MPP_FMT_RGB888 : { - val32 = 6; + val32 = 7; + r_mask = 7; + g_mask = 15; + b_mask = 23; + } break; + case MPP_FMT_BGR888 : { + val32 = 7; + r_mask = 23; + g_mask = 15; + b_mask = 7; } break; case MPP_FMT_RGB101010 : { - val32 = 7; + val32 = 8; + r_mask = 29; + g_mask = 19; + b_mask = 9; } break; default : { mpp_err_f("invalid input format %d\n", fmt); @@ -321,7 +346,9 @@ MPP_RET hal_jpege_vepu2_gen_regs(void *hal, HalTaskInfo *task) } /* TODO: 98 RGB bit mask */ - regs[98] = 0; + regs[98] = (r_mask & 0x1f) << 16 | + (g_mask & 0x1f) << 8 | + (b_mask & 0x1f); regs[103] = (hor_stride >> 4) << 8 | (ver_stride >> 4) << 20 | @@ -331,10 +358,10 @@ MPP_RET hal_jpege_vepu2_gen_regs(void *hal, HalTaskInfo *task) /* input byte swap configure */ regs[105] = 7 << 26; - if (val32 < 4) { + if (fmt < MPP_FMT_RGB565) { // YUV format regs[105] |= (7 << 29); - } else if (val32 < 7) { + } else if (fmt < MPP_FMT_RGB888) { // 16bit RGB regs[105] |= (2 << 29); } else { @@ -476,7 +503,8 @@ MPP_RET hal_jpege_vepu2_control(void *hal, RK_S32 cmd, void *param) if (cfg->format != MPP_FMT_YUV420SP && cfg->format != MPP_FMT_YUV420P && - cfg->format != MPP_FMT_RGB888) { + cfg->format != MPP_FMT_RGB888 && + cfg->format != MPP_FMT_BGR888) { mpp_err("jpege: invalid format %d is not supportted\n", cfg->format); ret = MPP_NOK; }