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git-svn-id: https://10.10.10.66:8443/svn/MediaProcessPlatform/trunk/mpp@1020 6e48237b-75ef-9749-8fc9-41990f28c85a
This commit is contained in:
GaoZhili
2016-07-14 09:34:04 +00:00
parent c7c9cc380b
commit 3249378118
23 changed files with 971 additions and 1084 deletions
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6
mpp/base/mpp_buffer_impl.cpp
View File

@@ -79,13 +79,11 @@ private:
struct list_head mListOrphan;
public:
static MppBufferService *get_instance()
{
static MppBufferService *get_instance() {
static MppBufferService instance;
return &instance;
}
static Mutex *get_lock()
{
static Mutex *get_lock() {
static Mutex lock;
return &lock;
}

9
mpp/codec/dec/h264/h264d_api.c
View File

@@ -732,8 +732,7 @@ __RETURN:
FunctionOut(p_Dec->logctx.parr[RUN_PARSE]);
return ret = MPP_OK;
__FAILED:
{
__FAILED: {
H264_StorePic_t *dec_pic = p_Dec->p_Vid->dec_pic;
if (dec_pic) {
H264D_WARNNING("[h264d_parse] h264d_parse failed.\n");
@@ -795,8 +794,7 @@ MPP_RET h264d_callback(void *decoder, void *errinfo)
if (ctx->hard_err || task_dec->flags.had_error) {
if (task_dec->flags.used_for_ref) {
mpp_frame_set_errinfo(mframe, VPU_FRAME_ERR_UNKNOW);
}
else {
} else {
mpp_frame_set_discard(mframe, VPU_FRAME_ERR_UNKNOW);
}
}
@@ -806,8 +804,7 @@ MPP_RET h264d_callback(void *decoder, void *errinfo)
if (ctx->device_id == HAL_RKVDEC) {
H264D_DBG(H264D_DBG_CALLBACK, "[CALLBACK] sw[01]=%08x, sw[45]=%08x, sw[76]=%08x\n", p_regs[1], p_regs[45], p_regs[76]);
}
else if (ctx->device_id == HAL_VDPU) {
} else if (ctx->device_id == HAL_VDPU) {
}
}

3
mpp/hal/inc/hal_task.h
View File

@@ -36,8 +36,7 @@ typedef struct IOInterruptCB {
void *opaque;
} IOInterruptCB;
typedef struct IOCallbackCtx_t
{
typedef struct IOCallbackCtx_t {
RK_U32 device_id;
void *task;
RK_U32 *regs;

3
mpp/hal/rkdec/h264d/hal_h264d_rkv_pkt.c
View File

@@ -45,7 +45,8 @@
#define FPGA_TEST 0
const enum {
const enum
{
H264ScalingList4x4Length = 16,
H264ScalingList8x8Length = 64,
} ScalingListLength;

6
mpp/hal/rkdec/h264d/hal_h264d_rkv_reg.c
View File

@@ -465,8 +465,7 @@ __SKIP_HARD:
|| p_regs->swreg1_int.sw_dec_empty_sta
|| p_regs->swreg45_strmd_error_status.sw_strmd_error_status
|| p_regs->swreg45_strmd_error_status.sw_colmv_error_ref_picidx
|| p_regs->swreg76_h264_errorinfo_num.sw_strmd_detect_error_flag)
{
|| p_regs->swreg76_h264_errorinfo_num.sw_strmd_detect_error_flag) {
m_ctx.hard_err = 1;
}
m_ctx.task = (void *)&task->dec;
@@ -539,8 +538,7 @@ MPP_RET rkv_h264d_control(void *hal, RK_S32 cmd_type, void *param)
INP_CHECK(ret, NULL == p_hal);
FunctionIn(p_hal->logctx.parr[RUN_HAL]);
switch ((MpiCmd)cmd_type)
{
switch ((MpiCmd)cmd_type) {
case MPP_CODEC_SET_FRAME_INFO: {
VPU_GENERIC *p = (VPU_GENERIC *)param;
if (p->CodecType == MPP_FMT_YUV422SP) {

54
mpp/hal/rkdec/h264d/hal_h264d_vdpu_pkt.c
View File

@@ -208,8 +208,7 @@ static RK_U32 check_dpb_buffer_is_valid(H264dHalCtx_t *p_hal, RK_U32 dpb_idx)
}
static MPP_RET vdpu_set_refer_pic_idx(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 val)
{
switch (i)
{
switch (i) {
case 0:
p_regs->sw76.num_ref_idx0 = val;
break;
@@ -266,8 +265,7 @@ static MPP_RET vdpu_set_refer_pic_idx(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16
}
static MPP_RET vdpu_set_refer_pic_list_p(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 val)
{
switch (i)
{
switch (i) {
case 0:
p_regs->sw106.init_reflist_pf0 = val;
break;
@@ -324,8 +322,7 @@ static MPP_RET vdpu_set_refer_pic_list_p(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U
}
static MPP_RET vdpu_set_refer_pic_list_b0(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 val)
{
switch (i)
{
switch (i) {
case 0:
p_regs->sw100.init_reflist_df0 = val;
break;
@@ -382,8 +379,7 @@ static MPP_RET vdpu_set_refer_pic_list_b0(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_
}
static MPP_RET vdpu_set_refer_pic_list_b1(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 val)
{
switch (i)
{
switch (i) {
case 0:
p_regs->sw103.init_reflist_db0 = val;
break;
@@ -441,8 +437,7 @@ static MPP_RET vdpu_set_refer_pic_list_b1(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_
static MPP_RET vdpu_set_refer_pic_base_addr(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U32 val)
{
switch (i)
{
switch (i) {
case 0:
p_regs->sw84.ref0_st_addr = val;
break;
@@ -550,8 +545,7 @@ MPP_RET vdpu_set_vlc_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
if (pp->RefFrameList[i / 2].bPicEntry == 0xff) { //!< invalid
longTermflags <<= 1;
validFlags <<= 1;
}
else {
} else {
longTermTmp = pp->RefFrameList[i / 2].AssociatedFlag; //!< get long term flag
longTermflags = (longTermflags << 1) | longTermTmp;
@@ -562,16 +556,14 @@ MPP_RET vdpu_set_vlc_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
}
p_regs->sw107.refpic_term_flag = longTermflags;
p_regs->sw108.refpic_valid_flag = validFlags;
}
else {
} else {
RK_U32 validTmp = 0, validFlags = 0;
RK_U32 longTermTmp = 0, longTermflags = 0;
for (i = 0; i < 16; i++) {
if (pp->RefFrameList[i].bPicEntry == 0xff) { //!< invalid
longTermflags <<= 1;
validFlags <<= 1;
}
else {
} else {
longTermTmp = pp->RefFrameList[i].AssociatedFlag;
longTermflags = (longTermflags << 1) | longTermTmp;
validTmp = check_dpb_buffer_is_valid(p_hal, pp->RefFrameList[i].Index7Bits);
@@ -587,8 +579,7 @@ MPP_RET vdpu_set_vlc_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
if (pp->RefFrameList[i].bPicEntry != 0xff) { //!< valid
if (pp->RefFrameList[i].AssociatedFlag) { //!< longterm flag
vdpu_set_refer_pic_idx(p_regs, i, pp->LongTermPicNumList[i]); //!< pic_num
}
else {
} else {
vdpu_set_refer_pic_idx(p_regs, i, pp->FrameNumList[i]); //< frame_num
}
}
@@ -602,8 +593,7 @@ MPP_RET vdpu_set_vlc_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
for (i = 0; i < 32; i++) {
if (pp->RefFrameList[i / 2].bPicEntry != 0xff) {
*pocBase++ = pp->FieldOrderCntList[i / 2][i & 0x1];
}
else {
} else {
*pocBase++ = 0;
}
}
@@ -611,8 +601,7 @@ MPP_RET vdpu_set_vlc_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
if (pp->field_pic_flag || !pp->MbaffFrameFlag) {
*pocBase++ = pp->CurrFieldOrderCnt[0];
*pocBase++ = pp->CurrFieldOrderCnt[1];
}
else {
} else {
*pocBase++ = pp->CurrFieldOrderCnt[0];
*pocBase++ = pp->CurrFieldOrderCnt[1];
}
@@ -656,16 +645,13 @@ MPP_RET vdpu_set_ref_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
nn = p_hal->pp->CurrPic.AssociatedFlag ? (2 * i + 1) : (2 * i);
if (p_long->RefPicList[j][nn].bPicEntry == 0xff) {
val = g_ValueList[i];
}
else {
} else {
val = p_long->RefPicList[j][nn].Index7Bits;
}
}
else { //!< frame
} else { //!< frame
if (p_long->RefPicList[j][i].bPicEntry == 0xff) {
val = g_ValueList[i];
}
else {
} else {
val = p_long->RefPicList[j][i].Index7Bits;
}
}
@@ -715,8 +701,7 @@ MPP_RET vdpu_set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
if (pp->RefFrameList[i].bPicEntry != 0xff) {
mpp_buf_slot_get_prop(p_hal->frame_slots, pp->RefFrameList[i].Index7Bits, SLOT_BUFFER, &frame_buf); //!< reference phy addr
j = i;
}
else {
} else {
mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &frame_buf); //!< current out phy addr
}
@@ -730,11 +715,9 @@ MPP_RET vdpu_set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
used_flag = ((pp->UsedForReferenceFlags >> (2 * i)) & 0x3);
if (used_flag & 0x3) {
ref_poc = MPP_MIN(pp->FieldOrderCntList[i][0], pp->FieldOrderCntList[i][1]);
}
else if (used_flag & 0x2) {
} else if (used_flag & 0x2) {
ref_poc = pp->FieldOrderCntList[i][1];
}
else if (used_flag & 0x1) {
} else if (used_flag & 0x1) {
ref_poc = pp->FieldOrderCntList[i][0];
}
top_closer = (cur_poc < ref_poc) ? 0x1 : 0;
@@ -768,8 +751,7 @@ MPP_RET vdpu_set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
if (pp->field_pic_flag && pp->CurrPic.AssociatedFlag) {
if (VPUClientGetIOMMUStatus() > 0) {
outPhyAddr |= ((pp->wFrameWidthInMbsMinus1 + 1) * 16) << 10;
}
else {
} else {
outPhyAddr += (pp->wFrameWidthInMbsMinus1 + 1) * 16;
}
}

234
mpp/hal/rkdec/h264d/hal_h264d_vdpu_pkt.h
View File

@@ -25,11 +25,9 @@
#include "hal_h264d_fifo.h"
#include "hal_h264d_global.h"
typedef struct
{
typedef struct {
RK_U32 sw00_49[50];
struct
{
struct {
RK_U32 dec_tiled_msb : 1;
RK_U32 adtion_latency : 6;
RK_U32 dec_fixed_quant : 1;
@@ -42,27 +40,23 @@ typedef struct
RK_U32 refbuf_pid : 5;
RK_U32 reverse0 : 2;
} sw50;
struct
{
struct {
RK_U32 stream_len : 24;
RK_U32 stream_len_ext : 1;
RK_U32 qp_init_val : 6;
RK_U32 reverse0 : 1;
} sw51;
struct
{
struct {
RK_U32 ydim_mbst : 8;
RK_U32 xdim_mbst : 9;
RK_U32 adv_pref_thrd : 14;
RK_U32 reverse0 : 1;
} sw52;
struct
{
struct {
RK_U32 dec_fmt_sel : 4;
RK_U32 reverse0 : 28;
} sw53;
struct
{
struct {
RK_U32 dec_in_endian : 1;
RK_U32 dec_out_endian : 1;
RK_U32 dec_in_wordsp : 1;
@@ -71,8 +65,7 @@ typedef struct
RK_U32 dec_strendian_e : 1;
RK_U32 reverse0 : 26;
} sw54;
struct
{
struct {
RK_U32 dec_irq : 1;
RK_U32 dec_irq_dis : 1;
RK_U32 reverse0 : 2;
@@ -88,8 +81,7 @@ typedef struct
RK_U32 timeout_det_sts : 1;
RK_U32 reverse3 : 18;
} sw55;
struct
{
struct {
RK_U32 dec_axi_id_rd : 8;
RK_U32 dec_axi_id_wr : 8;
RK_U32 dec_max_burlen : 5;
@@ -98,8 +90,7 @@ typedef struct
RK_U32 axi_sel : 1;
RK_U32 reverse0 : 8;
} sw56;
struct
{
struct {
RK_U32 dec_st_work : 1;
RK_U32 refpic_buf2_en : 1;
RK_U32 dec_wr_extmen_dis : 1;
@@ -132,40 +123,32 @@ typedef struct
RK_U32 reverse2 : 1;
RK_U32 dec_timeout_mode : 1;
} sw57;
struct
{
struct {
RK_U32 soft_rst : 1;
RK_U32 reverse0 : 31;
} sw58;
struct
{
struct {
RK_U32 reverse0 : 2;
RK_U32 pflt_set0_tap2 : 10;
RK_U32 pflt_set0_tap1 : 10;
RK_U32 pflt_set0_tap0 : 10;
} sw59;
struct
{
struct {
RK_U32 addit_ch_st_adr : 32;
} sw60;
struct
{
struct {
RK_U32 qtable_st_adr : 32;
} sw61;
struct
{
struct {
RK_U32 dmmv_st_adr : 32;
} sw62;
struct
{
struct {
RK_U32 dec_out_st_adr : 32;
} sw63;
struct
{
struct {
RK_U32 rlc_vlc_st_adr : 32;
} sw64;
struct
{
struct {
RK_U32 refbuf_y_offset : 9;
RK_U32 reserve0 : 3;
RK_U32 refbuf_fildpar_mode_e : 1;
@@ -176,26 +159,22 @@ typedef struct
} sw65;
RK_U32 sw66;
RK_U32 sw67;
struct
{
struct {
RK_U32 refbuf_sum_bot : 16;
RK_U32 refbuf_sum_top : 16;
} sw68;
struct
{
struct {
RK_U32 luma_sum_intra : 16;
RK_U32 refbuf_sum_hit : 16;
} sw69;
struct
{
struct {
RK_U32 ycomp_mv_sum : 22;
RK_U32 reserve0 : 10;
} sw70;
RK_U32 sw71;
RK_U32 sw72;
RK_U32 sw73;
struct
{
struct {
RK_U32 init_reflist_pf4 : 5;
RK_U32 init_reflist_pf5 : 5;
RK_U32 init_reflist_pf6 : 5;
@@ -204,8 +183,7 @@ typedef struct
RK_U32 init_reflist_pf9 : 5;
RK_U32 reverse0 : 2;
} sw74;
struct
{
struct {
RK_U32 init_reflist_pf10 : 5;
RK_U32 init_reflist_pf11 : 5;
RK_U32 init_reflist_pf12 : 5;
@@ -214,208 +192,167 @@ typedef struct
RK_U32 init_reflist_pf15 : 5;
RK_U32 reverse0 : 2;
} sw75;
struct
{
struct {
RK_U32 num_ref_idx0 : 16;
RK_U32 num_ref_idx1 : 16;
} sw76;
struct
{
struct {
RK_U32 num_ref_idx2 : 16;
RK_U32 num_ref_idx3 : 16;
} sw77;
struct
{
struct {
RK_U32 num_ref_idx4 : 16;
RK_U32 num_ref_idx5 : 16;
} sw78;
struct
{
struct {
RK_U32 num_ref_idx6 : 16;
RK_U32 num_ref_idx7 : 16;
} sw79;
struct
{
struct {
RK_U32 num_ref_idx8 : 16;
RK_U32 num_ref_idx9 : 16;
} sw80;
struct
{
struct {
RK_U32 num_ref_idx10 : 16;
RK_U32 num_ref_idx11 : 16;
} sw81;
struct
{
struct {
RK_U32 num_ref_idx12 : 16;
RK_U32 num_ref_idx13 : 16;
} sw82;
struct
{
struct {
RK_U32 num_ref_idx14 : 16;
RK_U32 num_ref_idx15 : 16;
} sw83;
union
{
union {
RK_U32 ref0_st_addr;
struct
{
struct {
RK_U32 ref0_closer_sel : 1;
RK_U32 ref0_field_en : 1;
RK_U32 reverse0 : 30;
};
} sw84;
union
{
union {
RK_U32 ref1_st_addr;
struct
{
struct {
RK_U32 ref1_closer_sel : 1;
RK_U32 ref1_field_en : 1;
RK_U32 reverse0 : 30;
};
} sw85;
union
{
union {
RK_U32 ref2_st_addr;
struct
{
struct {
RK_U32 ref2_closer_sel : 1;
RK_U32 ref2_field_en : 1;
RK_U32 reverse0 : 30;
};
} sw86;
union
{
union {
RK_U32 ref3_st_addr;
struct
{
struct {
RK_U32 ref3_closer_sel : 1;
RK_U32 ref3_field_en : 1;
RK_U32 reverse0 : 30;
};
} sw87;
union
{
union {
RK_U32 ref4_st_addr;
struct
{
struct {
RK_U32 ref4_closer_sel : 1;
RK_U32 ref4_field_en : 1;
RK_U32 reverse0 : 30;
};
} sw88;
union
{
union {
RK_U32 ref5_st_addr;
struct
{
struct {
RK_U32 ref5_closer_sel : 1;
RK_U32 ref5_field_en : 1;
RK_U32 reverse0 : 30;
};
} sw89;
union
{
union {
RK_U32 ref6_st_addr;
struct
{
struct {
RK_U32 ref6_closer_sel : 1;
RK_U32 ref6_field_en : 1;
RK_U32 reverse0 : 30;
};
} sw90;
union
{
union {
RK_U32 ref7_st_addr;
struct
{
struct {
RK_U32 ref7_closer_sel : 1;
RK_U32 ref7_field_en : 1;
RK_U32 reverse0 : 30;
};
} sw91;
union
{
union {
RK_U32 ref8_st_addr;
struct
{
struct {
RK_U32 ref8_closer_sel : 1;
RK_U32 ref8_field_en : 1;
RK_U32 reverse0 : 30;
};
} sw92;
union
{
union {
RK_U32 ref9_st_addr;
struct
{
struct {
RK_U32 ref9_closer_sel : 1;
RK_U32 ref9_field_en : 1;
RK_U32 reverse0 : 30;
};
} sw93;
union
{
union {
RK_U32 ref10_st_addr;
struct
{
struct {
RK_U32 ref10_closer_sel : 1;
RK_U32 ref10_field_en : 1;
RK_U32 reverse0 : 30;
};
} sw94;
union
{
union {
RK_U32 ref11_st_addr;
struct
{
struct {
RK_U32 ref11_closer_sel : 1;
RK_U32 ref11_field_en : 1;
RK_U32 reverse0 : 30;
};
} sw95;
union
{
union {
RK_U32 ref12_st_addr;
struct
{
struct {
RK_U32 ref12_closer_sel : 1;
RK_U32 ref12_field_en : 1;
RK_U32 reverse0 : 30;
};
} sw96;
union
{
union {
RK_U32 ref13_st_addr;
struct
{
struct {
RK_U32 ref13_closer_sel : 1;
RK_U32 ref13_field_en : 1;
RK_U32 reverse0 : 30;
};
} sw97;
union
{
union {
RK_U32 ref14_st_addr;
struct
{
struct {
RK_U32 ref14_closer_sel : 1;
RK_U32 ref14_field_en : 1;
RK_U32 reverse0 : 30;
};
} sw98;
union
{
union {
RK_U32 ref15_st_addr;
struct
{
struct {
RK_U32 ref15_closer_sel : 1;
RK_U32 ref15_field_en : 1;
RK_U32 reverse0 : 30;
};
} sw99;
struct
{
struct {
RK_U32 init_reflist_df0 : 5;
RK_U32 init_reflist_df1 : 5;
RK_U32 init_reflist_df2 : 5;
@@ -424,8 +361,7 @@ typedef struct
RK_U32 init_reflist_df5 : 5;
RK_U32 reverse0 : 2;
} sw100;
struct
{
struct {
RK_U32 init_reflist_df6 : 5;
RK_U32 init_reflist_df7 : 5;
RK_U32 init_reflist_df8 : 5;
@@ -434,16 +370,14 @@ typedef struct
RK_U32 init_reflist_df11 : 5;
RK_U32 reverse0 : 2;
} sw101;
struct
{
struct {
RK_U32 init_reflist_df12 : 5;
RK_U32 init_reflist_df13 : 5;
RK_U32 init_reflist_df14 : 5;
RK_U32 init_reflist_df15 : 5;
RK_U32 reverse0 : 12;
} sw102;
struct
{
struct {
RK_U32 init_reflist_db0 : 5;
RK_U32 init_reflist_db1 : 5;
RK_U32 init_reflist_db2 : 5;
@@ -452,8 +386,7 @@ typedef struct
RK_U32 init_reflist_db5 : 5;
RK_U32 reverse0 : 2;
} sw103;
struct
{
struct {
RK_U32 init_reflist_db6 : 5;
RK_U32 init_reflist_db7 : 5;
RK_U32 init_reflist_db8 : 5;
@@ -462,74 +395,63 @@ typedef struct
RK_U32 init_reflist_db11 : 5;
RK_U32 reverse0 : 2;
} sw104;
struct
{
struct {
RK_U32 init_reflist_db12 : 5;
RK_U32 init_reflist_db13 : 5;
RK_U32 init_reflist_db14 : 5;
RK_U32 init_reflist_db15 : 5;
RK_U32 reverse0 : 12;
} sw105;
struct
{
struct {
RK_U32 init_reflist_pf0 : 5;
RK_U32 init_reflist_pf1 : 5;
RK_U32 init_reflist_pf2 : 5;
RK_U32 init_reflist_pf3 : 5;
RK_U32 reverse0 : 12;
} sw106;
struct
{
struct {
RK_U32 refpic_term_flag : 32;
} sw107;
struct
{
struct {
RK_U32 refpic_valid_flag : 32;
} sw108;
struct
{
struct {
RK_U32 strm_start_bit : 6;
RK_U32 reverse0 : 26;
} sw109;
struct
{
struct {
RK_U32 pic_mb_w : 9;
RK_U32 pic_mb_h : 8;
RK_U32 flt_offset_cb_qp : 5;
RK_U32 flt_offset_cr_qp : 5;
RK_U32 reverse0 : 5;
} sw110;
struct
{
struct {
RK_U32 max_refnum : 5;
RK_U32 reverse0 : 11;
RK_U32 wp_bslice_sel : 2;
RK_U32 reverse1 : 14;
} sw111;
struct
{
struct {
RK_U32 curfrm_num : 16;
RK_U32 cur_frm_len : 5;
RK_U32 reverse0 : 9;
RK_U32 rpcp_flag : 1;
RK_U32 dblk_ctrl_flag : 1;
} sw112;
struct
{
struct {
RK_U32 idr_pic_id : 16;
RK_U32 refpic_mk_len : 11;
RK_U32 reverse0 : 5;
} sw113;
struct
{
struct {
RK_U32 poc_field_len : 8;
RK_U32 reverse0 : 6;
RK_U32 max_refidx0 : 5;
RK_U32 max_refidx1 : 5;
RK_U32 pps_id : 5;
} sw114;
struct
{
struct {
RK_U32 fieldpic_flag_exist : 1;
RK_U32 scl_matrix_en : 1;
RK_U32 tranf_8x8_flag_en : 1;

9
mpp/hal/rkdec/h264d/hal_h264d_vdpu_reg.c
View File

@@ -108,8 +108,7 @@ static MPP_RET vdpu_get_info_input(H264dHalCtx_t *p_hal, H264dVdpuPriv_t *priv)
priv->new_dpb[i].BOT_POC = pp->FieldOrderCntList[i][1];
if (priv->new_dpb[i].is_long_term) {
priv->new_dpb[i].long_term_frame_idx = pp->FrameNumList[i];
}
else {
} else {
priv->new_dpb[i].frame_num = pp->FrameNumList[i];
}
priv->new_dpb[i].long_term_pic_num = pp->LongTermPicNumList[i];
@@ -213,8 +212,7 @@ static MPP_RET vdpu_refill_info_input(H264dHalCtx_t *p_hal, H264dVdpuPriv_t *pri
for (i = 0; i < MPP_ARRAY_ELEMS(p_long->RefPicList[j]); i++) {
if (p[i].valid) {
fill_picture_entry(&p_long->RefPicList[j][i], p[i].dpb_idx, p[i].bottom_flag);
}
else {
} else {
p_long->RefPicList[j][i].bPicEntry = 0xff;
}
}
@@ -428,8 +426,7 @@ MPP_RET vdpu_h264d_start(void *hal, HalTaskInfo *task)
if (VPUClientSendReg(p_hal->vpu_socket, (RK_U32 *)p_hal->regs, DEC_VDPU_REGISTERS)) {
ret = MPP_ERR_VPUHW;
mpp_err_f("H264 VDPU FlushRegs fail, pid=%d, hal_frame_no=%d. \n", getpid(), p_hal->iDecodedNum);
}
else {
} else {
H264D_LOG("H264 VDPU FlushRegs success, pid=%d, hal_frame_no=%d. \n", getpid(), p_hal->iDecodedNum);
}
#endif

6
mpp/legacy/vpu_api.cpp
View File

@@ -203,8 +203,7 @@ public:
VpulibDlsym()
: rkapi_hdl(NULL),
rkvpu_open_cxt(NULL),
rkvpu_close_cxt(NULL)
{
rkvpu_close_cxt(NULL) {
if (!!access("/dev/rkvdec", F_OK)) {
rkapi_hdl = dlopen("/system/lib/librk_on2.so", RTLD_LAZY);
}
@@ -220,8 +219,7 @@ public:
}
}
~VpulibDlsym()
{
~VpulibDlsym() {
if (rkapi_hdl) {
dlclose(rkapi_hdl);
mpp_log("dlclose vpu lib");

3
mpp/legacy/vpu_api_legacy.cpp
View File

@@ -386,8 +386,7 @@ RK_S32 VpuApiLegacy::control(VpuCodecContext *ctx, VPU_API_CMD cmd, void *param)
ImgWidth = ((p->ImgWidth & 0xFFFF) * 10) >> 3;
p->CodecType = (p->ImgWidth & 0x40000000) ? MPP_FMT_YUV422SP_10BIT : MPP_FMT_YUV420SP_10BIT;
}
else {
} else {
ImgWidth = (p->ImgWidth & 0xFFFF);
p->CodecType = (p->ImgWidth & 0x40000000) ? MPP_FMT_YUV422SP : MPP_FMT_YUV420SP;
}

12
osal/inc/mpp_thread.h
View File

@@ -207,26 +207,22 @@ public:
void start();
void stop();
void lock(MppThreadSignal id = THREAD_WORK)
{
void lock(MppThreadSignal id = THREAD_WORK) {
mpp_assert(id < THREAD_SIGNAL_BUTT);
mMutexCond[id].lock();
}
void unlock(MppThreadSignal id = THREAD_WORK)
{
void unlock(MppThreadSignal id = THREAD_WORK) {
mpp_assert(id < THREAD_SIGNAL_BUTT);
mMutexCond[id].unlock();
}
void wait(MppThreadSignal id = THREAD_WORK)
{
void wait(MppThreadSignal id = THREAD_WORK) {
mpp_assert(id < THREAD_SIGNAL_BUTT);
mMutexCond[id].wait();
}
void signal(MppThreadSignal id = THREAD_WORK)
{
void signal(MppThreadSignal id = THREAD_WORK) {
mpp_assert(id < THREAD_SIGNAL_BUTT);
mMutexCond[id].signal();
}