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git-svn-id: https://10.10.10.66:8443/svn/MediaProcessPlatform/trunk/mpp@1020 6e48237b-75ef-9749-8fc9-41990f28c85a
This commit is contained in:
GaoZhili
2016-07-14 09:34:04 +00:00
parent c7c9cc380b
commit 3249378118
23 changed files with 971 additions and 1084 deletions
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6
mpp/base/mpp_buffer_impl.cpp
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@@ -79,13 +79,11 @@ private:
struct list_head mListOrphan; struct list_head mListOrphan;
public: public:
static MppBufferService *get_instance() static MppBufferService *get_instance() {
{
static MppBufferService instance; static MppBufferService instance;
return &instance; return &instance;
} }
static Mutex *get_lock() static Mutex *get_lock() {
{
static Mutex lock; static Mutex lock;
return &lock; return &lock;
} }

2
mpp/codec/dec/h263/h263d_parser.c
View File

@@ -315,7 +315,7 @@ MPP_RET mpp_h263_parser_split(H263dParser ctx, MppPacket dst, MppPacket src)
RK_S32 pos_frm_end = p->pos_frm_end; RK_S32 pos_frm_end = p->pos_frm_end;
RK_U32 src_eos = mpp_packet_get_eos(src); RK_U32 src_eos = mpp_packet_get_eos(src);
RK_S32 src_pos = 0; RK_S32 src_pos = 0;
RK_U32 state = (RK_U32)-1; RK_U32 state = (RK_U32) - 1;
h263d_dbg_func("in\n"); h263d_dbg_func("in\n");

13
mpp/codec/dec/h264/h264d_api.c
View File

@@ -732,8 +732,7 @@ __RETURN:
FunctionOut(p_Dec->logctx.parr[RUN_PARSE]); FunctionOut(p_Dec->logctx.parr[RUN_PARSE]);
return ret = MPP_OK; return ret = MPP_OK;
__FAILED: __FAILED: {
{
H264_StorePic_t *dec_pic = p_Dec->p_Vid->dec_pic; H264_StorePic_t *dec_pic = p_Dec->p_Vid->dec_pic;
if (dec_pic) { if (dec_pic) {
H264D_WARNNING("[h264d_parse] h264d_parse failed.\n"); H264D_WARNNING("[h264d_parse] h264d_parse failed.\n");
@@ -795,19 +794,17 @@ MPP_RET h264d_callback(void *decoder, void *errinfo)
if (ctx->hard_err || task_dec->flags.had_error) { if (ctx->hard_err || task_dec->flags.had_error) {
if (task_dec->flags.used_for_ref) { if (task_dec->flags.used_for_ref) {
mpp_frame_set_errinfo(mframe, VPU_FRAME_ERR_UNKNOW); mpp_frame_set_errinfo(mframe, VPU_FRAME_ERR_UNKNOW);
} } else {
else {
mpp_frame_set_discard(mframe, VPU_FRAME_ERR_UNKNOW); mpp_frame_set_discard(mframe, VPU_FRAME_ERR_UNKNOW);
} }
} }
H264D_DBG(H264D_DBG_CALLBACK, "[CALLBACK] g_no=%d, out_idx=%d, dpberr=%d, harderr=%d, ref_flag=%d, errinfo=%d, discard=%d\n", H264D_DBG(H264D_DBG_CALLBACK, "[CALLBACK] g_no=%d, out_idx=%d, dpberr=%d, harderr=%d, ref_flag=%d, errinfo=%d, discard=%d\n",
p_Dec->p_Vid->g_framecnt, task_dec->output, task_dec->flags.had_error, ctx->hard_err, task_dec->flags.used_for_ref, p_Dec->p_Vid->g_framecnt, task_dec->output, task_dec->flags.had_error, ctx->hard_err, task_dec->flags.used_for_ref,
mpp_frame_get_errinfo(mframe), mpp_frame_get_discard(mframe)); mpp_frame_get_errinfo(mframe), mpp_frame_get_discard(mframe));
if (ctx->device_id == HAL_RKVDEC) { if (ctx->device_id == HAL_RKVDEC) {
H264D_DBG(H264D_DBG_CALLBACK, "[CALLBACK] sw[01]=%08x, sw[45]=%08x, sw[76]=%08x\n", p_regs[1], p_regs[45], p_regs[76]); H264D_DBG(H264D_DBG_CALLBACK, "[CALLBACK] sw[01]=%08x, sw[45]=%08x, sw[76]=%08x\n", p_regs[1], p_regs[45], p_regs[76]);
} } else if (ctx->device_id == HAL_VDPU) {
else if (ctx->device_id == HAL_VDPU) {
} }
} }

6
mpp/codec/dec/h264/h264d_fill.c
View File

@@ -34,9 +34,9 @@ static MPP_RET fill_slice_stream(H264dDxvaCtx_t *dxva_ctx, H264_Nalu_t *p_nal)
MPP_RET ret = MPP_ERR_UNKNOW; MPP_RET ret = MPP_ERR_UNKNOW;
DXVA_Slice_H264_Long *p_long = NULL; DXVA_Slice_H264_Long *p_long = NULL;
if (dxva_ctx->slice_count > MAX_SLICE_NUM) { if (dxva_ctx->slice_count > MAX_SLICE_NUM) {
H264D_ERR("error, slcie_num is larger than 1024"); H264D_ERR("error, slcie_num is larger than 1024");
goto __FAILED; goto __FAILED;
} }
p_long = &dxva_ctx->slice_long[dxva_ctx->slice_count]; p_long = &dxva_ctx->slice_long[dxva_ctx->slice_count];
memset(p_long, 0, sizeof(DXVA_Slice_H264_Long)); memset(p_long, 0, sizeof(DXVA_Slice_H264_Long));

6
mpp/codec/dec/h264/h264d_init.c
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@@ -478,9 +478,9 @@ static MPP_RET check_dpb_field_paired(H264_FrameStore_t *p_last, H264_StorePic_t
H264D_DBG(H264D_DBG_FIELD_PAIRED, "[check_field_paired] combine_flag=%d, last_used=%d, last_pic_struct=%d, curr_struct=%d", H264D_DBG(H264D_DBG_FIELD_PAIRED, "[check_field_paired] combine_flag=%d, last_used=%d, last_pic_struct=%d, curr_struct=%d",
dec_pic->combine_flag, (p_last ? p_last->is_used : -1), last_pic_structure, cur_structure); dec_pic->combine_flag, (p_last ? p_last->is_used : -1), last_pic_structure, cur_structure);
#else #else
(void)p_last; (void)p_last;
(void)dec_pic; (void)dec_pic;
(void)last_pic_structure; (void)last_pic_structure;
#endif #endif
return ret = MPP_OK; return ret = MPP_OK;
} }

4
mpp/codec/dec/h264/h264d_sps.c
View File

@@ -181,9 +181,9 @@ static MPP_RET parser_sps(BitReadCtx_t *p_bitctx, H264_SPS_t *cur_sps, H264_DecC
READ_UE(p_bitctx, &cur_sps->chroma_format_idc, "chroma_format_idc"); READ_UE(p_bitctx, &cur_sps->chroma_format_idc, "chroma_format_idc");
mpp_log_f("chroma_format_idc=%d \n", cur_sps->chroma_format_idc); mpp_log_f("chroma_format_idc=%d \n", cur_sps->chroma_format_idc);
if (cur_sps->chroma_format_idc > 2) { if (cur_sps->chroma_format_idc > 2) {
H264D_ERR("ERROR: Not support chroma_format_idc=%d.", cur_sps->chroma_format_idc); H264D_ERR("ERROR: Not support chroma_format_idc=%d.", cur_sps->chroma_format_idc);
p_Dec->errctx.un_spt_flag = VPU_FRAME_ERR_UNSUPPORT; p_Dec->errctx.un_spt_flag = VPU_FRAME_ERR_UNSUPPORT;
goto __FAILED; goto __FAILED;
} }
READ_UE(p_bitctx, &cur_sps->bit_depth_luma_minus8, "bit_depth_luma_minus8"); READ_UE(p_bitctx, &cur_sps->bit_depth_luma_minus8, "bit_depth_luma_minus8");
ASSERT(cur_sps->bit_depth_luma_minus8 < 7); ASSERT(cur_sps->bit_depth_luma_minus8 < 7);

6
mpp/codec/dec/m2v/m2vd_parser.c
View File

@@ -183,7 +183,7 @@ static MPP_RET m2vd_parser_init_ctx(M2VDParserContext *ctx, ParserCfg *cfg)
ctx->fp_dbg_yuv = fopen("/sdcard/m2vd_dbg_yuv_out.txt", "wb"); ctx->fp_dbg_yuv = fopen("/sdcard/m2vd_dbg_yuv_out.txt", "wb");
if (!ctx->fp_dbg_yuv) if (!ctx->fp_dbg_yuv)
mpp_log("open file failed: %s", "/sdcard/m2vd_dbg_yuv_out.txt"); mpp_log("open file failed: %s", "/sdcard/m2vd_dbg_yuv_out.txt");
}else{ } else {
RK_S32 k = 0; RK_S32 k = 0;
for (k = 0; k < M2VD_DBG_FILE_NUM; k++) for (k = 0; k < M2VD_DBG_FILE_NUM; k++)
ctx->fp_dbg_file[k] = NULL; ctx->fp_dbg_file[k] = NULL;
@@ -329,7 +329,7 @@ MPP_RET m2vd_parser_flush(void *ctx)
mpp_buf_slot_enqueue(p->frame_slots, p->frame_ref0->slot_index, QUEUE_DISPLAY); mpp_buf_slot_enqueue(p->frame_slots, p->frame_ref0->slot_index, QUEUE_DISPLAY);
p->frame_ref0->flags = 0; p->frame_ref0->flags = 0;
exit: exit:
#if 0 #if 0
if (p->eos) { if (p->eos) {
if ( p->frame_ref0->slot_index < 0xff) { if ( p->frame_ref0->slot_index < 0xff) {
mpp_buf_slot_set_prop(p->frame_slots, p->frame_ref0->slot_index, SLOT_EOS, &p->eos); mpp_buf_slot_set_prop(p->frame_slots, p->frame_ref0->slot_index, SLOT_EOS, &p->eos);
@@ -339,7 +339,7 @@ exit:
} }
} }
} }
#endif #endif
return ret; return ret;
} }

14
mpp/codec/dec/mpg4/mpg4d_parser.c
View File

@@ -409,7 +409,7 @@ static MPP_RET read_vop_complexity_estimation_header(Mpeg4Estimation *e, BitRead
if (e->interpolate_mc_q) SKIP_BITS(gb, 8); /* */ if (e->interpolate_mc_q) SKIP_BITS(gb, 8); /* */
} }
#else #else
(void)mp4Hdr; (void)mp4Hdr;
#endif #endif
} }
@@ -873,15 +873,15 @@ static MPP_RET mpeg4_parse_vop_header(Mpg4dParserImpl *p, BitReadCtx_t *gb)
} }
if ((mp4Hdr->vol.shape != MPEG4_VIDOBJLAY_SHAPE_BINARY_ONLY) && if ((mp4Hdr->vol.shape != MPEG4_VIDOBJLAY_SHAPE_BINARY_ONLY) &&
((mp4Hdr->vop.coding_type == MPEG4_P_VOP) || ((mp4Hdr->vop.coding_type == MPEG4_P_VOP) ||
(mp4Hdr->vop.coding_type == MPEG4_S_VOP && (mp4Hdr->vop.coding_type == MPEG4_S_VOP &&
mp4Hdr->vol.sprite_enable == MPEG4_SPRITE_GMC))) { mp4Hdr->vol.sprite_enable == MPEG4_SPRITE_GMC))) {
READ_BITS(gb, 1, &(mp4Hdr->vop.rounding)); /* rounding_type */ READ_BITS(gb, 1, &(mp4Hdr->vop.rounding)); /* rounding_type */
} }
if (mp4Hdr->vol.reduced_resolution_enable && if (mp4Hdr->vol.reduced_resolution_enable &&
mp4Hdr->vol.shape == MPEG4_VIDOBJLAY_SHAPE_RECTANGULAR && mp4Hdr->vol.shape == MPEG4_VIDOBJLAY_SHAPE_RECTANGULAR &&
(mp4Hdr->vop.coding_type == MPEG4_P_VOP || mp4Hdr->vop.coding_type == MPEG4_I_VOP)) { (mp4Hdr->vop.coding_type == MPEG4_P_VOP || mp4Hdr->vop.coding_type == MPEG4_I_VOP)) {
READ_BITS(gb, 1, &val); READ_BITS(gb, 1, &val);
} }
@@ -907,7 +907,7 @@ static MPP_RET mpeg4_parse_vop_header(Mpg4dParserImpl *p, BitReadCtx_t *gb)
if ((mp4Hdr->vol.sprite_enable == MPEG4_SPRITE_STATIC || if ((mp4Hdr->vol.sprite_enable == MPEG4_SPRITE_STATIC ||
mp4Hdr->vol.sprite_enable == MPEG4_SPRITE_GMC) && mp4Hdr->vol.sprite_enable == MPEG4_SPRITE_GMC) &&
mp4Hdr->vop.coding_type == MPEG4_S_VOP) { mp4Hdr->vop.coding_type == MPEG4_S_VOP) {
mpp_err("unsupport split mode %d coding type %d\n", mpp_err("unsupport split mode %d coding type %d\n",
mp4Hdr->vol.sprite_enable, mp4Hdr->vop.coding_type); mp4Hdr->vol.sprite_enable, mp4Hdr->vop.coding_type);
return MPP_ERR_STREAM; return MPP_ERR_STREAM;
@@ -1178,7 +1178,7 @@ MPP_RET mpp_mpg4_parser_split(Mpg4dParser ctx, MppPacket dst, MppPacket src)
RK_S32 pos_frm_end = p->pos_frm_end; RK_S32 pos_frm_end = p->pos_frm_end;
RK_U32 src_eos = mpp_packet_get_eos(src); RK_U32 src_eos = mpp_packet_get_eos(src);
RK_S32 src_pos = 0; RK_S32 src_pos = 0;
RK_U32 state = (RK_U32)-1; RK_U32 state = (RK_U32) - 1;
mpg4d_dbg_func("in\n"); mpg4d_dbg_func("in\n");

5
mpp/hal/inc/hal_task.h
View File

@@ -36,13 +36,12 @@ typedef struct IOInterruptCB {
void *opaque; void *opaque;
} IOInterruptCB; } IOInterruptCB;
typedef struct IOCallbackCtx_t typedef struct IOCallbackCtx_t {
{
RK_U32 device_id; RK_U32 device_id;
void *task; void *task;
RK_U32 *regs; RK_U32 *regs;
RK_U32 hard_err; RK_U32 hard_err;
}IOCallbackCtx; } IOCallbackCtx;
/* /*
* modified by parser * modified by parser

2
mpp/hal/mpp_hal.cpp
View File

@@ -48,7 +48,7 @@ static const MppHalApi *hw_apis[] = {
&hal_api_h265d, &hal_api_h265d,
&hal_api_m2vd, &hal_api_m2vd,
&hal_api_mpg4d, &hal_api_mpg4d,
&hal_api_vp8d, &hal_api_vp8d,
&hal_api_vp9d, &hal_api_vp9d,
&hal_api_dummy_dec, &hal_api_dummy_dec,
&hal_api_dummy_enc, &hal_api_dummy_enc,

3
mpp/hal/rkdec/h264d/hal_h264d_rkv_pkt.c
View File

@@ -45,7 +45,8 @@
#define FPGA_TEST 0 #define FPGA_TEST 0
const enum { const enum
{
H264ScalingList4x4Length = 16, H264ScalingList4x4Length = 16,
H264ScalingList8x8Length = 64, H264ScalingList8x8Length = 64,
} ScalingListLength; } ScalingListLength;

12
mpp/hal/rkdec/h264d/hal_h264d_rkv_reg.c
View File

@@ -465,8 +465,7 @@ __SKIP_HARD:
|| p_regs->swreg1_int.sw_dec_empty_sta || p_regs->swreg1_int.sw_dec_empty_sta
|| p_regs->swreg45_strmd_error_status.sw_strmd_error_status || p_regs->swreg45_strmd_error_status.sw_strmd_error_status
|| p_regs->swreg45_strmd_error_status.sw_colmv_error_ref_picidx || p_regs->swreg45_strmd_error_status.sw_colmv_error_ref_picidx
|| p_regs->swreg76_h264_errorinfo_num.sw_strmd_detect_error_flag) || p_regs->swreg76_h264_errorinfo_num.sw_strmd_detect_error_flag) {
{
m_ctx.hard_err = 1; m_ctx.hard_err = 1;
} }
m_ctx.task = (void *)&task->dec; m_ctx.task = (void *)&task->dec;
@@ -539,13 +538,12 @@ MPP_RET rkv_h264d_control(void *hal, RK_S32 cmd_type, void *param)
INP_CHECK(ret, NULL == p_hal); INP_CHECK(ret, NULL == p_hal);
FunctionIn(p_hal->logctx.parr[RUN_HAL]); FunctionIn(p_hal->logctx.parr[RUN_HAL]);
switch ((MpiCmd)cmd_type) switch ((MpiCmd)cmd_type) {
{
case MPP_CODEC_SET_FRAME_INFO: { case MPP_CODEC_SET_FRAME_INFO: {
VPU_GENERIC *p = (VPU_GENERIC *)param; VPU_GENERIC *p = (VPU_GENERIC *)param;
if (p->CodecType == MPP_FMT_YUV422SP){ if (p->CodecType == MPP_FMT_YUV422SP) {
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align_422); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align_422);
mpp_log_f("control format YUV422SP \n"); mpp_log_f("control format YUV422SP \n");
} }
break; break;
} }

770
mpp/hal/rkdec/h264d/hal_h264d_vdpu_pkt.c
View File

@@ -208,241 +208,236 @@ static RK_U32 check_dpb_buffer_is_valid(H264dHalCtx_t *p_hal, RK_U32 dpb_idx)
} }
static MPP_RET vdpu_set_refer_pic_idx(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 val) static MPP_RET vdpu_set_refer_pic_idx(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 val)
{ {
switch (i) switch (i) {
{ case 0:
case 0: p_regs->sw76.num_ref_idx0 = val;
p_regs->sw76.num_ref_idx0 = val; break;
break; case 1:
case 1: p_regs->sw76.num_ref_idx1 = val;
p_regs->sw76.num_ref_idx1 = val; break;
break; case 2:
case 2: p_regs->sw77.num_ref_idx2 = val;
p_regs->sw77.num_ref_idx2 = val; break;
break; case 3:
case 3: p_regs->sw77.num_ref_idx3 = val;
p_regs->sw77.num_ref_idx3 = val; break;
break; case 4:
case 4: p_regs->sw78.num_ref_idx4 = val;
p_regs->sw78.num_ref_idx4 = val; break;
break; case 5:
case 5: p_regs->sw78.num_ref_idx5 = val;
p_regs->sw78.num_ref_idx5 = val; break;
break; case 6:
case 6: p_regs->sw79.num_ref_idx6 = val;
p_regs->sw79.num_ref_idx6 = val; break;
break; case 7:
case 7: p_regs->sw79.num_ref_idx7 = val;
p_regs->sw79.num_ref_idx7 = val; break;
break; case 8:
case 8: p_regs->sw80.num_ref_idx8 = val;
p_regs->sw80.num_ref_idx8 = val; break;
break; case 9:
case 9: p_regs->sw80.num_ref_idx9 = val;
p_regs->sw80.num_ref_idx9 = val; break;
break; case 10:
case 10: p_regs->sw81.num_ref_idx10 = val;
p_regs->sw81.num_ref_idx10 = val; break;
break; case 11:
case 11: p_regs->sw81.num_ref_idx11 = val;
p_regs->sw81.num_ref_idx11 = val; break;
break; case 12:
case 12: p_regs->sw82.num_ref_idx12 = val;
p_regs->sw82.num_ref_idx12 = val; break;
break; case 13:
case 13: p_regs->sw82.num_ref_idx13 = val;
p_regs->sw82.num_ref_idx13 = val; break;
break; case 14:
case 14: p_regs->sw83.num_ref_idx14 = val;
p_regs->sw83.num_ref_idx14 = val; break;
break; case 15:
case 15: p_regs->sw83.num_ref_idx15 = val;
p_regs->sw83.num_ref_idx15 = val; break;
break; default:
default: break;
break; }
}
return MPP_OK; return MPP_OK;
} }
static MPP_RET vdpu_set_refer_pic_list_p(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 val) static MPP_RET vdpu_set_refer_pic_list_p(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 val)
{ {
switch (i) switch (i) {
{ case 0:
case 0: p_regs->sw106.init_reflist_pf0 = val;
p_regs->sw106.init_reflist_pf0 = val; break;
break; case 1:
case 1: p_regs->sw106.init_reflist_pf1 = val;
p_regs->sw106.init_reflist_pf1 = val; break;
break; case 2:
case 2: p_regs->sw106.init_reflist_pf2 = val;
p_regs->sw106.init_reflist_pf2 = val; break;
break; case 3:
case 3: p_regs->sw106.init_reflist_pf3 = val;
p_regs->sw106.init_reflist_pf3 = val; break;
break; case 4:
case 4: p_regs->sw74.init_reflist_pf4 = val;
p_regs->sw74.init_reflist_pf4 = val; break;
break; case 5:
case 5: p_regs->sw74.init_reflist_pf5 = val;
p_regs->sw74.init_reflist_pf5 = val; break;
break; case 6:
case 6: p_regs->sw74.init_reflist_pf6 = val;
p_regs->sw74.init_reflist_pf6 = val; break;
break; case 7:
case 7: p_regs->sw74.init_reflist_pf7 = val;
p_regs->sw74.init_reflist_pf7 = val; break;
break; case 8:
case 8: p_regs->sw74.init_reflist_pf8 = val;
p_regs->sw74.init_reflist_pf8 = val; break;
break; case 9:
case 9: p_regs->sw74.init_reflist_pf9 = val;
p_regs->sw74.init_reflist_pf9 = val; break;
break; case 10:
case 10: p_regs->sw75.init_reflist_pf10 = val;
p_regs->sw75.init_reflist_pf10 = val; break;
break; case 11:
case 11: p_regs->sw75.init_reflist_pf11 = val;
p_regs->sw75.init_reflist_pf11 = val; break;
break; case 12:
case 12: p_regs->sw75.init_reflist_pf12 = val;
p_regs->sw75.init_reflist_pf12 = val; break;
break; case 13:
case 13: p_regs->sw75.init_reflist_pf13 = val;
p_regs->sw75.init_reflist_pf13 = val; break;
break; case 14:
case 14: p_regs->sw75.init_reflist_pf14 = val;
p_regs->sw75.init_reflist_pf14 = val; break;
break; case 15:
case 15: p_regs->sw75.init_reflist_pf15 = val;
p_regs->sw75.init_reflist_pf15 = val; break;
break; default:
default: break;
break; }
}
return MPP_OK; return MPP_OK;
} }
static MPP_RET vdpu_set_refer_pic_list_b0(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 val) static MPP_RET vdpu_set_refer_pic_list_b0(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 val)
{ {
switch (i) switch (i) {
{ case 0:
case 0: p_regs->sw100.init_reflist_df0 = val;
p_regs->sw100.init_reflist_df0 = val; break;
break; case 1:
case 1: p_regs->sw100.init_reflist_df1 = val;
p_regs->sw100.init_reflist_df1 = val; break;
break; case 2:
case 2: p_regs->sw100.init_reflist_df2 = val;
p_regs->sw100.init_reflist_df2 = val; break;
break; case 3:
case 3: p_regs->sw100.init_reflist_df3 = val;
p_regs->sw100.init_reflist_df3 = val; break;
break; case 4:
case 4: p_regs->sw100.init_reflist_df4 = val;
p_regs->sw100.init_reflist_df4 = val; break;
break; case 5:
case 5: p_regs->sw100.init_reflist_df5 = val;
p_regs->sw100.init_reflist_df5 = val; break;
break; case 6:
case 6: p_regs->sw101.init_reflist_df6 = val;
p_regs->sw101.init_reflist_df6 = val; break;
break; case 7:
case 7: p_regs->sw101.init_reflist_df7 = val;
p_regs->sw101.init_reflist_df7 = val; break;
break; case 8:
case 8: p_regs->sw101.init_reflist_df8 = val;
p_regs->sw101.init_reflist_df8 = val; break;
break; case 9:
case 9: p_regs->sw101.init_reflist_df9 = val;
p_regs->sw101.init_reflist_df9 = val; break;
break; case 10:
case 10: p_regs->sw101.init_reflist_df10 = val;
p_regs->sw101.init_reflist_df10 = val; break;
break; case 11:
case 11: p_regs->sw101.init_reflist_df11 = val;
p_regs->sw101.init_reflist_df11 = val; break;
break; case 12:
case 12: p_regs->sw102.init_reflist_df12 = val;
p_regs->sw102.init_reflist_df12 = val; break;
break; case 13:
case 13: p_regs->sw102.init_reflist_df13 = val;
p_regs->sw102.init_reflist_df13 = val; break;
break; case 14:
case 14: p_regs->sw102.init_reflist_df14 = val;
p_regs->sw102.init_reflist_df14 = val; break;
break; case 15:
case 15: p_regs->sw102.init_reflist_df15 = val;
p_regs->sw102.init_reflist_df15 = val; break;
break; default:
default: break;
break; }
}
return MPP_OK; return MPP_OK;
} }
static MPP_RET vdpu_set_refer_pic_list_b1(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 val) static MPP_RET vdpu_set_refer_pic_list_b1(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 val)
{ {
switch (i) switch (i) {
{ case 0:
case 0: p_regs->sw103.init_reflist_db0 = val;
p_regs->sw103.init_reflist_db0 = val; break;
break; case 1:
case 1: p_regs->sw103.init_reflist_db1 = val;
p_regs->sw103.init_reflist_db1 = val; break;
break; case 2:
case 2: p_regs->sw103.init_reflist_db2 = val;
p_regs->sw103.init_reflist_db2 = val; break;
break; case 3:
case 3: p_regs->sw103.init_reflist_db3 = val;
p_regs->sw103.init_reflist_db3 = val; break;
break; case 4:
case 4: p_regs->sw103.init_reflist_db4 = val;
p_regs->sw103.init_reflist_db4 = val; break;
break; case 5:
case 5: p_regs->sw103.init_reflist_db5 = val;
p_regs->sw103.init_reflist_db5 = val; break;
break; case 6:
case 6: p_regs->sw104.init_reflist_db6 = val;
p_regs->sw104.init_reflist_db6 = val; break;
break; case 7:
case 7: p_regs->sw104.init_reflist_db7 = val;
p_regs->sw104.init_reflist_db7 = val; break;
break; case 8:
case 8: p_regs->sw104.init_reflist_db8 = val;
p_regs->sw104.init_reflist_db8 = val; break;
break; case 9:
case 9: p_regs->sw104.init_reflist_db9 = val;
p_regs->sw104.init_reflist_db9 = val; break;
break; case 10:
case 10: p_regs->sw104.init_reflist_db10 = val;
p_regs->sw104.init_reflist_db10 = val; break;
break; case 11:
case 11: p_regs->sw104.init_reflist_db11 = val;
p_regs->sw104.init_reflist_db11 = val; break;
break; case 12:
case 12: p_regs->sw105.init_reflist_db12 = val;
p_regs->sw105.init_reflist_db12 = val; break;
break; case 13:
case 13: p_regs->sw105.init_reflist_db13 = val;
p_regs->sw105.init_reflist_db13 = val; break;
break; case 14:
case 14: p_regs->sw105.init_reflist_db14 = val;
p_regs->sw105.init_reflist_db14 = val; break;
break; case 15:
case 15: p_regs->sw105.init_reflist_db15 = val;
p_regs->sw105.init_reflist_db15 = val; break;
break; default:
default: break;
break; }
}
return MPP_OK; return MPP_OK;
} }
static MPP_RET vdpu_set_refer_pic_base_addr(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U32 val) static MPP_RET vdpu_set_refer_pic_base_addr(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U32 val)
{ {
switch (i) switch (i) {
{
case 0: case 0:
p_regs->sw84.ref0_st_addr = val; p_regs->sw84.ref0_st_addr = val;
break; break;
@@ -494,7 +489,7 @@ static MPP_RET vdpu_set_refer_pic_base_addr(H264dVdpuRegs_t *p_regs, RK_U32 i, R
default: default:
break; break;
} }
return MPP_OK; return MPP_OK;
} }
/*! /*!
*********************************************************************** ***********************************************************************
@@ -507,8 +502,8 @@ MPP_RET vdpu_set_pic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
{ {
MPP_RET ret = MPP_ERR_UNKNOW; MPP_RET ret = MPP_ERR_UNKNOW;
p_regs->sw110.pic_mb_w = p_hal->pp->wFrameWidthInMbsMinus1 + 1; p_regs->sw110.pic_mb_w = p_hal->pp->wFrameWidthInMbsMinus1 + 1;
p_regs->sw110.pic_mb_h = (2 - p_hal->pp->frame_mbs_only_flag) * (p_hal->pp->wFrameHeightInMbsMinus1 + 1); p_regs->sw110.pic_mb_h = (2 - p_hal->pp->frame_mbs_only_flag) * (p_hal->pp->wFrameHeightInMbsMinus1 + 1);
return ret = MPP_OK; return ret = MPP_OK;
} }
@@ -521,114 +516,108 @@ MPP_RET vdpu_set_pic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
//extern "C" //extern "C"
MPP_RET vdpu_set_vlc_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) MPP_RET vdpu_set_vlc_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
{ {
RK_U32 i = 0; RK_U32 i = 0;
MPP_RET ret = MPP_ERR_UNKNOW; MPP_RET ret = MPP_ERR_UNKNOW;
DXVA_PicParams_H264_MVC *pp = p_hal->pp; DXVA_PicParams_H264_MVC *pp = p_hal->pp;
FunctionIn(p_hal->logctx.parr[RUN_HAL]); FunctionIn(p_hal->logctx.parr[RUN_HAL]);
p_regs->sw57.dec_wr_extmen_dis = 0; p_regs->sw57.dec_wr_extmen_dis = 0;
p_regs->sw57.rlc_mode_en = 0; p_regs->sw57.rlc_mode_en = 0;
p_regs->sw51.qp_init_val = pp->pic_init_qp_minus26 + 26; p_regs->sw51.qp_init_val = pp->pic_init_qp_minus26 + 26;
p_regs->sw114.max_refidx0 = pp->num_ref_idx_l0_active_minus1 + 1; p_regs->sw114.max_refidx0 = pp->num_ref_idx_l0_active_minus1 + 1;
p_regs->sw111.max_refnum = pp->num_ref_frames; p_regs->sw111.max_refnum = pp->num_ref_frames;
p_regs->sw112.cur_frm_len = pp->log2_max_frame_num_minus4 + 4; p_regs->sw112.cur_frm_len = pp->log2_max_frame_num_minus4 + 4;
p_regs->sw112.curfrm_num = pp->frame_num; p_regs->sw112.curfrm_num = pp->frame_num;
p_regs->sw115.const_intra_en = pp->constrained_intra_pred_flag; p_regs->sw115.const_intra_en = pp->constrained_intra_pred_flag;
p_regs->sw112.dblk_ctrl_flag = pp->deblocking_filter_control_present_flag; p_regs->sw112.dblk_ctrl_flag = pp->deblocking_filter_control_present_flag;
p_regs->sw112.rpcp_flag = pp->redundant_pic_cnt_present_flag; p_regs->sw112.rpcp_flag = pp->redundant_pic_cnt_present_flag;
p_regs->sw113.refpic_mk_len = p_hal->slice_long[0].drpm_used_bitlen; p_regs->sw113.refpic_mk_len = p_hal->slice_long[0].drpm_used_bitlen;
p_regs->sw115.idr_pic_flag = p_hal->slice_long[0].idr_flag; p_regs->sw115.idr_pic_flag = p_hal->slice_long[0].idr_flag;
p_regs->sw113.idr_pic_id = p_hal->slice_long[0].idr_pic_id; p_regs->sw113.idr_pic_id = p_hal->slice_long[0].idr_pic_id;
p_regs->sw114.pps_id = p_hal->slice_long[0].active_pps_id; p_regs->sw114.pps_id = p_hal->slice_long[0].active_pps_id;
p_regs->sw114.poc_field_len = p_hal->slice_long[0].poc_used_bitlen; p_regs->sw114.poc_field_len = p_hal->slice_long[0].poc_used_bitlen;
/* reference picture flags, TODO separate fields */ /* reference picture flags, TODO separate fields */
if (pp->field_pic_flag) { if (pp->field_pic_flag) {
RK_U32 validTmp = 0, validFlags = 0; RK_U32 validTmp = 0, validFlags = 0;
RK_U32 longTermTmp = 0, longTermflags = 0; RK_U32 longTermTmp = 0, longTermflags = 0;
for (i = 0; i < 32; i++) { for (i = 0; i < 32; i++) {
if (pp->RefFrameList[i / 2].bPicEntry == 0xff) { //!< invalid if (pp->RefFrameList[i / 2].bPicEntry == 0xff) { //!< invalid
longTermflags <<= 1; longTermflags <<= 1;
validFlags <<= 1; validFlags <<= 1;
} } else {
else { longTermTmp = pp->RefFrameList[i / 2].AssociatedFlag; //!< get long term flag
longTermTmp = pp->RefFrameList[i / 2].AssociatedFlag; //!< get long term flag longTermflags = (longTermflags << 1) | longTermTmp;
longTermflags = (longTermflags << 1) | longTermTmp;
validTmp = check_dpb_buffer_is_valid(p_hal, pp->RefFrameList[i / 2].Index7Bits); validTmp = check_dpb_buffer_is_valid(p_hal, pp->RefFrameList[i / 2].Index7Bits);
validTmp = validTmp && ((pp->UsedForReferenceFlags >> i) & 0x01); validTmp = validTmp && ((pp->UsedForReferenceFlags >> i) & 0x01);
validFlags = (validFlags << 1) | validTmp; validFlags = (validFlags << 1) | validTmp;
} }
} }
p_regs->sw107.refpic_term_flag = longTermflags; p_regs->sw107.refpic_term_flag = longTermflags;
p_regs->sw108.refpic_valid_flag = validFlags; p_regs->sw108.refpic_valid_flag = validFlags;
} } else {
else { RK_U32 validTmp = 0, validFlags = 0;
RK_U32 validTmp = 0, validFlags = 0; RK_U32 longTermTmp = 0, longTermflags = 0;
RK_U32 longTermTmp = 0, longTermflags = 0; for (i = 0; i < 16; i++) {
for (i = 0; i < 16; i++) { if (pp->RefFrameList[i].bPicEntry == 0xff) { //!< invalid
if (pp->RefFrameList[i].bPicEntry == 0xff) { //!< invalid longTermflags <<= 1;
longTermflags <<= 1; validFlags <<= 1;
validFlags <<= 1; } else {
} longTermTmp = pp->RefFrameList[i].AssociatedFlag;
else { longTermflags = (longTermflags << 1) | longTermTmp;
longTermTmp = pp->RefFrameList[i].AssociatedFlag; validTmp = check_dpb_buffer_is_valid(p_hal, pp->RefFrameList[i].Index7Bits);
longTermflags = (longTermflags << 1) | longTermTmp; validTmp = validTmp && ((pp->UsedForReferenceFlags >> (2 * i)) & 0x03);
validTmp = check_dpb_buffer_is_valid(p_hal, pp->RefFrameList[i].Index7Bits); validFlags = (validFlags << 1) | validTmp;
validTmp = validTmp && ((pp->UsedForReferenceFlags >> (2 * i)) & 0x03); }
validFlags = (validFlags << 1) | validTmp; }
} p_regs->sw107.refpic_term_flag = (longTermflags << 16);
} p_regs->sw108.refpic_valid_flag = (validFlags << 16);
p_regs->sw107.refpic_term_flag = (longTermflags << 16); }
p_regs->sw108.refpic_valid_flag = (validFlags << 16);
}
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
if (pp->RefFrameList[i].bPicEntry != 0xff) { //!< valid if (pp->RefFrameList[i].bPicEntry != 0xff) { //!< valid
if (pp->RefFrameList[i].AssociatedFlag) { //!< longterm flag if (pp->RefFrameList[i].AssociatedFlag) { //!< longterm flag
vdpu_set_refer_pic_idx(p_regs, i, pp->LongTermPicNumList[i]); //!< pic_num vdpu_set_refer_pic_idx(p_regs, i, pp->LongTermPicNumList[i]); //!< pic_num
} } else {
else {
vdpu_set_refer_pic_idx(p_regs, i, pp->FrameNumList[i]); //< frame_num vdpu_set_refer_pic_idx(p_regs, i, pp->FrameNumList[i]); //< frame_num
} }
} }
} }
p_regs->sw57.rd_cnt_tab_en = 1; p_regs->sw57.rd_cnt_tab_en = 1;
//!< set poc to buffer //!< set poc to buffer
{ {
RK_U32 *pocBase = NULL; RK_U32 *pocBase = NULL;
pocBase = (RK_U32 *)((RK_U8 *)mpp_buffer_get_ptr(p_hal->cabac_buf) + VDPU_CABAC_TAB_SIZE); pocBase = (RK_U32 *)((RK_U8 *)mpp_buffer_get_ptr(p_hal->cabac_buf) + VDPU_CABAC_TAB_SIZE);
//!< set reference reorder poc //!< set reference reorder poc
for (i = 0; i < 32; i++) { for (i = 0; i < 32; i++) {
if (pp->RefFrameList[i / 2].bPicEntry != 0xff) { if (pp->RefFrameList[i / 2].bPicEntry != 0xff) {
*pocBase++ = pp->FieldOrderCntList[i / 2][i & 0x1]; *pocBase++ = pp->FieldOrderCntList[i / 2][i & 0x1];
} } else {
else { *pocBase++ = 0;
*pocBase++ = 0; }
} }
} //!< set current poc
//!< set current poc if (pp->field_pic_flag || !pp->MbaffFrameFlag) {
if (pp->field_pic_flag || !pp->MbaffFrameFlag) { *pocBase++ = pp->CurrFieldOrderCnt[0];
*pocBase++ = pp->CurrFieldOrderCnt[0]; *pocBase++ = pp->CurrFieldOrderCnt[1];
*pocBase++ = pp->CurrFieldOrderCnt[1]; } else {
} *pocBase++ = pp->CurrFieldOrderCnt[0];
else { *pocBase++ = pp->CurrFieldOrderCnt[1];
*pocBase++ = pp->CurrFieldOrderCnt[0]; }
*pocBase++ = pp->CurrFieldOrderCnt[1]; }
} p_regs->sw115.cabac_en = pp->entropy_coding_mode_flag;
} //!< stream position update
p_regs->sw115.cabac_en = pp->entropy_coding_mode_flag; {
//!< stream position update MppBuffer bitstream_buf = NULL;
{ p_regs->sw57.st_code_exit = 1;
MppBuffer bitstream_buf = NULL; mpp_buf_slot_get_prop(p_hal->packet_slots, p_hal->in_task->input, SLOT_BUFFER, &bitstream_buf);
p_regs->sw57.st_code_exit = 1; p_regs->sw109.strm_start_bit = 0; //!< sodb stream start bit
mpp_buf_slot_get_prop(p_hal->packet_slots, p_hal->in_task->input, SLOT_BUFFER, &bitstream_buf); if (VPUClientGetIOMMUStatus() > 0) {
p_regs->sw109.strm_start_bit = 0; //!< sodb stream start bit p_regs->sw64.rlc_vlc_st_adr = mpp_buffer_get_fd(bitstream_buf);
if (VPUClientGetIOMMUStatus() > 0) { }
p_regs->sw64.rlc_vlc_st_adr = mpp_buffer_get_fd(bitstream_buf); p_regs->sw51.stream_len = p_hal->strm_len;
} }
p_regs->sw51.stream_len = p_hal->strm_len;
}
FunctionOut(p_hal->logctx.parr[RUN_HAL]); FunctionOut(p_hal->logctx.parr[RUN_HAL]);
return ret = MPP_OK; return ret = MPP_OK;
@@ -656,16 +645,13 @@ MPP_RET vdpu_set_ref_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
nn = p_hal->pp->CurrPic.AssociatedFlag ? (2 * i + 1) : (2 * i); nn = p_hal->pp->CurrPic.AssociatedFlag ? (2 * i + 1) : (2 * i);
if (p_long->RefPicList[j][nn].bPicEntry == 0xff) { if (p_long->RefPicList[j][nn].bPicEntry == 0xff) {
val = g_ValueList[i]; val = g_ValueList[i];
} } else {
else {
val = p_long->RefPicList[j][nn].Index7Bits; val = p_long->RefPicList[j][nn].Index7Bits;
} }
} } else { //!< frame
else { //!< frame
if (p_long->RefPicList[j][i].bPicEntry == 0xff) { if (p_long->RefPicList[j][i].bPicEntry == 0xff) {
val = g_ValueList[i]; val = g_ValueList[i];
} } else {
else {
val = p_long->RefPicList[j][i].Index7Bits; val = p_long->RefPicList[j][i].Index7Bits;
} }
} }
@@ -699,26 +685,25 @@ MPP_RET vdpu_set_ref_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
//extern "C" //extern "C"
MPP_RET vdpu_set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) MPP_RET vdpu_set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
{ {
RK_U32 i = 0, j = 0; RK_U32 i = 0, j = 0;
RK_U32 outPhyAddr = 0; RK_U32 outPhyAddr = 0;
MppBuffer frame_buf = NULL; MppBuffer frame_buf = NULL;
MPP_RET ret = MPP_ERR_UNKNOW; MPP_RET ret = MPP_ERR_UNKNOW;
DXVA_PicParams_H264_MVC *pp = p_hal->pp; DXVA_PicParams_H264_MVC *pp = p_hal->pp;
DXVA_Slice_H264_Long *p_long = &p_hal->slice_long[0]; DXVA_Slice_H264_Long *p_long = &p_hal->slice_long[0];
FunctionIn(p_hal->logctx.parr[RUN_HAL]); FunctionIn(p_hal->logctx.parr[RUN_HAL]);
/* reference picture physic address */ /* reference picture physic address */
for (i = 0, j = 0xff; i < MPP_ARRAY_ELEMS(pp->RefFrameList); i++) { for (i = 0, j = 0xff; i < MPP_ARRAY_ELEMS(pp->RefFrameList); i++) {
RK_U32 val = 0; RK_U32 val = 0;
RK_U32 top_closer = 0; RK_U32 top_closer = 0;
RK_U32 field_flag = 0; RK_U32 field_flag = 0;
if (pp->RefFrameList[i].bPicEntry != 0xff) { if (pp->RefFrameList[i].bPicEntry != 0xff) {
mpp_buf_slot_get_prop(p_hal->frame_slots, pp->RefFrameList[i].Index7Bits, SLOT_BUFFER, &frame_buf); //!< reference phy addr mpp_buf_slot_get_prop(p_hal->frame_slots, pp->RefFrameList[i].Index7Bits, SLOT_BUFFER, &frame_buf); //!< reference phy addr
j = i; j = i;
} } else {
else { mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &frame_buf); //!< current out phy addr
mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &frame_buf); //!< current out phy addr }
}
field_flag = ((pp->RefPicFiledFlags >> i) & 0x1) ? 0x2 : 0; field_flag = ((pp->RefPicFiledFlags >> i) & 0x1) ? 0x2 : 0;
if (field_flag) { if (field_flag) {
@@ -730,11 +715,9 @@ MPP_RET vdpu_set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
used_flag = ((pp->UsedForReferenceFlags >> (2 * i)) & 0x3); used_flag = ((pp->UsedForReferenceFlags >> (2 * i)) & 0x3);
if (used_flag & 0x3) { if (used_flag & 0x3) {
ref_poc = MPP_MIN(pp->FieldOrderCntList[i][0], pp->FieldOrderCntList[i][1]); ref_poc = MPP_MIN(pp->FieldOrderCntList[i][0], pp->FieldOrderCntList[i][1]);
} } else if (used_flag & 0x2) {
else if (used_flag & 0x2) {
ref_poc = pp->FieldOrderCntList[i][1]; ref_poc = pp->FieldOrderCntList[i][1];
} } else if (used_flag & 0x1) {
else if (used_flag & 0x1) {
ref_poc = pp->FieldOrderCntList[i][0]; ref_poc = pp->FieldOrderCntList[i][0];
} }
top_closer = (cur_poc < ref_poc) ? 0x1 : 0; top_closer = (cur_poc < ref_poc) ? 0x1 : 0;
@@ -745,63 +728,62 @@ MPP_RET vdpu_set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
val = mpp_buffer_get_fd(frame_buf) | (val << 10); val = mpp_buffer_get_fd(frame_buf) | (val << 10);
} }
vdpu_set_refer_pic_base_addr(p_regs, i, val); vdpu_set_refer_pic_base_addr(p_regs, i, val);
} }
/* inter-view reference picture */ /* inter-view reference picture */
{ {
H264dVdpuPriv_t *priv = (H264dVdpuPriv_t *)p_hal->priv; H264dVdpuPriv_t *priv = (H264dVdpuPriv_t *)p_hal->priv;
if (pp->curr_layer_id && priv->ilt_dpb && priv->ilt_dpb->valid /*pp->inter_view_flag*/) { if (pp->curr_layer_id && priv->ilt_dpb && priv->ilt_dpb->valid /*pp->inter_view_flag*/) {
mpp_buf_slot_get_prop(p_hal->frame_slots, priv->ilt_dpb->slot_index, SLOT_BUFFER, &frame_buf); mpp_buf_slot_get_prop(p_hal->frame_slots, priv->ilt_dpb->slot_index, SLOT_BUFFER, &frame_buf);
if (VPUClientGetIOMMUStatus() > 0) { if (VPUClientGetIOMMUStatus() > 0) {
p_regs->sw99.ref15_st_addr = mpp_buffer_get_fd(frame_buf); //!< inter-view base, ref15 p_regs->sw99.ref15_st_addr = mpp_buffer_get_fd(frame_buf); //!< inter-view base, ref15
} }
p_regs->sw108.refpic_valid_flag |= (pp->field_pic_flag ? 0x3 : 0x10000); p_regs->sw108.refpic_valid_flag |= (pp->field_pic_flag ? 0x3 : 0x10000);
} }
} }
p_regs->sw50.dec_fixed_quant = pp->curr_layer_id; //!< VDPU_MVC_E p_regs->sw50.dec_fixed_quant = pp->curr_layer_id; //!< VDPU_MVC_E
p_regs->sw50.dblk_flt_dis = 0; //!< filterDisable = 0; p_regs->sw50.dblk_flt_dis = 0; //!< filterDisable = 0;
mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &frame_buf); //!< current out phy addr mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &frame_buf); //!< current out phy addr
if (VPUClientGetIOMMUStatus() > 0) { if (VPUClientGetIOMMUStatus() > 0) {
outPhyAddr = mpp_buffer_get_fd(frame_buf); outPhyAddr = mpp_buffer_get_fd(frame_buf);
} }
if (pp->field_pic_flag && pp->CurrPic.AssociatedFlag) { if (pp->field_pic_flag && pp->CurrPic.AssociatedFlag) {
if (VPUClientGetIOMMUStatus() > 0) { if (VPUClientGetIOMMUStatus() > 0) {
outPhyAddr |= ((pp->wFrameWidthInMbsMinus1 + 1) * 16) << 10; outPhyAddr |= ((pp->wFrameWidthInMbsMinus1 + 1) * 16) << 10;
} } else {
else { outPhyAddr += (pp->wFrameWidthInMbsMinus1 + 1) * 16;
outPhyAddr += (pp->wFrameWidthInMbsMinus1 + 1) * 16; }
} }
} p_regs->sw63.dec_out_st_adr = outPhyAddr; //!< outPhyAddr, pp->CurrPic.Index7Bits
p_regs->sw63.dec_out_st_adr = outPhyAddr; //!< outPhyAddr, pp->CurrPic.Index7Bits p_regs->sw110.flt_offset_cb_qp = pp->chroma_qp_index_offset;
p_regs->sw110.flt_offset_cb_qp = pp->chroma_qp_index_offset; p_regs->sw110.flt_offset_cr_qp = pp->second_chroma_qp_index_offset;
p_regs->sw110.flt_offset_cr_qp = pp->second_chroma_qp_index_offset; /* set default value for register[41] to avoid illegal translation fd */
/* set default value for register[41] to avoid illegal translation fd */ {
{ RK_U32 dirMvOffset = 0;
RK_U32 dirMvOffset = 0; RK_U32 picSizeInMbs = 0;
RK_U32 picSizeInMbs = 0;
picSizeInMbs = p_hal->pp->wFrameWidthInMbsMinus1 + 1; picSizeInMbs = p_hal->pp->wFrameWidthInMbsMinus1 + 1;
picSizeInMbs = picSizeInMbs * (2 - pp->frame_mbs_only_flag) * (pp->wFrameHeightInMbsMinus1 + 1); picSizeInMbs = picSizeInMbs * (2 - pp->frame_mbs_only_flag) * (pp->wFrameHeightInMbsMinus1 + 1);
dirMvOffset = picSizeInMbs * ((p_hal->pp->chroma_format_idc == 0) ? 256 : 384); dirMvOffset = picSizeInMbs * ((p_hal->pp->chroma_format_idc == 0) ? 256 : 384);
dirMvOffset += (pp->field_pic_flag && pp->CurrPic.AssociatedFlag) ? (picSizeInMbs * 32) : 0; dirMvOffset += (pp->field_pic_flag && pp->CurrPic.AssociatedFlag) ? (picSizeInMbs * 32) : 0;
if (VPUClientGetIOMMUStatus() > 0) { if (VPUClientGetIOMMUStatus() > 0) {
p_regs->sw62.dmmv_st_adr = (mpp_buffer_get_fd(frame_buf) | (dirMvOffset << 6)); p_regs->sw62.dmmv_st_adr = (mpp_buffer_get_fd(frame_buf) | (dirMvOffset << 6));
} }
} }
p_regs->sw57.dmmv_wr_en = (p_long->nal_ref_idc != 0) ? 1 : 0; //!< defalut set 1 p_regs->sw57.dmmv_wr_en = (p_long->nal_ref_idc != 0) ? 1 : 0; //!< defalut set 1
p_regs->sw115.dlmv_method_en = pp->direct_8x8_inference_flag; p_regs->sw115.dlmv_method_en = pp->direct_8x8_inference_flag;
p_regs->sw115.weight_pred_en = pp->weighted_pred_flag; p_regs->sw115.weight_pred_en = pp->weighted_pred_flag;
p_regs->sw111.wp_bslice_sel = pp->weighted_bipred_idc; p_regs->sw111.wp_bslice_sel = pp->weighted_bipred_idc;
p_regs->sw114.max_refidx1 = (pp->num_ref_idx_l1_active_minus1 + 1); p_regs->sw114.max_refidx1 = (pp->num_ref_idx_l1_active_minus1 + 1);
p_regs->sw115.fieldpic_flag_exist = (!pp->frame_mbs_only_flag) ? 1 : 0; p_regs->sw115.fieldpic_flag_exist = (!pp->frame_mbs_only_flag) ? 1 : 0;
p_regs->sw57.curpic_code_sel = (!pp->frame_mbs_only_flag && (pp->MbaffFrameFlag || pp->field_pic_flag)) ? 1 : 0; p_regs->sw57.curpic_code_sel = (!pp->frame_mbs_only_flag && (pp->MbaffFrameFlag || pp->field_pic_flag)) ? 1 : 0;
p_regs->sw57.curpic_stru_sel = pp->field_pic_flag; p_regs->sw57.curpic_stru_sel = pp->field_pic_flag;
p_regs->sw57.pic_decfield_sel = (!pp->CurrPic.AssociatedFlag) ? 1 : 0; //!< bottomFieldFlag p_regs->sw57.pic_decfield_sel = (!pp->CurrPic.AssociatedFlag) ? 1 : 0; //!< bottomFieldFlag
p_regs->sw57.sequ_mbaff_en = pp->MbaffFrameFlag; p_regs->sw57.sequ_mbaff_en = pp->MbaffFrameFlag;
p_regs->sw115.tranf_8x8_flag_en = pp->transform_8x8_mode_flag; p_regs->sw115.tranf_8x8_flag_en = pp->transform_8x8_mode_flag;
p_regs->sw115.monochr_en = (p_long->profileIdc >= 100 && pp->chroma_format_idc == 0) ? 1 : 0; p_regs->sw115.monochr_en = (p_long->profileIdc >= 100 && pp->chroma_format_idc == 0) ? 1 : 0;
p_regs->sw115.scl_matrix_en = pp->scaleing_list_enable_flag; p_regs->sw115.scl_matrix_en = pp->scaleing_list_enable_flag;
{ {
RK_U32 offset = VDPU_CABAC_TAB_SIZE + VDPU_POC_BUF_SIZE; RK_U32 offset = VDPU_CABAC_TAB_SIZE + VDPU_POC_BUF_SIZE;
if (p_hal->pp->scaleing_list_enable_flag) { if (p_hal->pp->scaleing_list_enable_flag) {
@@ -811,18 +793,18 @@ MPP_RET vdpu_set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
for (i = 0; i < 6; i++) { for (i = 0; i < 6; i++) {
for (j = 0; j < 4; j++) { for (j = 0; j < 4; j++) {
temp = (p_hal->qm->bScalingLists4x4[i][4 * j + 0] << 24) | temp = (p_hal->qm->bScalingLists4x4[i][4 * j + 0] << 24) |
(p_hal->qm->bScalingLists4x4[i][4 * j + 1] << 16) | (p_hal->qm->bScalingLists4x4[i][4 * j + 1] << 16) |
(p_hal->qm->bScalingLists4x4[i][4 * j + 2] << 8) | (p_hal->qm->bScalingLists4x4[i][4 * j + 2] << 8) |
(p_hal->qm->bScalingLists4x4[i][4 * j + 3]); (p_hal->qm->bScalingLists4x4[i][4 * j + 3]);
*ptr++ = temp; *ptr++ = temp;
} }
} }
for (i = 0; i < 2; i++) { for (i = 0; i < 2; i++) {
for (j = 0; j < 16; j++) { for (j = 0; j < 16; j++) {
temp = (p_hal->qm->bScalingLists8x8[i][4 * j + 0] << 24) | temp = (p_hal->qm->bScalingLists8x8[i][4 * j + 0] << 24) |
(p_hal->qm->bScalingLists8x8[i][4 * j + 1] << 16) | (p_hal->qm->bScalingLists8x8[i][4 * j + 1] << 16) |
(p_hal->qm->bScalingLists8x8[i][4 * j + 2] << 8) | (p_hal->qm->bScalingLists8x8[i][4 * j + 2] << 8) |
(p_hal->qm->bScalingLists8x8[i][4 * j + 3]); (p_hal->qm->bScalingLists8x8[i][4 * j + 3]);
*ptr++ = temp; *ptr++ = temp;
} }
} }
@@ -831,9 +813,9 @@ MPP_RET vdpu_set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
p_regs->sw61.qtable_st_adr = mpp_buffer_get_fd(p_hal->cabac_buf); p_regs->sw61.qtable_st_adr = mpp_buffer_get_fd(p_hal->cabac_buf);
} }
} }
p_regs->sw57.dec_wr_extmen_dis = 0; //!< set defalut 0 p_regs->sw57.dec_wr_extmen_dis = 0; //!< set defalut 0
p_regs->sw57.addit_ch_fmt_wen = 0; p_regs->sw57.addit_ch_fmt_wen = 0;
p_regs->sw57.dec_st_work = 1; p_regs->sw57.dec_st_work = 1;
FunctionOut(p_hal->logctx.parr[RUN_HAL]); FunctionOut(p_hal->logctx.parr[RUN_HAL]);
return ret = MPP_OK; return ret = MPP_OK;
} }

958
mpp/hal/rkdec/h264d/hal_h264d_vdpu_pkt.h
View File

@@ -25,524 +25,446 @@
#include "hal_h264d_fifo.h" #include "hal_h264d_fifo.h"
#include "hal_h264d_global.h" #include "hal_h264d_global.h"
typedef struct typedef struct {
{ RK_U32 sw00_49[50];
RK_U32 sw00_49[50]; struct {
struct RK_U32 dec_tiled_msb : 1;
{ RK_U32 adtion_latency : 6;
RK_U32 dec_tiled_msb : 1; RK_U32 dec_fixed_quant : 1;
RK_U32 adtion_latency : 6; RK_U32 dblk_flt_dis : 1;
RK_U32 dec_fixed_quant : 1; RK_U32 skip_sel : 1;
RK_U32 dblk_flt_dis : 1; RK_U32 dec_ascmd0_dis : 1;
RK_U32 skip_sel : 1; RK_U32 adv_pref_dis : 1;
RK_U32 dec_ascmd0_dis : 1; RK_U32 dec_tiled_lsb : 1;
RK_U32 adv_pref_dis : 1; RK_U32 refbuf_thrd : 12;
RK_U32 dec_tiled_lsb : 1; RK_U32 refbuf_pid : 5;
RK_U32 refbuf_thrd : 12; RK_U32 reverse0 : 2;
RK_U32 refbuf_pid : 5; } sw50;
RK_U32 reverse0 : 2; struct {
}sw50; RK_U32 stream_len : 24;
struct RK_U32 stream_len_ext : 1;
{ RK_U32 qp_init_val : 6;
RK_U32 stream_len : 24; RK_U32 reverse0 : 1;
RK_U32 stream_len_ext : 1; } sw51;
RK_U32 qp_init_val : 6; struct {
RK_U32 reverse0 : 1; RK_U32 ydim_mbst : 8;
}sw51; RK_U32 xdim_mbst : 9;
struct RK_U32 adv_pref_thrd : 14;
{ RK_U32 reverse0 : 1;
RK_U32 ydim_mbst : 8; } sw52;
RK_U32 xdim_mbst : 9; struct {
RK_U32 adv_pref_thrd : 14; RK_U32 dec_fmt_sel : 4;
RK_U32 reverse0 : 1; RK_U32 reverse0 : 28;
}sw52; } sw53;
struct struct {
{ RK_U32 dec_in_endian : 1;
RK_U32 dec_fmt_sel : 4; RK_U32 dec_out_endian : 1;
RK_U32 reverse0 : 28; RK_U32 dec_in_wordsp : 1;
}sw53; RK_U32 dec_out_wordsp : 1;
struct RK_U32 dec_strm_wordsp : 1;
{ RK_U32 dec_strendian_e : 1;
RK_U32 dec_in_endian : 1; RK_U32 reverse0 : 26;
RK_U32 dec_out_endian : 1; } sw54;
RK_U32 dec_in_wordsp : 1; struct {
RK_U32 dec_out_wordsp : 1; RK_U32 dec_irq : 1;
RK_U32 dec_strm_wordsp : 1; RK_U32 dec_irq_dis : 1;
RK_U32 dec_strendian_e : 1; RK_U32 reverse0 : 2;
RK_U32 reverse0 : 26; RK_U32 dec_rdy_sts : 1;
}sw54; RK_U32 pp_bus_sts : 1;
struct RK_U32 buf_emt_sts : 1;
{ RK_U32 reverse1 : 1;
RK_U32 dec_irq : 1; RK_U32 aso_det_sts : 1;
RK_U32 dec_irq_dis : 1; RK_U32 slice_det_sts : 1;
RK_U32 reverse0 : 2; RK_U32 bslice_det_sts : 1;
RK_U32 dec_rdy_sts : 1; RK_U32 reverse2 : 1;
RK_U32 pp_bus_sts : 1; RK_U32 error_det_sts : 1;
RK_U32 buf_emt_sts : 1; RK_U32 timeout_det_sts : 1;
RK_U32 reverse1 : 1; RK_U32 reverse3 : 18;
RK_U32 aso_det_sts : 1; } sw55;
RK_U32 slice_det_sts : 1; struct {
RK_U32 bslice_det_sts : 1; RK_U32 dec_axi_id_rd : 8;
RK_U32 reverse2 : 1; RK_U32 dec_axi_id_wr : 8;
RK_U32 error_det_sts : 1; RK_U32 dec_max_burlen : 5;
RK_U32 timeout_det_sts : 1; RK_U32 bus_pos_sel : 1;
RK_U32 reverse3 : 18; RK_U32 dec_data_discd_en : 1;
}sw55; RK_U32 axi_sel : 1;
struct RK_U32 reverse0 : 8;
{ } sw56;
RK_U32 dec_axi_id_rd : 8; struct {
RK_U32 dec_axi_id_wr : 8; RK_U32 dec_st_work : 1;
RK_U32 dec_max_burlen : 5; RK_U32 refpic_buf2_en : 1;
RK_U32 bus_pos_sel : 1; RK_U32 dec_wr_extmen_dis : 1;
RK_U32 dec_data_discd_en : 1; RK_U32 reverse0 : 1;
RK_U32 axi_sel : 1; RK_U32 dec_clkgate_en : 1;
RK_U32 reverse0 : 8; RK_U32 timeout_sts_en : 1;
}sw56; RK_U32 rd_cnt_tab_en : 1;
struct RK_U32 sequ_mbaff_en : 1;
{ RK_U32 first_reftop_en : 1;
RK_U32 dec_st_work : 1; RK_U32 reftop_en : 1;
RK_U32 refpic_buf2_en : 1; RK_U32 dmmv_wr_en : 1;
RK_U32 dec_wr_extmen_dis : 1; RK_U32 sorspa_en : 1;
RK_U32 reverse0 : 1; RK_U32 fwd_refpic_mode_sel : 1;
RK_U32 dec_clkgate_en : 1; RK_U32 pic_decfield_sel : 1;
RK_U32 timeout_sts_en : 1; RK_U32 pic_type_sel0 : 1;
RK_U32 rd_cnt_tab_en : 1; RK_U32 pic_type_sel1 : 1;
RK_U32 sequ_mbaff_en : 1; RK_U32 curpic_stru_sel : 1;
RK_U32 first_reftop_en : 1; RK_U32 curpic_code_sel : 1;
RK_U32 reftop_en : 1; RK_U32 prog_jpeg_en : 1;
RK_U32 dmmv_wr_en : 1; RK_U32 divx3_en : 1;
RK_U32 sorspa_en : 1; RK_U32 rlc_mode_en : 1;
RK_U32 fwd_refpic_mode_sel : 1; RK_U32 addit_ch_fmt_wen : 1;
RK_U32 pic_decfield_sel : 1; RK_U32 st_code_exit : 1;
RK_U32 pic_type_sel0 : 1; RK_U32 reverse1 : 2;
RK_U32 pic_type_sel1 : 1; RK_U32 inter_dblspeed : 1;
RK_U32 curpic_stru_sel : 1; RK_U32 intra_dblspeed : 1;
RK_U32 curpic_code_sel : 1; RK_U32 intra_dbl3t : 1;
RK_U32 prog_jpeg_en : 1; RK_U32 pref_sigchan : 1;
RK_U32 divx3_en : 1; RK_U32 cache_en : 1;
RK_U32 rlc_mode_en : 1; RK_U32 reverse2 : 1;
RK_U32 addit_ch_fmt_wen : 1; RK_U32 dec_timeout_mode : 1;
RK_U32 st_code_exit : 1; } sw57;
RK_U32 reverse1 : 2; struct {
RK_U32 inter_dblspeed : 1; RK_U32 soft_rst : 1;
RK_U32 intra_dblspeed : 1; RK_U32 reverse0 : 31;
RK_U32 intra_dbl3t : 1; } sw58;
RK_U32 pref_sigchan : 1; struct {
RK_U32 cache_en : 1; RK_U32 reverse0 : 2;
RK_U32 reverse2 : 1; RK_U32 pflt_set0_tap2 : 10;
RK_U32 dec_timeout_mode : 1; RK_U32 pflt_set0_tap1 : 10;
}sw57; RK_U32 pflt_set0_tap0 : 10;
struct } sw59;
{ struct {
RK_U32 soft_rst : 1; RK_U32 addit_ch_st_adr : 32;
RK_U32 reverse0 : 31; } sw60;
}sw58; struct {
struct RK_U32 qtable_st_adr : 32;
{ } sw61;
RK_U32 reverse0 : 2; struct {
RK_U32 pflt_set0_tap2 : 10; RK_U32 dmmv_st_adr : 32;
RK_U32 pflt_set0_tap1 : 10; } sw62;
RK_U32 pflt_set0_tap0 : 10; struct {
}sw59; RK_U32 dec_out_st_adr : 32;
struct } sw63;
{ struct {
RK_U32 addit_ch_st_adr : 32; RK_U32 rlc_vlc_st_adr : 32;
}sw60; } sw64;
struct struct {
{ RK_U32 refbuf_y_offset : 9;
RK_U32 qtable_st_adr : 32; RK_U32 reserve0 : 3;
}sw61; RK_U32 refbuf_fildpar_mode_e : 1;
struct RK_U32 refbuf_idcal_e : 1;
{ RK_U32 refbuf_picid : 5;
RK_U32 dmmv_st_adr : 32; RK_U32 refbuf_thr_level : 12;
}sw62; RK_U32 refbuf_e : 1;
struct } sw65;
{ RK_U32 sw66;
RK_U32 dec_out_st_adr : 32; RK_U32 sw67;
}sw63; struct {
struct RK_U32 refbuf_sum_bot : 16;
{ RK_U32 refbuf_sum_top : 16;
RK_U32 rlc_vlc_st_adr : 32; } sw68;
}sw64; struct {
struct RK_U32 luma_sum_intra : 16;
{ RK_U32 refbuf_sum_hit : 16;
RK_U32 refbuf_y_offset : 9; } sw69;
RK_U32 reserve0 : 3; struct {
RK_U32 refbuf_fildpar_mode_e : 1; RK_U32 ycomp_mv_sum : 22;
RK_U32 refbuf_idcal_e : 1; RK_U32 reserve0 : 10;
RK_U32 refbuf_picid : 5; } sw70;
RK_U32 refbuf_thr_level : 12; RK_U32 sw71;
RK_U32 refbuf_e : 1; RK_U32 sw72;
}sw65; RK_U32 sw73;
RK_U32 sw66; struct {
RK_U32 sw67; RK_U32 init_reflist_pf4 : 5;
struct RK_U32 init_reflist_pf5 : 5;
{ RK_U32 init_reflist_pf6 : 5;
RK_U32 refbuf_sum_bot : 16; RK_U32 init_reflist_pf7 : 5;
RK_U32 refbuf_sum_top : 16; RK_U32 init_reflist_pf8 : 5;
}sw68; RK_U32 init_reflist_pf9 : 5;
struct RK_U32 reverse0 : 2;
{ } sw74;
RK_U32 luma_sum_intra : 16; struct {
RK_U32 refbuf_sum_hit : 16; RK_U32 init_reflist_pf10 : 5;
}sw69; RK_U32 init_reflist_pf11 : 5;
struct RK_U32 init_reflist_pf12 : 5;
{ RK_U32 init_reflist_pf13 : 5;
RK_U32 ycomp_mv_sum : 22; RK_U32 init_reflist_pf14 : 5;
RK_U32 reserve0 : 10; RK_U32 init_reflist_pf15 : 5;
}sw70; RK_U32 reverse0 : 2;
RK_U32 sw71; } sw75;
RK_U32 sw72; struct {
RK_U32 sw73; RK_U32 num_ref_idx0 : 16;
struct RK_U32 num_ref_idx1 : 16;
{ } sw76;
RK_U32 init_reflist_pf4 : 5; struct {
RK_U32 init_reflist_pf5 : 5; RK_U32 num_ref_idx2 : 16;
RK_U32 init_reflist_pf6 : 5; RK_U32 num_ref_idx3 : 16;
RK_U32 init_reflist_pf7 : 5; } sw77;
RK_U32 init_reflist_pf8 : 5; struct {
RK_U32 init_reflist_pf9 : 5; RK_U32 num_ref_idx4 : 16;
RK_U32 reverse0 : 2; RK_U32 num_ref_idx5 : 16;
}sw74; } sw78;
struct struct {
{ RK_U32 num_ref_idx6 : 16;
RK_U32 init_reflist_pf10 : 5; RK_U32 num_ref_idx7 : 16;
RK_U32 init_reflist_pf11 : 5; } sw79;
RK_U32 init_reflist_pf12 : 5; struct {
RK_U32 init_reflist_pf13 : 5; RK_U32 num_ref_idx8 : 16;
RK_U32 init_reflist_pf14 : 5; RK_U32 num_ref_idx9 : 16;
RK_U32 init_reflist_pf15 : 5; } sw80;
RK_U32 reverse0 : 2; struct {
}sw75; RK_U32 num_ref_idx10 : 16;
struct RK_U32 num_ref_idx11 : 16;
{ } sw81;
RK_U32 num_ref_idx0 : 16; struct {
RK_U32 num_ref_idx1 : 16; RK_U32 num_ref_idx12 : 16;
}sw76; RK_U32 num_ref_idx13 : 16;
struct } sw82;
{ struct {
RK_U32 num_ref_idx2 : 16; RK_U32 num_ref_idx14 : 16;
RK_U32 num_ref_idx3 : 16; RK_U32 num_ref_idx15 : 16;
}sw77; } sw83;
struct union {
{ RK_U32 ref0_st_addr;
RK_U32 num_ref_idx4 : 16; struct {
RK_U32 num_ref_idx5 : 16; RK_U32 ref0_closer_sel : 1;
}sw78; RK_U32 ref0_field_en : 1;
struct RK_U32 reverse0 : 30;
{ };
RK_U32 num_ref_idx6 : 16; } sw84;
RK_U32 num_ref_idx7 : 16; union {
}sw79; RK_U32 ref1_st_addr;
struct struct {
{ RK_U32 ref1_closer_sel : 1;
RK_U32 num_ref_idx8 : 16; RK_U32 ref1_field_en : 1;
RK_U32 num_ref_idx9 : 16; RK_U32 reverse0 : 30;
}sw80; };
struct } sw85;
{ union {
RK_U32 num_ref_idx10 : 16; RK_U32 ref2_st_addr;
RK_U32 num_ref_idx11 : 16; struct {
}sw81; RK_U32 ref2_closer_sel : 1;
struct RK_U32 ref2_field_en : 1;
{ RK_U32 reverse0 : 30;
RK_U32 num_ref_idx12 : 16; };
RK_U32 num_ref_idx13 : 16; } sw86;
}sw82; union {
struct RK_U32 ref3_st_addr;
{ struct {
RK_U32 num_ref_idx14 : 16; RK_U32 ref3_closer_sel : 1;
RK_U32 num_ref_idx15 : 16; RK_U32 ref3_field_en : 1;
}sw83; RK_U32 reverse0 : 30;
union };
{ } sw87;
RK_U32 ref0_st_addr; union {
struct RK_U32 ref4_st_addr;
{ struct {
RK_U32 ref0_closer_sel : 1; RK_U32 ref4_closer_sel : 1;
RK_U32 ref0_field_en : 1; RK_U32 ref4_field_en : 1;
RK_U32 reverse0 : 30; RK_U32 reverse0 : 30;
}; };
}sw84; } sw88;
union union {
{ RK_U32 ref5_st_addr;
RK_U32 ref1_st_addr; struct {
struct RK_U32 ref5_closer_sel : 1;
{ RK_U32 ref5_field_en : 1;
RK_U32 ref1_closer_sel : 1; RK_U32 reverse0 : 30;
RK_U32 ref1_field_en : 1; };
RK_U32 reverse0 : 30; } sw89;
}; union {
}sw85; RK_U32 ref6_st_addr;
union struct {
{ RK_U32 ref6_closer_sel : 1;
RK_U32 ref2_st_addr; RK_U32 ref6_field_en : 1;
struct RK_U32 reverse0 : 30;
{ };
RK_U32 ref2_closer_sel : 1; } sw90;
RK_U32 ref2_field_en : 1; union {
RK_U32 reverse0 : 30; RK_U32 ref7_st_addr;
}; struct {
}sw86; RK_U32 ref7_closer_sel : 1;
union RK_U32 ref7_field_en : 1;
{ RK_U32 reverse0 : 30;
RK_U32 ref3_st_addr; };
struct } sw91;
{ union {
RK_U32 ref3_closer_sel : 1; RK_U32 ref8_st_addr;
RK_U32 ref3_field_en : 1; struct {
RK_U32 reverse0 : 30; RK_U32 ref8_closer_sel : 1;
}; RK_U32 ref8_field_en : 1;
}sw87; RK_U32 reverse0 : 30;
union };
{ } sw92;
RK_U32 ref4_st_addr; union {
struct RK_U32 ref9_st_addr;
{ struct {
RK_U32 ref4_closer_sel : 1; RK_U32 ref9_closer_sel : 1;
RK_U32 ref4_field_en : 1; RK_U32 ref9_field_en : 1;
RK_U32 reverse0 : 30; RK_U32 reverse0 : 30;
}; };
}sw88; } sw93;
union union {
{ RK_U32 ref10_st_addr;
RK_U32 ref5_st_addr; struct {
struct RK_U32 ref10_closer_sel : 1;
{ RK_U32 ref10_field_en : 1;
RK_U32 ref5_closer_sel : 1; RK_U32 reverse0 : 30;
RK_U32 ref5_field_en : 1; };
RK_U32 reverse0 : 30; } sw94;
}; union {
}sw89; RK_U32 ref11_st_addr;
union struct {
{ RK_U32 ref11_closer_sel : 1;
RK_U32 ref6_st_addr; RK_U32 ref11_field_en : 1;
struct RK_U32 reverse0 : 30;
{ };
RK_U32 ref6_closer_sel : 1; } sw95;
RK_U32 ref6_field_en : 1; union {
RK_U32 reverse0 : 30; RK_U32 ref12_st_addr;
}; struct {
}sw90; RK_U32 ref12_closer_sel : 1;
union RK_U32 ref12_field_en : 1;
{ RK_U32 reverse0 : 30;
RK_U32 ref7_st_addr; };
struct } sw96;
{ union {
RK_U32 ref7_closer_sel : 1; RK_U32 ref13_st_addr;
RK_U32 ref7_field_en : 1; struct {
RK_U32 reverse0 : 30; RK_U32 ref13_closer_sel : 1;
}; RK_U32 ref13_field_en : 1;
}sw91; RK_U32 reverse0 : 30;
union };
{ } sw97;
RK_U32 ref8_st_addr; union {
struct RK_U32 ref14_st_addr;
{ struct {
RK_U32 ref8_closer_sel : 1; RK_U32 ref14_closer_sel : 1;
RK_U32 ref8_field_en : 1; RK_U32 ref14_field_en : 1;
RK_U32 reverse0 : 30; RK_U32 reverse0 : 30;
}; };
}sw92; } sw98;
union union {
{ RK_U32 ref15_st_addr;
RK_U32 ref9_st_addr; struct {
struct RK_U32 ref15_closer_sel : 1;
{ RK_U32 ref15_field_en : 1;
RK_U32 ref9_closer_sel : 1; RK_U32 reverse0 : 30;
RK_U32 ref9_field_en : 1; };
RK_U32 reverse0 : 30; } sw99;
}; struct {
}sw93; RK_U32 init_reflist_df0 : 5;
union RK_U32 init_reflist_df1 : 5;
{ RK_U32 init_reflist_df2 : 5;
RK_U32 ref10_st_addr; RK_U32 init_reflist_df3 : 5;
struct RK_U32 init_reflist_df4 : 5;
{ RK_U32 init_reflist_df5 : 5;
RK_U32 ref10_closer_sel : 1; RK_U32 reverse0 : 2;
RK_U32 ref10_field_en : 1; } sw100;
RK_U32 reverse0 : 30; struct {
}; RK_U32 init_reflist_df6 : 5;
}sw94; RK_U32 init_reflist_df7 : 5;
union RK_U32 init_reflist_df8 : 5;
{ RK_U32 init_reflist_df9 : 5;
RK_U32 ref11_st_addr; RK_U32 init_reflist_df10 : 5;
struct RK_U32 init_reflist_df11 : 5;
{ RK_U32 reverse0 : 2;
RK_U32 ref11_closer_sel : 1; } sw101;
RK_U32 ref11_field_en : 1; struct {
RK_U32 reverse0 : 30; RK_U32 init_reflist_df12 : 5;
}; RK_U32 init_reflist_df13 : 5;
}sw95; RK_U32 init_reflist_df14 : 5;
union RK_U32 init_reflist_df15 : 5;
{ RK_U32 reverse0 : 12;
RK_U32 ref12_st_addr; } sw102;
struct struct {
{ RK_U32 init_reflist_db0 : 5;
RK_U32 ref12_closer_sel : 1; RK_U32 init_reflist_db1 : 5;
RK_U32 ref12_field_en : 1; RK_U32 init_reflist_db2 : 5;
RK_U32 reverse0 : 30; RK_U32 init_reflist_db3 : 5;
}; RK_U32 init_reflist_db4 : 5;
}sw96; RK_U32 init_reflist_db5 : 5;
union RK_U32 reverse0 : 2;
{ } sw103;
RK_U32 ref13_st_addr; struct {
struct RK_U32 init_reflist_db6 : 5;
{ RK_U32 init_reflist_db7 : 5;
RK_U32 ref13_closer_sel : 1; RK_U32 init_reflist_db8 : 5;
RK_U32 ref13_field_en : 1; RK_U32 init_reflist_db9 : 5;
RK_U32 reverse0 : 30; RK_U32 init_reflist_db10 : 5;
}; RK_U32 init_reflist_db11 : 5;
}sw97; RK_U32 reverse0 : 2;
union } sw104;
{ struct {
RK_U32 ref14_st_addr; RK_U32 init_reflist_db12 : 5;
struct RK_U32 init_reflist_db13 : 5;
{ RK_U32 init_reflist_db14 : 5;
RK_U32 ref14_closer_sel : 1; RK_U32 init_reflist_db15 : 5;
RK_U32 ref14_field_en : 1; RK_U32 reverse0 : 12;
RK_U32 reverse0 : 30; } sw105;
}; struct {
}sw98; RK_U32 init_reflist_pf0 : 5;
union RK_U32 init_reflist_pf1 : 5;
{ RK_U32 init_reflist_pf2 : 5;
RK_U32 ref15_st_addr; RK_U32 init_reflist_pf3 : 5;
struct RK_U32 reverse0 : 12;
{ } sw106;
RK_U32 ref15_closer_sel : 1; struct {
RK_U32 ref15_field_en : 1; RK_U32 refpic_term_flag : 32;
RK_U32 reverse0 : 30; } sw107;
}; struct {
}sw99; RK_U32 refpic_valid_flag : 32;
struct } sw108;
{ struct {
RK_U32 init_reflist_df0 : 5; RK_U32 strm_start_bit : 6;
RK_U32 init_reflist_df1 : 5; RK_U32 reverse0 : 26;
RK_U32 init_reflist_df2 : 5; } sw109;
RK_U32 init_reflist_df3 : 5; struct {
RK_U32 init_reflist_df4 : 5; RK_U32 pic_mb_w : 9;
RK_U32 init_reflist_df5 : 5; RK_U32 pic_mb_h : 8;
RK_U32 reverse0 : 2; RK_U32 flt_offset_cb_qp : 5;
}sw100; RK_U32 flt_offset_cr_qp : 5;
struct RK_U32 reverse0 : 5;
{ } sw110;
RK_U32 init_reflist_df6 : 5; struct {
RK_U32 init_reflist_df7 : 5; RK_U32 max_refnum : 5;
RK_U32 init_reflist_df8 : 5; RK_U32 reverse0 : 11;
RK_U32 init_reflist_df9 : 5; RK_U32 wp_bslice_sel : 2;
RK_U32 init_reflist_df10 : 5; RK_U32 reverse1 : 14;
RK_U32 init_reflist_df11 : 5; } sw111;
RK_U32 reverse0 : 2; struct {
}sw101; RK_U32 curfrm_num : 16;
struct RK_U32 cur_frm_len : 5;
{ RK_U32 reverse0 : 9;
RK_U32 init_reflist_df12 : 5; RK_U32 rpcp_flag : 1;
RK_U32 init_reflist_df13 : 5; RK_U32 dblk_ctrl_flag : 1;
RK_U32 init_reflist_df14 : 5; } sw112;
RK_U32 init_reflist_df15 : 5; struct {
RK_U32 reverse0 : 12; RK_U32 idr_pic_id : 16;
}sw102; RK_U32 refpic_mk_len : 11;
struct RK_U32 reverse0 : 5;
{ } sw113;
RK_U32 init_reflist_db0 : 5; struct {
RK_U32 init_reflist_db1 : 5; RK_U32 poc_field_len : 8;
RK_U32 init_reflist_db2 : 5; RK_U32 reverse0 : 6;
RK_U32 init_reflist_db3 : 5; RK_U32 max_refidx0 : 5;
RK_U32 init_reflist_db4 : 5; RK_U32 max_refidx1 : 5;
RK_U32 init_reflist_db5 : 5; RK_U32 pps_id : 5;
RK_U32 reverse0 : 2; } sw114;
}sw103; struct {
struct RK_U32 fieldpic_flag_exist : 1;
{ RK_U32 scl_matrix_en : 1;
RK_U32 init_reflist_db6 : 5; RK_U32 tranf_8x8_flag_en : 1;
RK_U32 init_reflist_db7 : 5; RK_U32 const_intra_en : 1;
RK_U32 init_reflist_db8 : 5; RK_U32 weight_pred_en : 1;
RK_U32 init_reflist_db9 : 5; RK_U32 cabac_en : 1;
RK_U32 init_reflist_db10 : 5; RK_U32 monochr_en : 1;
RK_U32 init_reflist_db11 : 5; RK_U32 dlmv_method_en : 1;
RK_U32 reverse0 : 2; RK_U32 idr_pic_flag : 1;
}sw104; RK_U32 reverse0 : 23;
struct } sw115;
{ RK_U32 sw116_158[43];
RK_U32 init_reflist_db12 : 5; } H264dVdpuRegs_t;
RK_U32 init_reflist_db13 : 5;
RK_U32 init_reflist_db14 : 5;
RK_U32 init_reflist_db15 : 5;
RK_U32 reverse0 : 12;
}sw105;
struct
{
RK_U32 init_reflist_pf0 : 5;
RK_U32 init_reflist_pf1 : 5;
RK_U32 init_reflist_pf2 : 5;
RK_U32 init_reflist_pf3 : 5;
RK_U32 reverse0 : 12;
}sw106;
struct
{
RK_U32 refpic_term_flag : 32;
}sw107;
struct
{
RK_U32 refpic_valid_flag : 32;
}sw108;
struct
{
RK_U32 strm_start_bit : 6;
RK_U32 reverse0 : 26;
}sw109;
struct
{
RK_U32 pic_mb_w : 9;
RK_U32 pic_mb_h : 8;
RK_U32 flt_offset_cb_qp : 5;
RK_U32 flt_offset_cr_qp : 5;
RK_U32 reverse0 : 5;
}sw110;
struct
{
RK_U32 max_refnum : 5;
RK_U32 reverse0 : 11;
RK_U32 wp_bslice_sel : 2;
RK_U32 reverse1 : 14;
}sw111;
struct
{
RK_U32 curfrm_num : 16;
RK_U32 cur_frm_len : 5;
RK_U32 reverse0 : 9;
RK_U32 rpcp_flag : 1;
RK_U32 dblk_ctrl_flag : 1;
}sw112;
struct
{
RK_U32 idr_pic_id : 16;
RK_U32 refpic_mk_len : 11;
RK_U32 reverse0 : 5;
}sw113;
struct
{
RK_U32 poc_field_len : 8;
RK_U32 reverse0 : 6;
RK_U32 max_refidx0 : 5;
RK_U32 max_refidx1 : 5;
RK_U32 pps_id : 5;
}sw114;
struct
{
RK_U32 fieldpic_flag_exist : 1;
RK_U32 scl_matrix_en : 1;
RK_U32 tranf_8x8_flag_en : 1;
RK_U32 const_intra_en : 1;
RK_U32 weight_pred_en : 1;
RK_U32 cabac_en : 1;
RK_U32 monochr_en : 1;
RK_U32 dlmv_method_en : 1;
RK_U32 idr_pic_flag : 1;
RK_U32 reverse0 : 23;
}sw115;
RK_U32 sw116_158[43];
}H264dVdpuRegs_t;
/* Number registers for the decoder */ /* Number registers for the decoder */

179
mpp/hal/rkdec/h264d/hal_h264d_vdpu_reg.c
View File

@@ -37,56 +37,56 @@
static RK_U32 vdpu_ver_align(RK_U32 val) static RK_U32 vdpu_ver_align(RK_U32 val)
{ {
return MPP_ALIGN(val, 16); return MPP_ALIGN(val, 16);
} }
static RK_U32 vdpu_hor_align(RK_U32 val) static RK_U32 vdpu_hor_align(RK_U32 val)
{ {
return MPP_ALIGN(val, 16); return MPP_ALIGN(val, 16);
} }
static MPP_RET vdpu_set_device_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_reg) static MPP_RET vdpu_set_device_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_reg)
{ {
MPP_RET ret = MPP_ERR_UNKNOW; MPP_RET ret = MPP_ERR_UNKNOW;
p_reg->sw53.dec_fmt_sel = 0; //!< set H264 mode p_reg->sw53.dec_fmt_sel = 0; //!< set H264 mode
p_reg->sw54.dec_out_endian = 1; //!< little endian p_reg->sw54.dec_out_endian = 1; //!< little endian
p_reg->sw54.dec_in_endian = 0; //!< big endian p_reg->sw54.dec_in_endian = 0; //!< big endian
p_reg->sw54.dec_strendian_e = 1; //!< little endian p_reg->sw54.dec_strendian_e = 1; //!< little endian
p_reg->sw50.dec_tiled_msb = 0; //!< 0: raster scan 1: tiled p_reg->sw50.dec_tiled_msb = 0; //!< 0: raster scan 1: tiled
p_reg->sw56.dec_max_burlen = 16; //!< (0, 4, 8, 16) choice one p_reg->sw56.dec_max_burlen = 16; //!< (0, 4, 8, 16) choice one
p_reg->sw50.dec_ascmd0_dis = 0; //!< disable p_reg->sw50.dec_ascmd0_dis = 0; //!< disable
p_reg->sw50.adv_pref_dis = 0; //!< disable p_reg->sw50.adv_pref_dis = 0; //!< disable
p_reg->sw52.adv_pref_thrd = 8; p_reg->sw52.adv_pref_thrd = 8;
p_reg->sw50.adtion_latency = 0; //!< compensation for bus latency; values up to 63 p_reg->sw50.adtion_latency = 0; //!< compensation for bus latency; values up to 63
p_reg->sw56.dec_data_discd_en = 0; p_reg->sw56.dec_data_discd_en = 0;
p_reg->sw54.dec_out_wordsp = 1;//!< little endian p_reg->sw54.dec_out_wordsp = 1;//!< little endian
p_reg->sw54.dec_in_wordsp = 1;//!< little endian p_reg->sw54.dec_in_wordsp = 1;//!< little endian
p_reg->sw54.dec_strm_wordsp = 1;//!< little endian p_reg->sw54.dec_strm_wordsp = 1;//!< little endian
p_reg->sw57.timeout_sts_en = 1; p_reg->sw57.timeout_sts_en = 1;
p_reg->sw57.dec_clkgate_en = 1; p_reg->sw57.dec_clkgate_en = 1;
p_reg->sw55.dec_irq_dis = 0; p_reg->sw55.dec_irq_dis = 0;
//!< set AXI RW IDs //!< set AXI RW IDs
p_reg->sw56.dec_axi_id_rd = (0xFF & 0xFFU); //!< 0-255 p_reg->sw56.dec_axi_id_rd = (0xFF & 0xFFU); //!< 0-255
p_reg->sw56.dec_axi_id_wr = (0x0 & 0xFFU); //!< 0-255 p_reg->sw56.dec_axi_id_wr = (0x0 & 0xFFU); //!< 0-255
///!< Set prediction filter taps ///!< Set prediction filter taps
{ {
RK_U32 val = 0; RK_U32 val = 0;
p_reg->sw59.pflt_set0_tap0 = 1; p_reg->sw59.pflt_set0_tap0 = 1;
val = (RK_U32)(-5); val = (RK_U32)(-5);
p_reg->sw59.pflt_set0_tap1 = val; p_reg->sw59.pflt_set0_tap1 = val;
p_reg->sw59.pflt_set0_tap2 = 20; p_reg->sw59.pflt_set0_tap2 = 20;
} }
p_reg->sw50.adtion_latency = 0; p_reg->sw50.adtion_latency = 0;
//!< clock_gating 0:clock always on, 1: clock gating module control the key(turn off when decoder free) //!< clock_gating 0:clock always on, 1: clock gating module control the key(turn off when decoder free)
p_reg->sw57.dec_clkgate_en = 1; p_reg->sw57.dec_clkgate_en = 1;
p_reg->sw50.dec_tiled_msb = 0; //!< 0: raster scan 1: tiled p_reg->sw50.dec_tiled_msb = 0; //!< 0: raster scan 1: tiled
//!< bus_burst_length = 16, bus burst //!< bus_burst_length = 16, bus burst
p_reg->sw56.dec_max_burlen = 16; p_reg->sw56.dec_max_burlen = 16;
p_reg->sw56.dec_data_discd_en = 0; p_reg->sw56.dec_data_discd_en = 0;
(void)p_hal; (void)p_hal;
return ret = MPP_OK; return ret = MPP_OK;
} }
static MPP_RET vdpu_get_info_input(H264dHalCtx_t *p_hal, H264dVdpuPriv_t *priv) static MPP_RET vdpu_get_info_input(H264dHalCtx_t *p_hal, H264dVdpuPriv_t *priv)
@@ -108,8 +108,7 @@ static MPP_RET vdpu_get_info_input(H264dHalCtx_t *p_hal, H264dVdpuPriv_t *priv)
priv->new_dpb[i].BOT_POC = pp->FieldOrderCntList[i][1]; priv->new_dpb[i].BOT_POC = pp->FieldOrderCntList[i][1];
if (priv->new_dpb[i].is_long_term) { if (priv->new_dpb[i].is_long_term) {
priv->new_dpb[i].long_term_frame_idx = pp->FrameNumList[i]; priv->new_dpb[i].long_term_frame_idx = pp->FrameNumList[i];
} } else {
else {
priv->new_dpb[i].frame_num = pp->FrameNumList[i]; priv->new_dpb[i].frame_num = pp->FrameNumList[i];
} }
priv->new_dpb[i].long_term_pic_num = pp->LongTermPicNumList[i]; priv->new_dpb[i].long_term_pic_num = pp->LongTermPicNumList[i];
@@ -213,8 +212,7 @@ static MPP_RET vdpu_refill_info_input(H264dHalCtx_t *p_hal, H264dVdpuPriv_t *pri
for (i = 0; i < MPP_ARRAY_ELEMS(p_long->RefPicList[j]); i++) { for (i = 0; i < MPP_ARRAY_ELEMS(p_long->RefPicList[j]); i++) {
if (p[i].valid) { if (p[i].valid) {
fill_picture_entry(&p_long->RefPicList[j][i], p[i].dpb_idx, p[i].bottom_flag); fill_picture_entry(&p_long->RefPicList[j][i], p[i].dpb_idx, p[i].bottom_flag);
} } else {
else {
p_long->RefPicList[j][i].bPicEntry = 0xff; p_long->RefPicList[j][i].bPicEntry = 0xff;
} }
} }
@@ -312,32 +310,32 @@ static MPP_RET vdpu_adjust_input(H264dHalCtx_t *p_hal, H264dVdpuPriv_t *priv)
//extern "C" //extern "C"
MPP_RET vdpu_h264d_init(void *hal, MppHalCfg *cfg) MPP_RET vdpu_h264d_init(void *hal, MppHalCfg *cfg)
{ {
RK_U32 cabac_size = 0; RK_U32 cabac_size = 0;
MPP_RET ret = MPP_ERR_UNKNOW; MPP_RET ret = MPP_ERR_UNKNOW;
H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
INP_CHECK(ret, NULL == hal); INP_CHECK(ret, NULL == hal);
//!< malloc init registers //!< malloc init registers
MEM_CHECK(ret, p_hal->regs = mpp_calloc_size(void, sizeof(H264dVdpuRegs_t))); MEM_CHECK(ret, p_hal->regs = mpp_calloc_size(void, sizeof(H264dVdpuRegs_t)));
MEM_CHECK(ret, p_hal->priv = mpp_calloc_size(void, sizeof(H264dVdpuPriv_t))); MEM_CHECK(ret, p_hal->priv = mpp_calloc_size(void, sizeof(H264dVdpuPriv_t)));
//!< malloc cabac+scanlis + packets + poc_buf //!< malloc cabac+scanlis + packets + poc_buf
cabac_size = VDPU_CABAC_TAB_SIZE + VDPU_SCALING_LIST_SIZE + VDPU_POC_BUF_SIZE; cabac_size = VDPU_CABAC_TAB_SIZE + VDPU_SCALING_LIST_SIZE + VDPU_POC_BUF_SIZE;
FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, &p_hal->cabac_buf, cabac_size)); FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, &p_hal->cabac_buf, cabac_size));
//!< copy cabac table bytes //!< copy cabac table bytes
FUN_CHECK(ret = mpp_buffer_write(p_hal->cabac_buf, 0, (void *)H264_VDPU_Cabac_table, sizeof(H264_VDPU_Cabac_table))); FUN_CHECK(ret = mpp_buffer_write(p_hal->cabac_buf, 0, (void *)H264_VDPU_Cabac_table, sizeof(H264_VDPU_Cabac_table)));
FUN_CHECK(ret = vdpu_set_device_regs(p_hal, (H264dVdpuRegs_t *)p_hal->regs)); FUN_CHECK(ret = vdpu_set_device_regs(p_hal, (H264dVdpuRegs_t *)p_hal->regs));
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, vdpu_hor_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, vdpu_hor_align);
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, vdpu_ver_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, vdpu_ver_align);
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, NULL); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, NULL);
p_hal->iDecodedNum = 0; p_hal->iDecodedNum = 0;
(void)cfg; (void)cfg;
__RETURN: __RETURN:
return MPP_OK; return MPP_OK;
__FAILED: __FAILED:
vdpu_h264d_deinit(hal); vdpu_h264d_deinit(hal);
return ret; return ret;
} }
@@ -353,15 +351,15 @@ MPP_RET vdpu_h264d_deinit(void *hal)
MPP_RET ret = MPP_ERR_UNKNOW; MPP_RET ret = MPP_ERR_UNKNOW;
H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
INP_CHECK(ret, NULL == p_hal); INP_CHECK(ret, NULL == p_hal);
FunctionIn(p_hal->logctx.parr[RUN_HAL]); FunctionIn(p_hal->logctx.parr[RUN_HAL]);
MPP_FREE(p_hal->regs); MPP_FREE(p_hal->regs);
MPP_FREE(p_hal->priv); MPP_FREE(p_hal->priv);
if (p_hal->cabac_buf) { if (p_hal->cabac_buf) {
FUN_CHECK(ret = mpp_buffer_put(p_hal->cabac_buf)); FUN_CHECK(ret = mpp_buffer_put(p_hal->cabac_buf));
} }
FunctionOut(p_hal->logctx.parr[RUN_HAL]); FunctionOut(p_hal->logctx.parr[RUN_HAL]);
__RETURN: __RETURN:
@@ -384,7 +382,7 @@ MPP_RET vdpu_h264d_gen_regs(void *hal, HalTaskInfo *task)
INP_CHECK(ret, NULL == p_hal); INP_CHECK(ret, NULL == p_hal);
FunctionIn(p_hal->logctx.parr[RUN_HAL]); FunctionIn(p_hal->logctx.parr[RUN_HAL]);
p_hal->in_task = &task->dec; p_hal->in_task = &task->dec;
if (task->dec.flags.had_error) { if (task->dec.flags.had_error) {
goto __RETURN; goto __RETURN;
} }
LogTrace(p_hal->logctx.parr[RUN_HAL], "[Generate register begin]"); LogTrace(p_hal->logctx.parr[RUN_HAL], "[Generate register begin]");
@@ -392,7 +390,7 @@ MPP_RET vdpu_h264d_gen_regs(void *hal, HalTaskInfo *task)
FUN_CHECK(ret = vdpu_set_pic_regs(p_hal, (H264dVdpuRegs_t *)p_hal->regs)); FUN_CHECK(ret = vdpu_set_pic_regs(p_hal, (H264dVdpuRegs_t *)p_hal->regs));
FUN_CHECK(ret = vdpu_set_vlc_regs(p_hal, (H264dVdpuRegs_t *)p_hal->regs)); FUN_CHECK(ret = vdpu_set_vlc_regs(p_hal, (H264dVdpuRegs_t *)p_hal->regs));
FUN_CHECK(ret = vdpu_set_ref_regs(p_hal, (H264dVdpuRegs_t *)p_hal->regs)); FUN_CHECK(ret = vdpu_set_ref_regs(p_hal, (H264dVdpuRegs_t *)p_hal->regs));
FUN_CHECK(ret = vdpu_set_asic_regs(p_hal,(H264dVdpuRegs_t *)p_hal->regs)); FUN_CHECK(ret = vdpu_set_asic_regs(p_hal, (H264dVdpuRegs_t *)p_hal->regs));
LogTrace(p_hal->logctx.parr[RUN_HAL], "[Generate register end]"); LogTrace(p_hal->logctx.parr[RUN_HAL], "[Generate register end]");
p_hal->in_task->valid = 0; p_hal->in_task->valid = 0;
FunctionOut(p_hal->logctx.parr[RUN_HAL]); FunctionOut(p_hal->logctx.parr[RUN_HAL]);
@@ -414,7 +412,7 @@ MPP_RET vdpu_h264d_start(void *hal, HalTaskInfo *task)
H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
H264dVdpuRegs_t *p_regs = (H264dVdpuRegs_t *)p_hal->regs; H264dVdpuRegs_t *p_regs = (H264dVdpuRegs_t *)p_hal->regs;
FunctionIn(p_hal->logctx.parr[RUN_HAL]); FunctionIn(p_hal->logctx.parr[RUN_HAL]);
if (task->dec.flags.had_error) { if (task->dec.flags.had_error) {
goto __RETURN; goto __RETURN;
} }
@@ -427,11 +425,10 @@ MPP_RET vdpu_h264d_start(void *hal, HalTaskInfo *task)
#ifdef RKPLATFORM #ifdef RKPLATFORM
if (VPUClientSendReg(p_hal->vpu_socket, (RK_U32 *)p_hal->regs, DEC_VDPU_REGISTERS)) { if (VPUClientSendReg(p_hal->vpu_socket, (RK_U32 *)p_hal->regs, DEC_VDPU_REGISTERS)) {
ret = MPP_ERR_VPUHW; ret = MPP_ERR_VPUHW;
mpp_err_f("H264 VDPU FlushRegs fail, pid=%d, hal_frame_no=%d. \n", getpid(), p_hal->iDecodedNum); mpp_err_f("H264 VDPU FlushRegs fail, pid=%d, hal_frame_no=%d. \n", getpid(), p_hal->iDecodedNum);
} } else {
else { H264D_LOG("H264 VDPU FlushRegs success, pid=%d, hal_frame_no=%d. \n", getpid(), p_hal->iDecodedNum);
H264D_LOG("H264 VDPU FlushRegs success, pid=%d, hal_frame_no=%d. \n", getpid(), p_hal->iDecodedNum); }
}
#endif #endif
__RETURN: __RETURN:
FunctionOut(p_hal->logctx.parr[RUN_HAL]); FunctionOut(p_hal->logctx.parr[RUN_HAL]);
@@ -449,27 +446,27 @@ MPP_RET vdpu_h264d_wait(void *hal, HalTaskInfo *task)
{ {
MPP_RET ret = MPP_ERR_UNKNOW; MPP_RET ret = MPP_ERR_UNKNOW;
H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
H264dVdpuRegs_t *p_regs = (H264dVdpuRegs_t *)p_hal->regs; H264dVdpuRegs_t *p_regs = (H264dVdpuRegs_t *)p_hal->regs;
FunctionIn(p_hal->logctx.parr[RUN_HAL]); FunctionIn(p_hal->logctx.parr[RUN_HAL]);
if (task->dec.flags.had_error) { if (task->dec.flags.had_error) {
goto __SKIP_HARD; goto __SKIP_HARD;
} }
#ifdef RKPLATFORM #ifdef RKPLATFORM
{ {
RK_S32 wait_ret = -1; RK_S32 wait_ret = -1;
RK_S32 ret_len = 0, cur_deat = 0; RK_S32 ret_len = 0, cur_deat = 0;
VPU_CMD_TYPE ret_cmd = VPU_CMD_BUTT; VPU_CMD_TYPE ret_cmd = VPU_CMD_BUTT;
RK_S64 p_s, p_e; RK_S64 p_s, p_e;
p_s = mpp_time(); p_s = mpp_time();
wait_ret = VPUClientWaitResult(p_hal->vpu_socket, (RK_U32 *)p_hal->regs, DEC_VDPU_REGISTERS, &ret_cmd, &ret_len); wait_ret = VPUClientWaitResult(p_hal->vpu_socket, (RK_U32 *)p_hal->regs, DEC_VDPU_REGISTERS, &ret_cmd, &ret_len);
p_e = mpp_time(); p_e = mpp_time();
cur_deat = (p_e - p_s) / 1000; cur_deat = (p_e - p_s) / 1000;
p_hal->total_time += cur_deat; p_hal->total_time += cur_deat;
p_hal->iDecodedNum++; p_hal->iDecodedNum++;
(void)wait_ret; (void)wait_ret;
} }
#endif #endif
__SKIP_HARD: __SKIP_HARD:
@@ -483,7 +480,7 @@ __SKIP_HARD:
m_ctx.regs = (RK_U32 *)p_hal->regs; m_ctx.regs = (RK_U32 *)p_hal->regs;
p_hal->init_cb.callBack(p_hal->init_cb.opaque, &m_ctx); p_hal->init_cb.callBack(p_hal->init_cb.opaque, &m_ctx);
} }
memset(&p_regs->sw55, 0, sizeof(RK_U32)); memset(&p_regs->sw55, 0, sizeof(RK_U32));
FunctionOut(p_hal->logctx.parr[RUN_HAL]); FunctionOut(p_hal->logctx.parr[RUN_HAL]);
(void)task; (void)task;

8
mpp/hal/vpu/h263d/hal_h263d_reg.h
View File

@@ -116,10 +116,10 @@ typedef struct {
RK_U32 sw_dec_ahb_hlock_e : 1; RK_U32 sw_dec_ahb_hlock_e : 1;
} reg57_enable_ctrl; } reg57_enable_ctrl;
struct { struct {
RK_U32 sw_soft_rst : 1; RK_U32 sw_soft_rst : 1;
RK_U32 reverse0 : 31; RK_U32 reverse0 : 31;
} reg58; } reg58;
struct { struct {
RK_U32 reserve : 2; RK_U32 reserve : 2;

8
mpp/hal/vpu/mpg4d/hal_mpg4d_reg.h
View File

@@ -116,10 +116,10 @@ typedef struct {
RK_U32 sw_dec_ahb_hlock_e : 1; RK_U32 sw_dec_ahb_hlock_e : 1;
} reg57_enable_ctrl; } reg57_enable_ctrl;
struct { struct {
RK_U32 sw_soft_rst : 1; RK_U32 sw_soft_rst : 1;
RK_U32 reverse0 : 31; RK_U32 reverse0 : 31;
} reg58; } reg58;
struct { struct {
RK_U32 reserve : 2; RK_U32 reserve : 2;

6
mpp/legacy/vpu_api.cpp
View File

@@ -203,8 +203,7 @@ public:
VpulibDlsym() VpulibDlsym()
: rkapi_hdl(NULL), : rkapi_hdl(NULL),
rkvpu_open_cxt(NULL), rkvpu_open_cxt(NULL),
rkvpu_close_cxt(NULL) rkvpu_close_cxt(NULL) {
{
if (!!access("/dev/rkvdec", F_OK)) { if (!!access("/dev/rkvdec", F_OK)) {
rkapi_hdl = dlopen("/system/lib/librk_on2.so", RTLD_LAZY); rkapi_hdl = dlopen("/system/lib/librk_on2.so", RTLD_LAZY);
} }
@@ -220,8 +219,7 @@ public:
} }
} }
~VpulibDlsym() ~VpulibDlsym() {
{
if (rkapi_hdl) { if (rkapi_hdl) {
dlclose(rkapi_hdl); dlclose(rkapi_hdl);
mpp_log("dlclose vpu lib"); mpp_log("dlclose vpu lib");

3
mpp/legacy/vpu_api_legacy.cpp
View File

@@ -386,8 +386,7 @@ RK_S32 VpuApiLegacy::control(VpuCodecContext *ctx, VPU_API_CMD cmd, void *param)
ImgWidth = ((p->ImgWidth & 0xFFFF) * 10) >> 3; ImgWidth = ((p->ImgWidth & 0xFFFF) * 10) >> 3;
p->CodecType = (p->ImgWidth & 0x40000000) ? MPP_FMT_YUV422SP_10BIT : MPP_FMT_YUV420SP_10BIT; p->CodecType = (p->ImgWidth & 0x40000000) ? MPP_FMT_YUV422SP_10BIT : MPP_FMT_YUV420SP_10BIT;
} } else {
else {
ImgWidth = (p->ImgWidth & 0xFFFF); ImgWidth = (p->ImgWidth & 0xFFFF);
p->CodecType = (p->ImgWidth & 0x40000000) ? MPP_FMT_YUV422SP : MPP_FMT_YUV420SP; p->CodecType = (p->ImgWidth & 0x40000000) ? MPP_FMT_YUV422SP : MPP_FMT_YUV420SP;
} }

4
mpp/mpp.cpp
View File

@@ -302,8 +302,8 @@ MPP_RET Mpp::control(MpiCmd cmd, MppParam param)
} }
case MPP_DEC_SET_INTERNAL_PTS_ENABLE: { case MPP_DEC_SET_INTERNAL_PTS_ENABLE: {
if (mType == MPP_CTX_DEC && if (mType == MPP_CTX_DEC &&
(mCoding == MPP_VIDEO_CodingMPEG2 || (mCoding == MPP_VIDEO_CodingMPEG2 ||
mCoding == MPP_VIDEO_CodingMPEG4)) { mCoding == MPP_VIDEO_CodingMPEG4)) {
mpp_dec_control(mDec, cmd, param); mpp_dec_control(mDec, cmd, param);
} else { } else {
mpp_err("type %x coding %x does not support use internal pts control\n"); mpp_err("type %x coding %x does not support use internal pts control\n");

12
osal/inc/mpp_thread.h
View File

@@ -207,26 +207,22 @@ public:
void start(); void start();
void stop(); void stop();
void lock(MppThreadSignal id = THREAD_WORK) void lock(MppThreadSignal id = THREAD_WORK) {
{
mpp_assert(id < THREAD_SIGNAL_BUTT); mpp_assert(id < THREAD_SIGNAL_BUTT);
mMutexCond[id].lock(); mMutexCond[id].lock();
} }
void unlock(MppThreadSignal id = THREAD_WORK) void unlock(MppThreadSignal id = THREAD_WORK) {
{
mpp_assert(id < THREAD_SIGNAL_BUTT); mpp_assert(id < THREAD_SIGNAL_BUTT);
mMutexCond[id].unlock(); mMutexCond[id].unlock();
} }
void wait(MppThreadSignal id = THREAD_WORK) void wait(MppThreadSignal id = THREAD_WORK) {
{
mpp_assert(id < THREAD_SIGNAL_BUTT); mpp_assert(id < THREAD_SIGNAL_BUTT);
mMutexCond[id].wait(); mMutexCond[id].wait();
} }
void signal(MppThreadSignal id = THREAD_WORK) void signal(MppThreadSignal id = THREAD_WORK) {
{
mpp_assert(id < THREAD_SIGNAL_BUTT); mpp_assert(id < THREAD_SIGNAL_BUTT);
mMutexCond[id].signal(); mMutexCond[id].signal();
} }