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fix[av1d]: Fix av1d ref stride error

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Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
Change-Id: I6511c88a445f211c8171bfd108856e87310f8a44
This commit is contained in:
Chandler Chen
2024-03-13 11:02:59 +08:00
committed by Herman Chen
parent be2dfdbd0a
commit 31e9d148b6
1 changed files with 11 additions and 10 deletions
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21
mpp/hal/vpu/av1d/hal_av1d_vdpu383.c
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@@ -2232,22 +2232,20 @@ MPP_RET vdpu383_av1d_gen_regs(void *hal, HalTaskInfo *task)
regs->av1d_paras.reg68_hor_virstride = MPP_ALIGN(hor_virstride, 64) / 64; regs->av1d_paras.reg68_hor_virstride = MPP_ALIGN(hor_virstride, 64) / 64;
fbd_offset = regs->av1d_paras.reg68_hor_virstride * MPP_ALIGN(ver_virstride, 8) * 4; fbd_offset = regs->av1d_paras.reg68_hor_virstride * MPP_ALIGN(ver_virstride, 8) * 4;
regs->av1d_addrs.reg193_fbc_payload_offset = fbd_offset; regs->av1d_addrs.reg193_fbc_payload_offset = fbd_offset;
regs->av1d_paras.reg80_error_ref_hor_virstride = regs->av1d_paras.reg68_hor_virstride;
} else if (MPP_FRAME_FMT_IS_TILE(mpp_frame_get_fmt(mframe))) { } else if (MPP_FRAME_FMT_IS_TILE(mpp_frame_get_fmt(mframe))) {
regs->ctrl_regs.reg9.tile_e = 1; regs->ctrl_regs.reg9.tile_e = 1;
regs->av1d_paras.reg68_hor_virstride = hor_virstride * 6 / 16; regs->av1d_paras.reg68_hor_virstride = MPP_ALIGN(hor_virstride * 6, 16) >> 4;
regs->av1d_paras.reg70_y_virstride = (y_virstride + uv_virstride) / 16; regs->av1d_paras.reg70_y_virstride = (y_virstride + uv_virstride) >> 4;
regs->av1d_paras.reg80_error_ref_hor_virstride = hor_virstride >> 4;
} else { } else {
regs->ctrl_regs.reg9.fbc_e = 0; regs->ctrl_regs.reg9.fbc_e = 0;
regs->av1d_paras.reg68_hor_virstride = hor_virstride >> 4; regs->av1d_paras.reg68_hor_virstride = hor_virstride >> 4;
regs->av1d_paras.reg69_raster_uv_hor_virstride = hor_virstride >> 4; regs->av1d_paras.reg69_raster_uv_hor_virstride = hor_virstride >> 4;
regs->av1d_paras.reg70_y_virstride = y_virstride >> 4; regs->av1d_paras.reg70_y_virstride = y_virstride >> 4;
regs->av1d_paras.reg80_error_ref_hor_virstride = hor_virstride >> 4;
} }
/* error */ /* error */
regs->av1d_paras.reg81_error_ref_raster_uv_hor_virstride = hor_virstride >> 4; regs->av1d_paras.reg80_error_ref_hor_virstride = regs->av1d_paras.reg68_hor_virstride;
regs->av1d_paras.reg82_error_ref_virstride = y_virstride >> 4; regs->av1d_paras.reg81_error_ref_raster_uv_hor_virstride = regs->av1d_paras.reg69_raster_uv_hor_virstride;
regs->av1d_paras.reg82_error_ref_virstride = regs->av1d_paras.reg70_y_virstride;
} }
for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; ++i) { for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; ++i) {
@@ -2256,11 +2254,14 @@ MPP_RET vdpu383_av1d_gen_regs(void *hal, HalTaskInfo *task)
mpp_buf_slot_get_prop(p_hal->slots, dxva->frame_refs[mapped_idx].Index, SLOT_FRAME_PTR, &mframe); mpp_buf_slot_get_prop(p_hal->slots, dxva->frame_refs[mapped_idx].Index, SLOT_FRAME_PTR, &mframe);
if (mframe) { if (mframe) {
hor_virstride = mpp_frame_get_hor_stride(mframe); hor_virstride = mpp_frame_get_hor_stride(mframe);
if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) {
hor_virstride = MPP_ALIGN(hor_virstride, 64) / 4;
}
ver_virstride = mpp_frame_get_ver_stride(mframe); ver_virstride = mpp_frame_get_ver_stride(mframe);
y_virstride = hor_virstride * ver_virstride; y_virstride = hor_virstride * ver_virstride;
if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) {
hor_virstride = MPP_ALIGN(hor_virstride, 64) / 4;
} else if (MPP_FRAME_FMT_IS_TILE(mpp_frame_get_fmt(mframe))) {
hor_virstride = MPP_ALIGN(hor_virstride * 6, 16);
y_virstride += y_virstride / 2;
}
SET_REF_HOR_VIRSTRIDE(regs->av1d_paras, mapped_idx, hor_virstride >> 4); SET_REF_HOR_VIRSTRIDE(regs->av1d_paras, mapped_idx, hor_virstride >> 4);
SET_REF_RASTER_UV_HOR_VIRSTRIDE(regs->av1d_paras, mapped_idx, hor_virstride >> 4); SET_REF_RASTER_UV_HOR_VIRSTRIDE(regs->av1d_paras, mapped_idx, hor_virstride >> 4);
SET_REF_VIRSTRIDE(regs->av1d_paras, mapped_idx, y_virstride >> 4); SET_REF_VIRSTRIDE(regs->av1d_paras, mapped_idx, y_virstride >> 4);