diff --git a/mpp/hal/rkdec/h264d/hal_h264d_global.h b/mpp/hal/rkdec/h264d/hal_h264d_global.h index 237b0264..4ab3ece3 100644 --- a/mpp/hal/rkdec/h264d/hal_h264d_global.h +++ b/mpp/hal/rkdec/h264d/hal_h264d_global.h @@ -22,6 +22,7 @@ #include "mpp_hal.h" #include "mpp_log.h" #include "mpp_device.h" +#include "hal_bufs.h" #include "dxva_syntax.h" #include "h264d_syntax.h" @@ -122,6 +123,9 @@ typedef struct h264d_hal_ctx_t { MppBufSlots frame_slots; MppBufSlots packet_slots; MppBufferGroup buf_group; + HalBufs cmv_bufs; + RK_U32 mv_size; + RK_U32 mv_count; IOInterruptCB init_cb; MppDev dev; diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c b/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c index 9f303fe4..dcfe916b 100644 --- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c +++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c @@ -450,7 +450,7 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal { DXVA_PicParams_H264_MVC *pp = p_hal->pp; Vdpu34xRegCommon *common = ®s->common; - RK_U32 yuv_virstride = 0; + HalBuf *mv_buf = NULL; memset(regs, 0, sizeof(Vdpu34xH264dRegSet)); @@ -487,13 +487,6 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal ver_virstride = mpp_frame_get_ver_stride(mframe); y_virstride = hor_virstride * ver_virstride; - if (pp->chroma_format_idc == 0) { //!< Y400 - yuv_virstride = y_virstride; - } else if (pp->chroma_format_idc == 1) { //!< Y420 - yuv_virstride = y_virstride + y_virstride / 2; - } else if (pp->chroma_format_idc == 2) { //!< Y422 - yuv_virstride = 2 * y_virstride; - } common->dec_y_hor_stride.y_hor_virstride = hor_virstride / 16; common->dec_uv_hor_stride.uv_hor_virstride = hor_virstride / 16; common->dec_y_stride.y_virstride = y_virstride / 16; @@ -502,7 +495,6 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal { MppBuffer mbuffer = NULL; RK_S32 fd = -1; - MppDevRegOffsetCfg cfg; regs->h264d_param.cur_poc.cur_top_poc = pp->CurrFieldOrderCnt[0]; regs->h264d_param.cur_poc1.cur_bot_poc = pp->CurrFieldOrderCnt[1]; @@ -510,13 +502,11 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal fd = mpp_buffer_get_fd(mbuffer); regs->common_addr.decout_base.decout_base = fd; //colmv_cur_base - regs->common_addr.colmv_cur_base.colmv_cur_base = fd; + + mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, pp->CurrPic.Index7Bits); + regs->common_addr.colmv_cur_base.colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]); regs->common_addr.error_ref_base.error_ref_base = fd; - cfg.reg_idx = 131; - cfg.offset = MPP_ALIGN(yuv_virstride, 16); - - mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &cfg); } //!< set reference { @@ -524,7 +514,6 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal RK_S32 ref_index = -1; RK_S32 near_index = -1; MppBuffer mbuffer = NULL; - MppDevRegOffsetCfg cfg; for (i = 0; i < 15; i++) { regs->h264d_param.ref0_31_poc[i].ref_poc = (i & 1) @@ -545,12 +534,9 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_BUFFER, &mbuffer); RK_S32 fd = mpp_buffer_get_fd(mbuffer); regs->h264d_addr.ref_base[i] = fd; - regs->h264d_addr.colmv_base[i] = fd; + mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, ref_index); + regs->h264d_addr.colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]); - cfg.reg_idx = 181 + i; - cfg.offset = MPP_ALIGN(yuv_virstride, 16); - - mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &cfg); } regs->h264d_param.ref0_31_poc[30].ref_poc = pp->FieldOrderCntList[15][0]; regs->h264d_param.ref0_31_poc[31].ref_poc = pp->FieldOrderCntList[15][1]; @@ -567,12 +553,8 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_BUFFER, &mbuffer); RK_S32 fd = mpp_buffer_get_fd(mbuffer); regs->h264d_addr.ref_base[15] = fd; - regs->h264d_addr.colmv_base[15] = fd; - - cfg.reg_idx = 181 + 15; - cfg.offset = MPP_ALIGN(yuv_virstride, 16); - - mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &cfg); + mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, ref_index); + regs->h264d_addr.colmv_base[15] = mpp_buffer_get_fd(mv_buf->buf[0]); } { MppBuffer mbuffer = NULL; @@ -665,6 +647,7 @@ MPP_RET vdpu34x_h264d_deinit(void *hal) mpp_buffer_put(reg_ctx->cabac_buf); mpp_buffer_put(reg_ctx->errinfo_buf); mpp_buffer_put(reg_ctx->rcb_buf); + hal_bufs_deinit(p_hal->cmv_bufs); MPP_FREE(p_hal->reg_ctx); return MPP_OK; @@ -674,15 +657,36 @@ MPP_RET vdpu34x_h264d_gen_regs(void *hal, HalTaskInfo *task) { MPP_RET ret = MPP_ERR_UNKNOW; H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; - + RK_U32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64); + RK_U32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64); + H264dRkvRegCtx_t *ctx = (H264dRkvRegCtx_t *)p_hal->reg_ctx; + Vdpu34xH264dRegSet *regs = ctx->regs; + RK_U32 mv_size = (width * height >> 1); INP_CHECK(ret, NULL == p_hal); if (task->dec.flags.parse_err || task->dec.flags.ref_err) { goto __RETURN; } - H264dRkvRegCtx_t *ctx = (H264dRkvRegCtx_t *)p_hal->reg_ctx; - Vdpu34xH264dRegSet *regs = ctx->regs; + + if (p_hal->cmv_bufs == NULL || p_hal->mv_size < mv_size) { + size_t size = mv_size; + + if (p_hal->cmv_bufs) { + hal_bufs_deinit(p_hal->cmv_bufs); + p_hal->cmv_bufs = NULL; + } + + hal_bufs_init(&p_hal->cmv_bufs); + if (p_hal->cmv_bufs == NULL) { + mpp_err_f("colmv bufs init fail"); + goto __RETURN; + } + p_hal->mv_size = mv_size; + p_hal->mv_count = mpp_buf_slot_get_count(p_hal->frame_slots); + hal_bufs_setup(p_hal->cmv_bufs, p_hal->mv_count, 1, &size); + } + if (p_hal->fast_mode) { RK_U32 i = 0; for (i = 0; i < MPP_ARRAY_ELEMS(ctx->reg_buf); i++) { @@ -720,9 +724,6 @@ MPP_RET vdpu34x_h264d_gen_regs(void *hal, HalTaskInfo *task) regs->h264d_addr.scanlist_addr = mpp_buffer_get_fd(ctx->sclst_buf); regs->common.dec_sec_en.scanlist_addr_valid_en = 1; - RK_U32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64); - RK_U32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64); - if (ctx->rcb_buf == NULL) { RK_U32 rcb_buf_size = RCB_INTRAR_COEF * width + diff --git a/mpp/hal/rkdec/h265d/hal_h265d_ctx.h b/mpp/hal/rkdec/h265d/hal_h265d_ctx.h index a6d972dc..1cf3c927 100644 --- a/mpp/hal/rkdec/h265d/hal_h265d_ctx.h +++ b/mpp/hal/rkdec/h265d/hal_h265d_ctx.h @@ -19,6 +19,7 @@ #include "mpp_device.h" #include "mpp_hal.h" +#include "hal_bufs.h" #define MAX_GEN_REG 3 @@ -55,6 +56,10 @@ typedef struct HalH265dCtx_t { RK_U32 fast_mode_err_found; void *scaling_rk; void *scaling_qm; + HalBufs cmv_bufs; + RK_U32 mv_size; + RK_S32 mv_count; + RK_U32 is_v345; RK_U32 is_v34x; } HalH265dCtx; diff --git a/mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c b/mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c index 6aebcaa7..49d12592 100644 --- a/mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c +++ b/mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c @@ -226,7 +226,6 @@ static MPP_RET hal_h265d_vdpu34x_init(void *hal, MppHalCfg *cfg) mpp_err("h265d write cabac_table data failed\n"); return ret; } - ret = hal_h265d_alloc_res(hal); if (ret) { mpp_err("hal_h265d_alloc_res failed\n"); @@ -269,6 +268,7 @@ static MPP_RET hal_h265d_vdpu34x_deinit(void *hal) return ret; } } + hal_bufs_deinit(reg_cxt->cmv_bufs); return MPP_OK; } @@ -727,7 +727,7 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn) RK_S32 i = 0; RK_S32 log2_min_cb_size; RK_S32 width, height; - RK_S32 stride_y, stride_uv, virstrid_y, virstrid_yuv; + RK_S32 stride_y, stride_uv, virstrid_y; Vdpu34xH265dRegSet *hw_regs; RK_S32 ret = MPP_SUCCESS; MppBuffer streambuf = NULL; @@ -735,6 +735,9 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn) RK_S32 valid_ref = -1; MppBuffer framebuf = NULL; RK_U32 sw_ref_valid = 0; + HalBuf *mv_buf = NULL; + RK_S32 fd = -1; + RK_U32 mv_size = 0; if (syn->dec.flags.parse_err || syn->dec.flags.ref_err) { @@ -797,6 +800,25 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn) width = (dxva_cxt->pp.PicWidthInMinCbsY << log2_min_cb_size); height = (dxva_cxt->pp.PicHeightInMinCbsY << log2_min_cb_size); + mv_size = (width * height >> 1); + if (reg_cxt->cmv_bufs == NULL || reg_cxt->mv_size < mv_size) { + size_t size = mv_size; + + if (reg_cxt->cmv_bufs) { + hal_bufs_deinit(reg_cxt->cmv_bufs); + reg_cxt->cmv_bufs = NULL; + } + + hal_bufs_init(®_cxt->cmv_bufs); + if (reg_cxt->cmv_bufs == NULL) { + mpp_err_f("colmv bufs init fail"); + return MPP_ERR_NULL_PTR; + } + + reg_cxt->mv_size = mv_size; + reg_cxt->mv_count = mpp_buf_slot_get_count(reg_cxt->slots); + hal_bufs_setup(reg_cxt->cmv_bufs, reg_cxt->mv_count, 1, &size); + } stride_y = ((MPP_ALIGN(width, 64) * (dxva_cxt->pp.bit_depth_luma_minus8 + 8)) >> 3); @@ -806,13 +828,11 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn) stride_y = hevc_hor_align(stride_y); stride_uv = hevc_hor_align(stride_uv); virstrid_y = hevc_ver_align(height) * stride_y; - virstrid_yuv = virstrid_y + stride_uv * hevc_ver_align(height) / 2; hw_regs->common.dec_slice_num.slice_num = dxva_cxt->slice_count; hw_regs->common.dec_y_hor_stride.y_hor_virstride = stride_y >> 4; hw_regs->common.dec_uv_hor_stride.uv_hor_virstride = stride_uv >> 4; hw_regs->common.dec_y_stride.y_virstride = virstrid_y >> 4; - //hw_regs->sw_yuv_virstride = virstrid_yuv >> 4; hw_regs->h265d_param.h26x_set.h26x_rps_mode = 0; hw_regs->h265d_param.h26x_set.h26x_frame_orslice = 0; hw_regs->h265d_param.h26x_set.h26x_stream_mode = 0; @@ -820,15 +840,17 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn) mpp_buf_slot_get_prop(reg_cxt->slots, dxva_cxt->pp.CurrPic.Index7Bits, SLOT_BUFFER, &framebuf); hw_regs->common_addr.decout_base.decout_base = mpp_buffer_get_fd(framebuf); //just index need map - //add colmv base offset(22bits) + addr(10bits) - hw_regs->common_addr.colmv_cur_base.colmv_cur_base = - hw_regs->common_addr.decout_base.decout_base + ((virstrid_yuv) << 10); /*if out_base is equal to zero it means this frame may error we return directly add by csy*/ if (hw_regs->common_addr.decout_base.decout_base == 0) { return 0; } + fd = mpp_buffer_get_fd(framebuf); + hw_regs->common_addr.decout_base.decout_base = fd; + + mv_buf = hal_bufs_get_buf(reg_cxt->cmv_bufs, dxva_cxt->pp.CurrPic.Index7Bits); + hw_regs->common_addr.colmv_cur_base.colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]); hw_regs->h265d_param.cur_poc.cur_top_poc = dxva_cxt->pp.CurrPicOrderCntVal; @@ -888,17 +910,18 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn) } else { hw_regs->h265d_addr.ref0_15_base[i].ref_base = valid_ref; } - hw_regs->h265d_addr.ref0_15_colmv_base[i].colmv_base = - valid_ref + ((virstrid_yuv) << 10); + + mv_buf = hal_bufs_get_buf(reg_cxt->cmv_bufs, dxva_cxt->pp.RefPicList[i].Index7Bits); + hw_regs->h265d_addr.ref0_15_colmv_base[i].colmv_base = mpp_buffer_get_fd(mv_buf->buf[0]); + sw_ref_valid |= (1 << i); SET_REF_VALID(hw_regs->h265d_param, i, 1); } else { + mv_buf = hal_bufs_get_buf(reg_cxt->cmv_bufs, dxva_cxt->pp.CurrPic.Index7Bits); hw_regs->h265d_addr.ref0_15_base[i].ref_base = hw_regs->common_addr.decout_base.decout_base; - hw_regs->h265d_addr.ref0_15_colmv_base[i].colmv_base = - hw_regs->common_addr.decout_base.decout_base + ((virstrid_yuv) << 10); + hw_regs->h265d_addr.ref0_15_colmv_base[i].colmv_base = mpp_buffer_get_fd(mv_buf->buf[0]); } } - hw_regs->common.dec_en_mode_set.colmv_error_mode = 1; hw_regs->common.dec_en_mode_set.timeout_mode = 1; hw_regs->common.dec_en_mode_set.cur_pic_is_idr = dxva_cxt->pp.IdrPicFlag;//p_hal->slice_long->idr_flag;