From 29fc1ae1ecb46a4e5ff37ee2ba19375c66342b50 Mon Sep 17 00:00:00 2001 From: Randy Li Date: Tue, 7 Mar 2017 11:32:28 +0800 Subject: [PATCH] [h264d]: move the register table into the other file It is not necessary to make export the register table except the hal of a codec format itself. Those functions with a vdpu_ prefix is only applied to VDPU2 have been rename with vdpu2_ prefix. I also fix some code style problems. Change-Id: Ib0c3d20c84d60369c7c6432e9b0d0924e69124ff Signed-off-by: Randy Li --- mpp/hal/rkdec/h264d/CMakeLists.txt | 8 +- mpp/hal/rkdec/h264d/hal_h264d_api.c | 52 ++++---- ...al_h264d_vdpu1_reg.c => hal_h264d_vdpu1.c} | 124 ++++++++++++------ mpp/hal/rkdec/h264d/hal_h264d_vdpu1.h | 40 ++++++ mpp/hal/rkdec/h264d/hal_h264d_vdpu1_reg.h | 30 +---- ...hal_h264d_vdpu_reg.c => hal_h264d_vdpu2.c} | 120 +++++++++++------ mpp/hal/rkdec/h264d/hal_h264d_vdpu2.h | 41 ++++++ ...h264d_vdpu_reg.h => hal_h264d_vdpu2_reg.h} | 58 +++----- 8 files changed, 297 insertions(+), 176 deletions(-) rename mpp/hal/rkdec/h264d/{hal_h264d_vdpu1_reg.c => hal_h264d_vdpu1.c} (86%) create mode 100644 mpp/hal/rkdec/h264d/hal_h264d_vdpu1.h rename mpp/hal/rkdec/h264d/{hal_h264d_vdpu_reg.c => hal_h264d_vdpu2.c} (86%) create mode 100644 mpp/hal/rkdec/h264d/hal_h264d_vdpu2.h rename mpp/hal/rkdec/h264d/{hal_h264d_vdpu_reg.h => hal_h264d_vdpu2_reg.h} (90%) diff --git a/mpp/hal/rkdec/h264d/CMakeLists.txt b/mpp/hal/rkdec/h264d/CMakeLists.txt index 228bba88..1fe048c5 100644 --- a/mpp/hal/rkdec/h264d/CMakeLists.txt +++ b/mpp/hal/rkdec/h264d/CMakeLists.txt @@ -1,20 +1,16 @@ # vim: syntax=cmake - # hal h264 header set(HAL_H264D_HDR hal_h264d_global.h - hal_h264d_rkv_reg.h - hal_h264d_vdpu_reg.h - hal_h264d_vdpu1_reg.h ) # hal h264 decoder sourse set(HAL_H264D_SRC hal_h264d_api.c hal_h264d_rkv_reg.c - hal_h264d_vdpu_reg.c - hal_h264d_vdpu1_reg.c + hal_h264d_vdpu2.c + hal_h264d_vdpu1.c hal_h264d_common.c ) diff --git a/mpp/hal/rkdec/h264d/hal_h264d_api.c b/mpp/hal/rkdec/h264d/hal_h264d_api.c index 1a1d71cb..ad5e3fc4 100644 --- a/mpp/hal/rkdec/h264d/hal_h264d_api.c +++ b/mpp/hal/rkdec/h264d/hal_h264d_api.c @@ -41,8 +41,8 @@ #include "hal_h264d_api.h" #include "hal_h264d_rkv_reg.h" -#include "hal_h264d_vdpu_reg.h" -#include "hal_h264d_vdpu1_reg.h" +#include "hal_h264d_vdpu2.h" +#include "hal_h264d_vdpu1.h" RK_U32 rkv_h264d_hal_debug = 0; @@ -153,14 +153,14 @@ MPP_RET hal_h264d_init(void *hal, MppHalCfg *cfg) vpu_client = VPU_DEC; break; case VDPU2_MODE: - p_api->init = vdpu_h264d_init; - p_api->deinit = vdpu_h264d_deinit; - p_api->reg_gen = vdpu_h264d_gen_regs; - p_api->start = vdpu_h264d_start; - p_api->wait = vdpu_h264d_wait; - p_api->reset = vdpu_h264d_reset; - p_api->flush = vdpu_h264d_flush; - p_api->control = vdpu_h264d_control; + p_api->init = vdpu2_h264d_init; + p_api->deinit = vdpu2_h264d_deinit; + p_api->reg_gen = vdpu2_h264d_gen_regs; + p_api->start = vdpu2_h264d_start; + p_api->wait = vdpu2_h264d_wait; + p_api->reset = vdpu2_h264d_reset; + p_api->flush = vdpu2_h264d_flush; + p_api->control = vdpu2_h264d_control; cfg->device_id = HAL_VDPU; vpu_client = VPU_DEC; break; @@ -187,9 +187,11 @@ MPP_RET hal_h264d_init(void *hal, MppHalCfg *cfg) if (p_hal->buf_group == NULL) { #ifdef RKPLATFORM mpp_log_f("mpp_buffer_group_get_internal used ion In"); - FUN_CHECK(ret = mpp_buffer_group_get_internal(&p_hal->buf_group, MPP_BUFFER_TYPE_ION)); + FUN_CHECK(ret = mpp_buffer_group_get_internal + (&p_hal->buf_group, MPP_BUFFER_TYPE_ION)); #else - FUN_CHECK(ret = mpp_buffer_group_get_internal(&p_hal->buf_group, MPP_BUFFER_TYPE_NORMAL)); + FUN_CHECK(ret = mpp_buffer_group_get_internal + (&p_hal->buf_group, MPP_BUFFER_TYPE_NORMAL)); #endif } @@ -317,18 +319,18 @@ MPP_RET hal_h264d_control(void *hal, RK_S32 cmd_type, void *param) const MppHalApi hal_api_h264d = { - "h264d_rkdec", - MPP_CTX_DEC, - MPP_VIDEO_CodingAVC, - sizeof(H264dHalCtx_t), - 0, - hal_h264d_init, - hal_h264d_deinit, - hal_h264d_gen_regs, - hal_h264d_start, - hal_h264d_wait, - hal_h264d_reset, - hal_h264d_flush, - hal_h264d_control, + .name = "h264d_rkdec", + .type = MPP_CTX_DEC, + .coding = MPP_VIDEO_CodingAVC, + .ctx_size = sizeof(H264dHalCtx_t), + .flag = 0, + .init = hal_h264d_init, + .deinit = hal_h264d_deinit, + .reg_gen = hal_h264d_gen_regs, + .start = hal_h264d_start, + .wait = hal_h264d_wait, + .reset = hal_h264d_reset, + .flush = hal_h264d_flush, + .control = hal_h264d_control, }; diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu1_reg.c b/mpp/hal/rkdec/h264d/hal_h264d_vdpu1.c similarity index 86% rename from mpp/hal/rkdec/h264d/hal_h264d_vdpu1_reg.c rename to mpp/hal/rkdec/h264d/hal_h264d_vdpu1.c index f68120c6..e843f44c 100644 --- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu1_reg.c +++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu1.c @@ -30,13 +30,12 @@ #include "hal_h264d_global.h" #include "hal_h264d_api.h" -#include "hal_h264d_vdpu1_reg.h" #include "hal_h264d_common.h" +#include "hal_h264d_vdpu1.h" +#include "hal_h264d_vdpu1_reg.h" -/* Number registers for the decoder */ -#define DEC_VDPU1_REGISTERS (102) - -static MPP_RET vdpu1_set_refer_pic_idx(H264dVdpu1Regs_t *p_regs, RK_U32 i, RK_U16 val) +static MPP_RET vdpu1_set_refer_pic_idx(H264dVdpu1Regs_t *p_regs, RK_U32 i, + RK_U16 val) { switch (i) { case 0: @@ -94,7 +93,8 @@ static MPP_RET vdpu1_set_refer_pic_idx(H264dVdpu1Regs_t *p_regs, RK_U32 i, RK_U1 return MPP_OK; } -static MPP_RET vdpu1_set_refer_pic_list_p(H264dVdpu1Regs_t *p_regs, RK_U32 i, RK_U16 val) +static MPP_RET vdpu1_set_refer_pic_list_p(H264dVdpu1Regs_t *p_regs, RK_U32 i, + RK_U16 val) { switch (i) { case 0: @@ -152,7 +152,8 @@ static MPP_RET vdpu1_set_refer_pic_list_p(H264dVdpu1Regs_t *p_regs, RK_U32 i, RK return MPP_OK; } -static MPP_RET vdpu1_set_refer_pic_list_b0(H264dVdpu1Regs_t *p_regs, RK_U32 i, RK_U16 val) +static MPP_RET vdpu1_set_refer_pic_list_b0(H264dVdpu1Regs_t *p_regs, RK_U32 i, + RK_U16 val) { switch (i) { case 0: @@ -210,7 +211,8 @@ static MPP_RET vdpu1_set_refer_pic_list_b0(H264dVdpu1Regs_t *p_regs, RK_U32 i, R return MPP_OK; } -static MPP_RET vdpu1_set_refer_pic_list_b1(H264dVdpu1Regs_t *p_regs, RK_U32 i, RK_U16 val) +static MPP_RET vdpu1_set_refer_pic_list_b1(H264dVdpu1Regs_t *p_regs, RK_U32 i, + RK_U16 val) { switch (i) { case 0: @@ -268,7 +270,8 @@ static MPP_RET vdpu1_set_refer_pic_list_b1(H264dVdpu1Regs_t *p_regs, RK_U32 i, R return MPP_OK; } -static MPP_RET vdpu1_set_refer_pic_base_addr(H264dVdpu1Regs_t *p_regs, RK_U32 i, RK_U32 val) +static MPP_RET vdpu1_set_refer_pic_base_addr(H264dVdpu1Regs_t *p_regs, RK_U32 i, + RK_U32 val) { switch (i) { case 0: @@ -325,17 +328,20 @@ static MPP_RET vdpu1_set_refer_pic_base_addr(H264dVdpu1Regs_t *p_regs, RK_U32 i, return MPP_OK; } -static MPP_RET vdpu1_set_pic_regs(H264dHalCtx_t *p_hal, H264dVdpu1Regs_t *p_regs) +static MPP_RET vdpu1_set_pic_regs(H264dHalCtx_t *p_hal, + H264dVdpu1Regs_t *p_regs) { MPP_RET ret = MPP_ERR_UNKNOW; p_regs->SwReg04.sw_pic_mb_width = p_hal->pp->wFrameWidthInMbsMinus1 + 1; - p_regs->SwReg04.sw_pic_mb_height_p = (2 - p_hal->pp->frame_mbs_only_flag) * (p_hal->pp->wFrameHeightInMbsMinus1 + 1); + p_regs->SwReg04.sw_pic_mb_height_p = (2 - p_hal->pp->frame_mbs_only_flag) + * (p_hal->pp->wFrameHeightInMbsMinus1 + 1); return ret = MPP_OK; } -static MPP_RET vdpu1_set_vlc_regs(H264dHalCtx_t *p_hal, H264dVdpu1Regs_t *p_regs) +static MPP_RET vdpu1_set_vlc_regs(H264dHalCtx_t *p_hal, + H264dVdpu1Regs_t *p_regs) { RK_U32 i = 0; MPP_RET ret = MPP_ERR_UNKNOW; @@ -351,7 +357,8 @@ static MPP_RET vdpu1_set_vlc_regs(H264dHalCtx_t *p_hal, H264dVdpu1Regs_t *p_regs p_regs->SwReg07.sw_framenum = pp->frame_num; p_regs->SwReg08.sw_const_intra_e = pp->constrained_intra_pred_flag; - p_regs->SwReg08.sw_filt_ctrl_pres = pp->deblocking_filter_control_present_flag; + p_regs->SwReg08.sw_filt_ctrl_pres = + pp->deblocking_filter_control_present_flag; p_regs->SwReg08.sw_rdpic_cnt_pres = pp->redundant_pic_cnt_present_flag; p_regs->SwReg08.sw_refpic_mk_len = p_hal->slice_long[0].drpm_used_bitlen; p_regs->SwReg08.sw_idr_pic_e = p_hal->slice_long[0].idr_flag; @@ -409,7 +416,8 @@ static MPP_RET vdpu1_set_vlc_regs(H264dHalCtx_t *p_hal, H264dVdpu1Regs_t *p_regs //!< set poc to buffer { RK_U32 *pocBase = NULL; - pocBase = (RK_U32 *)((RK_U8 *)mpp_buffer_get_ptr(p_hal->cabac_buf) + VDPU_CABAC_TAB_SIZE); + pocBase = (RK_U32 *)((RK_U8 *)mpp_buffer_get_ptr(p_hal->cabac_buf) + + VDPU_CABAC_TAB_SIZE); //!< set reference reorder poc for (i = 0; i < 32; i++) { @@ -437,7 +445,8 @@ static MPP_RET vdpu1_set_vlc_regs(H264dHalCtx_t *p_hal, H264dVdpu1Regs_t *p_regs MppBuffer bitstream_buf = NULL; p_regs->SwReg06.sw_start_code_e = 1; - mpp_buf_slot_get_prop(p_hal->packet_slots, p_hal->in_task->input, SLOT_BUFFER, &bitstream_buf); + mpp_buf_slot_get_prop(p_hal->packet_slots, p_hal->in_task->input, + SLOT_BUFFER, &bitstream_buf); p_regs->SwReg05.sw_strm_start_bit = 0; /* sodb stream start bit */ p_regs->SwReg12.rlc_vlc_st_adr = mpp_buffer_get_fd(bitstream_buf); @@ -448,7 +457,8 @@ static MPP_RET vdpu1_set_vlc_regs(H264dHalCtx_t *p_hal, H264dVdpu1Regs_t *p_regs return ret = MPP_OK; } -static MPP_RET vdpu1_set_ref_regs(H264dHalCtx_t *p_hal, H264dVdpu1Regs_t *p_regs) +static MPP_RET vdpu1_set_ref_regs(H264dHalCtx_t *p_hal, + H264dVdpu1Regs_t *p_regs) { RK_U32 i = 0, j = 0; MPP_RET ret = MPP_ERR_UNKNOW; @@ -495,7 +505,8 @@ static MPP_RET vdpu1_set_ref_regs(H264dHalCtx_t *p_hal, H264dVdpu1Regs_t *p_regs return ret = MPP_OK; } -static MPP_RET vdpu1_set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpu1Regs_t *p_regs) +static MPP_RET vdpu1_set_asic_regs(H264dHalCtx_t *p_hal, + H264dVdpu1Regs_t *p_regs) { RK_U32 i = 0, j = 0; RK_U32 outPhyAddr = 0; @@ -510,10 +521,14 @@ static MPP_RET vdpu1_set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpu1Regs_t *p_reg RK_U32 top_closer = 0; RK_U32 field_flag = 0; if (pp->RefFrameList[i].bPicEntry != 0xff) { - mpp_buf_slot_get_prop(p_hal->frame_slots, pp->RefFrameList[i].Index7Bits, SLOT_BUFFER, &frame_buf); //!< reference phy addr + mpp_buf_slot_get_prop(p_hal->frame_slots, + pp->RefFrameList[i].Index7Bits, + SLOT_BUFFER, &frame_buf); //!< reference phy addr j = i; } else { - mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &frame_buf); //!< current out phy addr + mpp_buf_slot_get_prop(p_hal->frame_slots, + pp->CurrPic.Index7Bits, + SLOT_BUFFER, &frame_buf); //!< current out phy addr } field_flag = ((pp->RefPicFiledFlags >> i) & 0x1) ? 0x2 : 0; @@ -522,10 +537,12 @@ static MPP_RET vdpu1_set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpu1Regs_t *p_reg RK_S32 cur_poc = 0; RK_S32 ref_poc = 0; - cur_poc = pp->CurrPic.AssociatedFlag ? pp->CurrFieldOrderCnt[1] : pp->CurrFieldOrderCnt[0]; + cur_poc = pp->CurrPic.AssociatedFlag + ? pp->CurrFieldOrderCnt[1] : pp->CurrFieldOrderCnt[0]; used_flag = ((pp->UsedForReferenceFlags >> (2 * i)) & 0x3); if (used_flag & 0x3) { - ref_poc = MPP_MIN(pp->FieldOrderCntList[i][0], pp->FieldOrderCntList[i][1]); + ref_poc = MPP_MIN(pp->FieldOrderCntList[i][0], + pp->FieldOrderCntList[i][1]); } else if (used_flag & 0x2) { ref_poc = pp->FieldOrderCntList[i][1]; } else if (used_flag & 0x1) { @@ -543,16 +560,21 @@ static MPP_RET vdpu1_set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpu1Regs_t *p_reg { H264dVdpuPriv_t *priv = (H264dVdpuPriv_t *)p_hal->priv; if (pp->curr_layer_id && priv->ilt_dpb && priv->ilt_dpb->valid /*pp->inter_view_flag*/) { - mpp_buf_slot_get_prop(p_hal->frame_slots, priv->ilt_dpb->slot_index, SLOT_BUFFER, &frame_buf); + mpp_buf_slot_get_prop(p_hal->frame_slots, + priv->ilt_dpb->slot_index, + SLOT_BUFFER, &frame_buf); p_regs->SwReg29.sw_refer15_base = mpp_buffer_get_fd(frame_buf); //!< inter-view base, ref15 - p_regs->SwReg39.refpic_valid_flag |= (pp->field_pic_flag ? 0x3 : 0x10000); + p_regs->SwReg39.refpic_valid_flag |= + (pp->field_pic_flag ? 0x3 : 0x10000); } } p_regs->SwReg03.sw_pic_fixed_quant = pp->curr_layer_id; //!< VDPU_MVC_E p_regs->SwReg03.sw_filtering_dis = 0; - mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &frame_buf); //!< current out phy addr + mpp_buf_slot_get_prop(p_hal->frame_slots, + pp->CurrPic.Index7Bits, + SLOT_BUFFER, &frame_buf); //!< current out phy addr outPhyAddr = mpp_buffer_get_fd(frame_buf); if (pp->field_pic_flag && pp->CurrPic.AssociatedFlag) { outPhyAddr |= ((pp->wFrameWidthInMbsMinus1 + 1) * 16) << 10; @@ -568,9 +590,12 @@ static MPP_RET vdpu1_set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpu1Regs_t *p_reg RK_U32 picSizeInMbs = 0; picSizeInMbs = p_hal->pp->wFrameWidthInMbsMinus1 + 1; - picSizeInMbs = picSizeInMbs * (2 - pp->frame_mbs_only_flag) * (pp->wFrameHeightInMbsMinus1 + 1); - dirMvOffset = picSizeInMbs * ((p_hal->pp->chroma_format_idc == 0) ? 256 : 384); - dirMvOffset += (pp->field_pic_flag && pp->CurrPic.AssociatedFlag) ? (picSizeInMbs * 32) : 0; + picSizeInMbs = picSizeInMbs * (2 - pp->frame_mbs_only_flag) + * (pp->wFrameHeightInMbsMinus1 + 1); + dirMvOffset = picSizeInMbs + * ((p_hal->pp->chroma_format_idc == 0) ? 256 : 384); + dirMvOffset += (pp->field_pic_flag && pp->CurrPic.AssociatedFlag) + ? (picSizeInMbs * 32) : 0; p_regs->SwReg41.dmmv_st_adr = (mpp_buffer_get_fd(frame_buf) | (dirMvOffset << 6)); } @@ -581,12 +606,15 @@ static MPP_RET vdpu1_set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpu1Regs_t *p_reg p_regs->SwReg09.sw_refidx1_active = (pp->num_ref_idx_l1_active_minus1 + 1); p_regs->SwReg05.sw_fieldpic_flag_e = (!pp->frame_mbs_only_flag) ? 1 : 0; - p_regs->SwReg03.sw_pic_interlace_e = (!pp->frame_mbs_only_flag && (pp->MbaffFrameFlag || pp->field_pic_flag)) ? 1 : 0; + p_regs->SwReg03.sw_pic_interlace_e = + (!pp->frame_mbs_only_flag + && (pp->MbaffFrameFlag || pp->field_pic_flag)) ? 1 : 0; p_regs->SwReg03.sw_pic_fieldmode_e = pp->field_pic_flag; p_regs->SwReg03.sw_pic_topfield_e = (!pp->CurrPic.AssociatedFlag) ? 1 : 0; /* bottomFieldFlag */ p_regs->SwReg03.sw_seq_mbaff_e = pp->MbaffFrameFlag; p_regs->SwReg08.sw_8x8trans_flag_e = pp->transform_8x8_mode_flag; - p_regs->SwReg07.sw_blackwhite_e = (p_long->profileIdc >= 100 && pp->chroma_format_idc == 0) ? 1 : 0; + p_regs->SwReg07.sw_blackwhite_e = (p_long->profileIdc >= 100 + && pp->chroma_format_idc == 0) ? 1 : 0; p_regs->SwReg05.sw_type1_quant_e = pp->scaleing_list_enable_flag; { @@ -594,7 +622,8 @@ static MPP_RET vdpu1_set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpu1Regs_t *p_reg if (p_hal->pp->scaleing_list_enable_flag) { RK_U32 temp = 0; RK_U32 *ptr = NULL; - ptr = (RK_U32 *)((RK_U8 *)mpp_buffer_get_ptr(p_hal->cabac_buf) + offset); + ptr = (RK_U32 *)((RK_U8 *)mpp_buffer_get_ptr(p_hal->cabac_buf) + + offset); for (i = 0; i < 6; i++) { for (j = 0; j < 4; j++) { @@ -626,7 +655,8 @@ static MPP_RET vdpu1_set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpu1Regs_t *p_reg return ret = MPP_OK; } -static MPP_RET vdpu1_set_device_regs(H264dHalCtx_t *p_hal, H264dVdpu1Regs_t *p_reg) +static MPP_RET vdpu1_set_device_regs(H264dHalCtx_t *p_hal, + H264dVdpu1Regs_t *p_reg) { MPP_RET ret = MPP_ERR_UNKNOW; @@ -688,16 +718,23 @@ MPP_RET vdpu1_h264d_init(void *hal, MppHalCfg *cfg) INP_CHECK(ret, NULL == hal); //!< malloc init registers - MEM_CHECK(ret, p_hal->regs = mpp_calloc_size(void, sizeof(H264dVdpu1Regs_t))); - MEM_CHECK(ret, p_hal->priv = mpp_calloc_size(void, sizeof(H264dVdpuPriv_t))); + MEM_CHECK(ret, p_hal->regs = + mpp_calloc_size(void, sizeof(H264dVdpu1Regs_t))); + MEM_CHECK(ret, p_hal->priv = + mpp_calloc_size(void, sizeof(H264dVdpuPriv_t))); //!< malloc cabac+scanlis + packets + poc_buf - cabac_size = VDPU_CABAC_TAB_SIZE + VDPU_SCALING_LIST_SIZE + VDPU_POC_BUF_SIZE; - FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, &p_hal->cabac_buf, cabac_size)); + cabac_size = VDPU_CABAC_TAB_SIZE + VDPU_SCALING_LIST_SIZE + + VDPU_POC_BUF_SIZE; + FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, &p_hal->cabac_buf, + cabac_size)); //!< copy cabac table bytes - FUN_CHECK(ret = mpp_buffer_write(p_hal->cabac_buf, 0, (void *)vdpu_cabac_table, sizeof(vdpu_cabac_table))); - FUN_CHECK(ret = vdpu1_set_device_regs(p_hal, (H264dVdpu1Regs_t *)p_hal->regs)); + FUN_CHECK(ret = mpp_buffer_write(p_hal->cabac_buf, 0, + (void *)vdpu_cabac_table, + sizeof(vdpu_cabac_table))); + FUN_CHECK(ret = vdpu1_set_device_regs(p_hal, + (H264dVdpu1Regs_t *)p_hal->regs)); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, vdpu_hor_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, vdpu_ver_align); @@ -761,7 +798,8 @@ MPP_RET vdpu1_h264d_gen_regs(void *hal, HalTaskInfo *task) FUN_CHECK(ret = vdpu1_set_pic_regs(p_hal, (H264dVdpu1Regs_t *)p_hal->regs)); FUN_CHECK(ret = vdpu1_set_vlc_regs(p_hal, (H264dVdpu1Regs_t *)p_hal->regs)); FUN_CHECK(ret = vdpu1_set_ref_regs(p_hal, (H264dVdpu1Regs_t *)p_hal->regs)); - FUN_CHECK(ret = vdpu1_set_asic_regs(p_hal, (H264dVdpu1Regs_t *)p_hal->regs)); + FUN_CHECK(ret = vdpu1_set_asic_regs(p_hal, + (H264dVdpu1Regs_t *)p_hal->regs)); p_hal->in_task->valid = 0; __RETURN: @@ -795,9 +833,11 @@ MPP_RET vdpu1_h264d_start(void *hal, HalTaskInfo *task) p_regs->SwReg57.sw_paral_bus = 1; #ifdef RKPLATFORM - if (VPUClientSendReg(p_hal->vpu_socket, (RK_U32 *)p_hal->regs, DEC_VDPU1_REGISTERS)) { + if (VPUClientSendReg(p_hal->vpu_socket, (RK_U32 *)p_hal->regs, + DEC_VDPU1_REGISTERS)) { ret = MPP_ERR_VPUHW; - mpp_err_f("H264 VDPU1 FlushRegs fail, pid=%d, hal_frame_no=%d. \n", getpid()); + mpp_err_f("H264 VDPU1 FlushRegs fail, pid=%d, hal_frame_no=%d. \n", + getpid()); } #endif @@ -827,7 +867,9 @@ MPP_RET vdpu1_h264d_wait(void *hal, HalTaskInfo *task) RK_S32 wait_ret = -1; RK_S32 ret_len = 0; VPU_CMD_TYPE ret_cmd = VPU_CMD_BUTT; - wait_ret = VPUClientWaitResult(p_hal->vpu_socket, (RK_U32 *)p_hal->regs, DEC_VDPU1_REGISTERS, &ret_cmd, &ret_len); + wait_ret = VPUClientWaitResult(p_hal->vpu_socket, + (RK_U32 *)p_hal->regs, + DEC_VDPU1_REGISTERS, &ret_cmd, &ret_len); if (wait_ret) { ret = MPP_ERR_VPUHW; mpp_err("H264 VDPU1 wait result fail, pid=%d.\n", getpid()); diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu1.h b/mpp/hal/rkdec/h264d/hal_h264d_vdpu1.h new file mode 100644 index 00000000..2324f035 --- /dev/null +++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu1.h @@ -0,0 +1,40 @@ +/* + * + * Copyright 2015 Rockchip Electronics Co. LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_H264D_VDPU1_REG_H__ +#define __HAL_H264D_VDPU1_REG_H__ + +#include "mpp_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + +MPP_RET vdpu1_h264d_init (void *hal, MppHalCfg *cfg); +MPP_RET vdpu1_h264d_deinit (void *hal); +MPP_RET vdpu1_h264d_gen_regs(void *hal, HalTaskInfo *task); +MPP_RET vdpu1_h264d_start (void *hal, HalTaskInfo *task); +MPP_RET vdpu1_h264d_wait (void *hal, HalTaskInfo *task); +MPP_RET vdpu1_h264d_reset (void *hal); +MPP_RET vdpu1_h264d_flush (void *hal); +MPP_RET vdpu1_h264d_control (void *hal, RK_S32 cmd_type, void *param); + +#ifdef __cplusplus +} +#endif + +#endif /*__HAL_H264D_VDPU1_REG_H__*/ diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu1_reg.h b/mpp/hal/rkdec/h264d/hal_h264d_vdpu1_reg.h index 45b06123..e0f471c6 100644 --- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu1_reg.h +++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu1_reg.h @@ -15,11 +15,13 @@ * limitations under the License. */ -#ifndef __HAL_H264D_VDPU1_REG_H__ -#define __HAL_H264D_VDPU1_REG_H__ +#ifndef __HAL_H264D_VDPU1_REG_TBL_H__ +#define __HAL_H264D_VDPU1_REG_TBL_H__ -#include "mpp_hal.h" +#include "rk_type.h" +/* Number registers for the decoder */ +#define DEC_VDPU1_REGISTERS (101) typedef struct { RK_U32 SwReg00; @@ -422,25 +424,7 @@ typedef struct { RK_U32 reserve0 : 24; } SwReg57; - RK_U32 SwReg58_101[44]; + RK_U32 SwReg58_100[43]; } H264dVdpu1Regs_t; - -#ifdef __cplusplus -extern "C" { -#endif - -MPP_RET vdpu1_h264d_init (void *hal, MppHalCfg *cfg); -MPP_RET vdpu1_h264d_deinit (void *hal); -MPP_RET vdpu1_h264d_gen_regs(void *hal, HalTaskInfo *task); -MPP_RET vdpu1_h264d_start (void *hal, HalTaskInfo *task); -MPP_RET vdpu1_h264d_wait (void *hal, HalTaskInfo *task); -MPP_RET vdpu1_h264d_reset (void *hal); -MPP_RET vdpu1_h264d_flush (void *hal); -MPP_RET vdpu1_h264d_control (void *hal, RK_S32 cmd_type, void *param); - -#ifdef __cplusplus -} -#endif - -#endif /*__HAL_H264D_VDPU1_REG_H__*/ +#endif /*__HAL_H264D_VDPU1_REG_TBL_H__*/ diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu_reg.c b/mpp/hal/rkdec/h264d/hal_h264d_vdpu2.c similarity index 86% rename from mpp/hal/rkdec/h264d/hal_h264d_vdpu_reg.c rename to mpp/hal/rkdec/h264d/hal_h264d_vdpu2.c index 362aabe6..e5c361ee 100644 --- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu_reg.c +++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu2.c @@ -30,11 +30,9 @@ #include "hal_h264d_global.h" #include "hal_h264d_api.h" -#include "hal_h264d_vdpu_reg.h" #include "hal_h264d_common.h" - -/* Number registers for the decoder */ -#define DEC_VDPU_REGISTERS 159 +#include "hal_h264d_vdpu2.h" +#include "hal_h264d_vdpu2_reg.h" static MPP_RET set_device_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_reg) { @@ -138,7 +136,8 @@ static MPP_RET set_refer_pic_idx(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 val) return MPP_OK; } -static MPP_RET set_refer_pic_list_p(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 val) +static MPP_RET set_refer_pic_list_p(H264dVdpuRegs_t *p_regs, RK_U32 i, + RK_U16 val) { switch (i) { case 0: @@ -196,7 +195,8 @@ static MPP_RET set_refer_pic_list_p(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 va return MPP_OK; } -static MPP_RET set_refer_pic_list_b0(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 val) +static MPP_RET set_refer_pic_list_b0(H264dVdpuRegs_t *p_regs, RK_U32 i, + RK_U16 val) { switch (i) { case 0: @@ -254,7 +254,8 @@ static MPP_RET set_refer_pic_list_b0(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 v return MPP_OK; } -static MPP_RET set_refer_pic_list_b1(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 val) +static MPP_RET set_refer_pic_list_b1(H264dVdpuRegs_t *p_regs, RK_U32 i, + RK_U16 val) { switch (i) { case 0: @@ -312,7 +313,8 @@ static MPP_RET set_refer_pic_list_b1(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 v return MPP_OK; } -static MPP_RET set_refer_pic_base_addr(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U32 val) +static MPP_RET set_refer_pic_base_addr(H264dVdpuRegs_t *p_regs, RK_U32 i, + RK_U32 val) { switch (i) { case 0: @@ -374,7 +376,8 @@ static MPP_RET set_pic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) MPP_RET ret = MPP_ERR_UNKNOW; p_regs->sw110.pic_mb_w = p_hal->pp->wFrameWidthInMbsMinus1 + 1; - p_regs->sw110.pic_mb_h = (2 - p_hal->pp->frame_mbs_only_flag) * (p_hal->pp->wFrameHeightInMbsMinus1 + 1); + p_regs->sw110.pic_mb_h = (2 - p_hal->pp->frame_mbs_only_flag) + * (p_hal->pp->wFrameHeightInMbsMinus1 + 1); return ret = MPP_OK; } @@ -412,7 +415,8 @@ static MPP_RET set_vlc_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) longTermTmp = pp->RefFrameList[i / 2].AssociatedFlag; //!< get long term flag longTermflags = (longTermflags << 1) | longTermTmp; - validFlags = (validFlags << 1) | ((pp->UsedForReferenceFlags >> i) & 0x01); + validFlags = (validFlags << 1) + | ((pp->UsedForReferenceFlags >> i) & 0x01); } } p_regs->sw107.refpic_term_flag = longTermflags; @@ -427,7 +431,8 @@ static MPP_RET set_vlc_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) } else { longTermTmp = pp->RefFrameList[i].AssociatedFlag; longTermflags = (longTermflags << 1) | longTermTmp; - validFlags = (validFlags << 1) | ((pp->UsedForReferenceFlags >> (2 * i)) & 0x03); + validFlags = (validFlags << 1) + | ((pp->UsedForReferenceFlags >> (2 * i)) & 0x03); } } p_regs->sw107.refpic_term_flag = (longTermflags << 16); @@ -447,7 +452,8 @@ static MPP_RET set_vlc_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) //!< set poc to buffer { RK_U32 *ptr = NULL; - ptr = (RK_U32 *)((RK_U8 *)mpp_buffer_get_ptr(p_hal->cabac_buf) + VDPU_CABAC_TAB_SIZE); + ptr = (RK_U32 *)((RK_U8 *)mpp_buffer_get_ptr(p_hal->cabac_buf) + + VDPU_CABAC_TAB_SIZE); //!< set reference reorder poc for (i = 0; i < 32; i++) { if (pp->RefFrameList[i / 2].bPicEntry != 0xff) { @@ -470,7 +476,9 @@ static MPP_RET set_vlc_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) { MppBuffer bitstream_buf = NULL; p_regs->sw57.st_code_exit = 1; - mpp_buf_slot_get_prop(p_hal->packet_slots, p_hal->in_task->input, SLOT_BUFFER, &bitstream_buf); + mpp_buf_slot_get_prop(p_hal->packet_slots, + p_hal->in_task->input, + SLOT_BUFFER, &bitstream_buf); p_regs->sw109.strm_start_bit = 0; //!< sodb stream start bit p_regs->sw64.rlc_vlc_st_adr = mpp_buffer_get_fd(bitstream_buf); p_regs->sw51.stream_len = p_hal->strm_len; @@ -540,10 +548,14 @@ static MPP_RET set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) RK_U32 top_closer = 0; RK_U32 field_flag = 0; if (pp->RefFrameList[i].bPicEntry != 0xff) { - mpp_buf_slot_get_prop(p_hal->frame_slots, pp->RefFrameList[i].Index7Bits, SLOT_BUFFER, &frame_buf); //!< reference phy addr + mpp_buf_slot_get_prop(p_hal->frame_slots, + pp->RefFrameList[i].Index7Bits, + SLOT_BUFFER, &frame_buf); //!< reference phy addr j = i; } else { - mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &frame_buf); //!< current out phy addr + mpp_buf_slot_get_prop(p_hal->frame_slots, + pp->CurrPic.Index7Bits, + SLOT_BUFFER, &frame_buf); //!< current out phy addr } field_flag = ((pp->RefPicFiledFlags >> i) & 0x1) ? 0x2 : 0; @@ -552,10 +564,12 @@ static MPP_RET set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) RK_S32 cur_poc = 0; RK_S32 ref_poc = 0; - cur_poc = pp->CurrPic.AssociatedFlag ? pp->CurrFieldOrderCnt[1] : pp->CurrFieldOrderCnt[0]; + cur_poc = pp->CurrPic.AssociatedFlag + ? pp->CurrFieldOrderCnt[1] : pp->CurrFieldOrderCnt[0]; used_flag = ((pp->UsedForReferenceFlags >> (2 * i)) & 0x3); if (used_flag & 0x3) { - ref_poc = MPP_MIN(pp->FieldOrderCntList[i][0], pp->FieldOrderCntList[i][1]); + ref_poc = MPP_MIN(pp->FieldOrderCntList[i][0], + pp->FieldOrderCntList[i][1]); } else if (used_flag & 0x2) { ref_poc = pp->FieldOrderCntList[i][1]; } else if (used_flag & 0x1) { @@ -570,15 +584,20 @@ static MPP_RET set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) /* inter-view reference picture */ { H264dVdpuPriv_t *priv = (H264dVdpuPriv_t *)p_hal->priv; - if (pp->curr_layer_id && priv->ilt_dpb && priv->ilt_dpb->valid /*pp->inter_view_flag*/) { - mpp_buf_slot_get_prop(p_hal->frame_slots, priv->ilt_dpb->slot_index, SLOT_BUFFER, &frame_buf); + if (pp->curr_layer_id && priv->ilt_dpb && priv->ilt_dpb->valid) { + mpp_buf_slot_get_prop(p_hal->frame_slots, + priv->ilt_dpb->slot_index, + SLOT_BUFFER, &frame_buf); p_regs->sw99.ref15_st_addr = mpp_buffer_get_fd(frame_buf); //!< inter-view base, ref15 - p_regs->sw108.refpic_valid_flag |= (pp->field_pic_flag ? 0x3 : 0x10000); + p_regs->sw108.refpic_valid_flag |= (pp->field_pic_flag + ? 0x3 : 0x10000); } } p_regs->sw50.dec_fixed_quant = pp->curr_layer_id; //!< VDPU_MVC_E p_regs->sw50.dblk_flt_dis = 0; //!< filterDisable = 0; - mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &frame_buf); //!< current out phy addr + mpp_buf_slot_get_prop(p_hal->frame_slots, + pp->CurrPic.Index7Bits, + SLOT_BUFFER, &frame_buf); //!< current out phy addr outPhyAddr = mpp_buffer_get_fd(frame_buf); if (pp->field_pic_flag && pp->CurrPic.AssociatedFlag) { outPhyAddr |= ((pp->wFrameWidthInMbsMinus1 + 1) * 16) << 10; @@ -592,9 +611,12 @@ static MPP_RET set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) RK_U32 picSizeInMbs = 0; picSizeInMbs = p_hal->pp->wFrameWidthInMbsMinus1 + 1; - picSizeInMbs = picSizeInMbs * (2 - pp->frame_mbs_only_flag) * (pp->wFrameHeightInMbsMinus1 + 1); - dirMvOffset = picSizeInMbs * ((p_hal->pp->chroma_format_idc == 0) ? 256 : 384); - dirMvOffset += (pp->field_pic_flag && pp->CurrPic.AssociatedFlag) ? (picSizeInMbs * 32) : 0; + picSizeInMbs = picSizeInMbs + * (2 - pp->frame_mbs_only_flag) * (pp->wFrameHeightInMbsMinus1 + 1); + dirMvOffset = picSizeInMbs + * ((p_hal->pp->chroma_format_idc == 0) ? 256 : 384); + dirMvOffset += (pp->field_pic_flag && pp->CurrPic.AssociatedFlag) + ? (picSizeInMbs * 32) : 0; p_regs->sw62.dmmv_st_adr = (mpp_buffer_get_fd(frame_buf) | (dirMvOffset << 6)); } p_regs->sw57.dmmv_wr_en = (p_long->nal_ref_idc != 0) ? 1 : 0; //!< defalut set 1 @@ -603,19 +625,22 @@ static MPP_RET set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) p_regs->sw111.wp_bslice_sel = pp->weighted_bipred_idc; p_regs->sw114.max_refidx1 = (pp->num_ref_idx_l1_active_minus1 + 1); p_regs->sw115.fieldpic_flag_exist = (!pp->frame_mbs_only_flag) ? 1 : 0; - p_regs->sw57.curpic_code_sel = (!pp->frame_mbs_only_flag && (pp->MbaffFrameFlag || pp->field_pic_flag)) ? 1 : 0; + p_regs->sw57.curpic_code_sel = (!pp->frame_mbs_only_flag + && (pp->MbaffFrameFlag || pp->field_pic_flag)) ? 1 : 0; p_regs->sw57.curpic_stru_sel = pp->field_pic_flag; p_regs->sw57.pic_decfield_sel = (!pp->CurrPic.AssociatedFlag) ? 1 : 0; //!< bottomFieldFlag p_regs->sw57.sequ_mbaff_en = pp->MbaffFrameFlag; p_regs->sw115.tranf_8x8_flag_en = pp->transform_8x8_mode_flag; - p_regs->sw115.monochr_en = (p_long->profileIdc >= 100 && pp->chroma_format_idc == 0) ? 1 : 0; + p_regs->sw115.monochr_en = (p_long->profileIdc >= 100 + && pp->chroma_format_idc == 0) ? 1 : 0; p_regs->sw115.scl_matrix_en = pp->scaleing_list_enable_flag; { RK_U32 offset = VDPU_CABAC_TAB_SIZE + VDPU_POC_BUF_SIZE; if (p_hal->pp->scaleing_list_enable_flag) { RK_U32 temp = 0; RK_U32 *ptr = NULL; - ptr = (RK_U32 *)((RK_U8 *)mpp_buffer_get_ptr(p_hal->cabac_buf) + offset); + ptr = (RK_U32 *)((RK_U8 *)mpp_buffer_get_ptr(p_hal->cabac_buf) + + offset); for (i = 0; i < 6; i++) { for (j = 0; j < 4; j++) { temp = (p_hal->qm->bScalingLists4x4[i][4 * j + 0] << 24) | @@ -651,7 +676,7 @@ static MPP_RET set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) *********************************************************************** */ //extern "C" -MPP_RET vdpu_h264d_init(void *hal, MppHalCfg *cfg) +MPP_RET vdpu2_h264d_init(void *hal, MppHalCfg *cfg) { RK_U32 cabac_size = 0; MPP_RET ret = MPP_ERR_UNKNOW; @@ -659,13 +684,19 @@ MPP_RET vdpu_h264d_init(void *hal, MppHalCfg *cfg) INP_CHECK(ret, NULL == hal); //!< malloc init registers - MEM_CHECK(ret, p_hal->regs = mpp_calloc_size(void, sizeof(H264dVdpuRegs_t))); - MEM_CHECK(ret, p_hal->priv = mpp_calloc_size(void, sizeof(H264dVdpuPriv_t))); + MEM_CHECK(ret, p_hal->regs = mpp_calloc_size(void, + sizeof(H264dVdpuRegs_t))); + MEM_CHECK(ret, p_hal->priv = mpp_calloc_size(void, + sizeof(H264dVdpuPriv_t))); //!< malloc cabac+scanlis + packets + poc_buf - cabac_size = VDPU_CABAC_TAB_SIZE + VDPU_SCALING_LIST_SIZE + VDPU_POC_BUF_SIZE; - FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, &p_hal->cabac_buf, cabac_size)); + cabac_size = VDPU_CABAC_TAB_SIZE + VDPU_SCALING_LIST_SIZE + + VDPU_POC_BUF_SIZE; + FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, + &p_hal->cabac_buf, cabac_size)); //!< copy cabac table bytes - FUN_CHECK(ret = mpp_buffer_write(p_hal->cabac_buf, 0, (void *)vdpu_cabac_table, sizeof(vdpu_cabac_table))); + FUN_CHECK(ret = mpp_buffer_write(p_hal->cabac_buf, 0, + (void *)vdpu_cabac_table, + sizeof(vdpu_cabac_table))); FUN_CHECK(ret = set_device_regs(p_hal, (H264dVdpuRegs_t *)p_hal->regs)); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, vdpu_hor_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, vdpu_ver_align); @@ -674,7 +705,7 @@ MPP_RET vdpu_h264d_init(void *hal, MppHalCfg *cfg) __RETURN: return MPP_OK; __FAILED: - vdpu_h264d_deinit(hal); + vdpu2_h264d_deinit(hal); return ret; } @@ -687,7 +718,7 @@ __FAILED: *********************************************************************** */ //extern "C" -MPP_RET vdpu_h264d_deinit(void *hal) +MPP_RET vdpu2_h264d_deinit(void *hal) { MPP_RET ret = MPP_ERR_UNKNOW; H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; @@ -712,7 +743,7 @@ __FAILED: *********************************************************************** */ //extern "C" -MPP_RET vdpu_h264d_gen_regs(void *hal, HalTaskInfo *task) +MPP_RET vdpu2_h264d_gen_regs(void *hal, HalTaskInfo *task) { MPP_RET ret = MPP_ERR_UNKNOW; @@ -746,7 +777,7 @@ __FAILED: *********************************************************************** */ //extern "C" -MPP_RET vdpu_h264d_start(void *hal, HalTaskInfo *task) +MPP_RET vdpu2_h264d_start(void *hal, HalTaskInfo *task) { MPP_RET ret = MPP_ERR_UNKNOW; H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; @@ -762,7 +793,8 @@ MPP_RET vdpu_h264d_start(void *hal, HalTaskInfo *task) p_regs->sw57.inter_dblspeed = 1; p_regs->sw57.intra_dblspeed = 1; #ifdef RKPLATFORM - if (VPUClientSendReg(p_hal->vpu_socket, (RK_U32 *)p_hal->regs, DEC_VDPU_REGISTERS)) { + if (VPUClientSendReg(p_hal->vpu_socket, (RK_U32 *)p_hal->regs, + DEC_VDPU_REGISTERS)) { ret = MPP_ERR_VPUHW; mpp_err("H264 VDPU FlushRegs fail, pid=%d.\n", getpid()); } @@ -778,7 +810,7 @@ __RETURN: *********************************************************************** */ //extern "C" -MPP_RET vdpu_h264d_wait(void *hal, HalTaskInfo *task) +MPP_RET vdpu2_h264d_wait(void *hal, HalTaskInfo *task) { MPP_RET ret = MPP_ERR_UNKNOW; H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; @@ -792,7 +824,9 @@ MPP_RET vdpu_h264d_wait(void *hal, HalTaskInfo *task) RK_S32 wait_ret = -1; RK_S32 ret_len = 0; VPU_CMD_TYPE ret_cmd = VPU_CMD_BUTT; - wait_ret = VPUClientWaitResult(p_hal->vpu_socket, (RK_U32 *)p_hal->regs, DEC_VDPU_REGISTERS, &ret_cmd, &ret_len); + wait_ret = VPUClientWaitResult(p_hal->vpu_socket, + (RK_U32 *)p_hal->regs, + DEC_VDPU_REGISTERS, &ret_cmd, &ret_len); if (wait_ret) { ret = MPP_ERR_VPUHW; mpp_err("H264 VDPU wait result fail, pid=%d.\n", getpid()); @@ -826,7 +860,7 @@ __SKIP_HARD: *********************************************************************** */ //extern "C" -MPP_RET vdpu_h264d_reset(void *hal) +MPP_RET vdpu2_h264d_reset(void *hal) { MPP_RET ret = MPP_ERR_UNKNOW; H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; @@ -845,7 +879,7 @@ __RETURN: *********************************************************************** */ //extern "C" -MPP_RET vdpu_h264d_flush(void *hal) +MPP_RET vdpu2_h264d_flush(void *hal) { MPP_RET ret = MPP_ERR_UNKNOW; H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; @@ -862,7 +896,7 @@ __RETURN: *********************************************************************** */ //extern "C" -MPP_RET vdpu_h264d_control(void *hal, RK_S32 cmd_type, void *param) +MPP_RET vdpu2_h264d_control(void *hal, RK_S32 cmd_type, void *param) { MPP_RET ret = MPP_ERR_UNKNOW; H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu2.h b/mpp/hal/rkdec/h264d/hal_h264d_vdpu2.h new file mode 100644 index 00000000..7f13705a --- /dev/null +++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu2.h @@ -0,0 +1,41 @@ +/* + * + * Copyright 2015 Rockchip Electronics Co. LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_H264D_VDPU2_REG_H__ +#define __HAL_H264D_VDPU2_REG_H__ + +#include "mpp_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + +MPP_RET vdpu2_h264d_init (void *hal, MppHalCfg *cfg); +MPP_RET vdpu2_h264d_deinit (void *hal); +MPP_RET vdpu2_h264d_gen_regs(void *hal, HalTaskInfo *task); +MPP_RET vdpu2_h264d_start (void *hal, HalTaskInfo *task); +MPP_RET vdpu2_h264d_wait (void *hal, HalTaskInfo *task); +MPP_RET vdpu2_h264d_reset (void *hal); +MPP_RET vdpu2_h264d_flush (void *hal); +MPP_RET vdpu2_h264d_control (void *hal, RK_S32 cmd_type, void *param); + + +#ifdef __cplusplus +} +#endif + +#endif /*__HAL_H264D_VDPU2_REG_H__*/ diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu_reg.h b/mpp/hal/rkdec/h264d/hal_h264d_vdpu2_reg.h similarity index 90% rename from mpp/hal/rkdec/h264d/hal_h264d_vdpu_reg.h rename to mpp/hal/rkdec/h264d/hal_h264d_vdpu2_reg.h index 1e41a995..8bdec9a9 100644 --- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu_reg.h +++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu2_reg.h @@ -1,26 +1,26 @@ /* -* -* Copyright 2015 Rockchip Electronics Co. LTD -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ + * Copyright 2015 Rockchip Electronics Co. LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __HAL_H264D_VDPU2_REG_TBL_H__ +#define __HAL_H264D_VDPU2_REG_TBL_H__ -#ifndef __HAL_H264D_VDPU_REG_H__ -#define __HAL_H264D_VDPU_REG_H__ - -#include "mpp_hal.h" +#include "rk_type.h" +/* Number registers for the decoder */ +#define DEC_VDPU_REGISTERS 159 typedef struct { RK_U32 sw00_49[50]; @@ -463,22 +463,4 @@ typedef struct { RK_U32 sw116_158[43]; } H264dVdpuRegs_t; -#ifdef __cplusplus -extern "C" { -#endif - -MPP_RET vdpu_h264d_init (void *hal, MppHalCfg *cfg); -MPP_RET vdpu_h264d_deinit (void *hal); -MPP_RET vdpu_h264d_gen_regs(void *hal, HalTaskInfo *task); -MPP_RET vdpu_h264d_start (void *hal, HalTaskInfo *task); -MPP_RET vdpu_h264d_wait (void *hal, HalTaskInfo *task); -MPP_RET vdpu_h264d_reset (void *hal); -MPP_RET vdpu_h264d_flush (void *hal); -MPP_RET vdpu_h264d_control (void *hal, RK_S32 cmd_type, void *param); - - -#ifdef __cplusplus -} -#endif - -#endif /*__HAL_H264D_VDPU_REG_H__*/ +#endif /*__HAL_H264D_VDPU_REG_TBL_H__*/