From 273d2bdd926ad543c245c50b33a317c1469c1e1c Mon Sep 17 00:00:00 2001 From: "sayon.chen" Date: Mon, 8 Aug 2022 10:44:49 +0800 Subject: [PATCH] [h265e_ps]: Add auto tile split cfg Auto tile cfg will let encoder auto split picture into tiles according to platform encoder core number. When enabled on RK3588 all picture will be splited into two tiles. Encoder cfg string: h265:auto_tile Change-Id: I3bd91a7781fc2c7e0b43bf2e3be775a5b8098d78 Signed-off-by: sayon.chen --- inc/rk_venc_cmd.h | 2 ++ mpp/base/mpp_enc_cfg.cpp | 3 ++- mpp/codec/enc/h265/h265e_api.c | 3 +++ mpp/codec/enc/h265/h265e_ps.c | 5 ++++- 4 files changed, 11 insertions(+), 2 deletions(-) diff --git a/inc/rk_venc_cmd.h b/inc/rk_venc_cmd.h index a9c7e270..e6e39d91 100644 --- a/inc/rk_venc_cmd.h +++ b/inc/rk_venc_cmd.h @@ -930,6 +930,7 @@ typedef enum MppEncH265CfgChange_e { MPP_ENC_H265_CFG_RC_I_QP_CHANGE = (1 << 19), MPP_ENC_H265_CFG_RC_MAX_QP_STEP_CHANGE = (1 << 21), MPP_ENC_H265_CFG_RC_IP_DELTA_QP_CHANGE = (1 << 20), + MPP_ENC_H265_CFG_TITLE_CHANGE = (1 << 22), MPP_ENC_H265_CFG_CHANGE_ALL = (0xFFFFFFFF), } MppEncH265CfgChange; @@ -1050,6 +1051,7 @@ typedef struct MppEncH265Cfg_t { MppEncH265DblkCfg_t dblk_cfg; MppEncH265RefCfg ref_cfg; MppEncH265MergesCfg merge_cfg; + RK_S32 auto_tile; /* extra info */ MppEncH265VuiCfg vui; diff --git a/mpp/base/mpp_enc_cfg.cpp b/mpp/base/mpp_enc_cfg.cpp index cfcb9616..bd357cb5 100644 --- a/mpp/base/mpp_enc_cfg.cpp +++ b/mpp/base/mpp_enc_cfg.cpp @@ -225,6 +225,7 @@ public: ENTRY(h265, qp_delta_ip, S32, RK_S32, MPP_ENC_RC_CFG_CHANGE_QP_IP, rc, qp_delta_ip) \ ENTRY(h265, sao_luma_disable, S32, RK_S32, MPP_ENC_H265_CFG_SAO_CHANGE, codec.h265, sao_cfg.slice_sao_luma_disable) \ ENTRY(h265, sao_chroma_disable, S32, RK_S32, MPP_ENC_H265_CFG_SAO_CHANGE, codec.h265, sao_cfg.slice_sao_chroma_disable) \ + ENTRY(h265, auto_tile, S32, RK_S32, MPP_ENC_H265_CFG_TITLE_CHANGE, codec.h265, auto_tile) \ /* vp8 config */ \ ENTRY(vp8, qp_init, S32, RK_S32, MPP_ENC_RC_CFG_CHANGE_QP_INIT, rc, qp_init) \ ENTRY(vp8, qp_min, S32, RK_S32, MPP_ENC_RC_CFG_CHANGE_QP_RANGE, rc, qp_min) \ @@ -358,7 +359,7 @@ MppEncCfgService::MppEncCfgService() : MPP_RET ret; RK_S32 i; - ret = mpp_trie_init(&trie, 1622, cfg_cnt); + ret = mpp_trie_init(&trie, 1639, cfg_cnt); if (ret) { mpp_err_f("failed to init enc cfg set trie\n"); return ; diff --git a/mpp/codec/enc/h265/h265e_api.c b/mpp/codec/enc/h265/h265e_api.c index 83e0028c..66bfd744 100644 --- a/mpp/codec/enc/h265/h265e_api.c +++ b/mpp/codec/enc/h265/h265e_api.c @@ -447,6 +447,9 @@ static MPP_RET h265e_proc_h265_cfg(MppEncH265Cfg *dst, MppEncH265Cfg *src) memcpy(&dst->sao_cfg, &src->sao_cfg, sizeof(src->sao_cfg)); } + if (change & MPP_ENC_H265_CFG_TITLE_CHANGE) + dst->auto_tile = src->auto_tile; + /* * NOTE: use OR here for avoiding overwrite on multiple config * When next encoding is trigger the change flag will be clear diff --git a/mpp/codec/enc/h265/h265e_ps.c b/mpp/codec/enc/h265/h265e_ps.c index a77998e3..b1d5ce53 100644 --- a/mpp/codec/enc/h265/h265e_ps.c +++ b/mpp/codec/enc/h265/h265e_ps.c @@ -439,7 +439,10 @@ MPP_RET h265e_set_pps(H265eCtx *ctx, H265ePps *pps, H265eSps *sps) if (strstr(soc_name, "rk3566") || strstr(soc_name, "rk3568")) { pps->m_nNumTileColumnsMinus1 = (sps->m_picWidthInLumaSamples - 1) / 1920 ; } else if (strstr(soc_name, "rk3588")) { - pps->m_nNumTileColumnsMinus1 = (sps->m_picWidthInLumaSamples - 1) / 4096 ; + if (codec->auto_tile) + pps->m_nNumTileColumnsMinus1 = 1; + else + pps->m_nNumTileColumnsMinus1 = (sps->m_picWidthInLumaSamples - 1) / 4096 ; } if (pps->m_nNumTileColumnsMinus1) { pps->m_tiles_enabled_flag = 1;