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https://github.com/nyanmisaka/mpp.git
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[mpp_dec] Calc FBC buffer size on SET_FRAME_INFO
Determine FBC alignment when set frame info control Change-Id: Ibc0c6c455029a58875b820c17b7d94cc4e64cdda Signed-off-by: Rimon Xu <rimon.xu@rock-chips.com>
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@@ -1216,7 +1216,9 @@ MPP_RET vdpu34x_h264d_control(void *hal, MpiCmd cmd_type, void *param)
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if (fmt == MPP_FMT_YUV422SP) {
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mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align_422);
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}
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if (imgwidth > 1920 || imgheight > 1088) {
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if (MPP_FRAME_FMT_IS_FBC(fmt)) {
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vdpu34x_afbc_align_calc(p_hal->frame_slots, (MppFrame)param, 16);
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} else if (imgwidth > 1920 || imgheight > 1088) {
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mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, rkv_hor_align_256_odds);
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}
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break;
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@@ -1375,10 +1375,19 @@ static MPP_RET hal_h265d_vdpu34x_flush(void *hal)
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static MPP_RET hal_h265d_vdpu34x_control(void *hal, MpiCmd cmd_type, void *param)
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{
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MPP_RET ret = MPP_OK;
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HalH265dCtx *p_hal = (HalH265dCtx *)hal;
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(void)hal;
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(void)param;
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switch ((MpiCmd)cmd_type) {
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case MPP_DEC_SET_FRAME_INFO: {
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MppFrame frame = (MppFrame)param;
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MppFrameFormat fmt = mpp_frame_get_fmt(frame);
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if (MPP_FRAME_FMT_IS_FBC(fmt)) {
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vdpu34x_afbc_align_calc(p_hal->slots, frame, 16);
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}
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break;
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}
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case MPP_DEC_SET_OUTPUT_FORMAT: {
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} break;
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default:
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@@ -18,6 +18,7 @@
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#define __VDPU34X_COM_H__
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#include "mpp_device.h"
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#include "mpp_buf_slot.h"
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#include "vdpu34x.h"
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#define OFFSET_COMMON_REGS (8 * sizeof(RK_U32))
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@@ -457,6 +458,7 @@ RK_S32 get_rcb_buf_size(Vdpu34xRcbInfo *info, RK_S32 width, RK_S32 height);
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void vdpu34x_setup_rcb(Vdpu34xRegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdpu34xRcbInfo *info);
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RK_S32 vdpu34x_compare_rcb_size(const void *a, const void *b);
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void vdpu34x_setup_statistic(Vdpu34xRegCommon *com, Vdpu34xRegStatistic *sta);
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void vdpu34x_afbc_align_calc(MppBufSlots slots, MppFrame frame, RK_U32 expand);
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#ifdef __cplusplus
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}
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@@ -21,6 +21,7 @@
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#include "mpp_log.h"
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#include "mpp_buffer.h"
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#include "mpp_common.h"
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#include "mpp_compat_impl.h"
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#include "vdpu34x_com.h"
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@@ -177,3 +178,17 @@ void vdpu34x_setup_statistic(Vdpu34xRegCommon *com, Vdpu34xRegStatistic *sta)
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sta->reg270.bus2mc_buffer_qos_level = 255;
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sta->reg271_wr_wait_cycle_qos = 0;
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}
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void vdpu34x_afbc_align_calc(MppBufSlots slots, MppFrame frame, RK_U32 expand)
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{
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RK_U32 ver_stride = 0;
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RK_U32 img_height = mpp_frame_get_height(frame);
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mpp_slots_set_prop(slots, SLOTS_HOR_ALIGN, mpp_align_64);
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mpp_slots_set_prop(slots, SLOTS_VER_ALIGN, mpp_align_16);
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ver_stride = mpp_align_16(img_height);
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if (*compat_ext_fbc_buf_size) {
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ver_stride += expand;
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}
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mpp_frame_set_ver_stride(frame, ver_stride);
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}
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@@ -1041,21 +1041,26 @@ static MPP_RET hal_vp9d_vdpu34x_flush(void *hal)
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static MPP_RET hal_vp9d_vdpu34x_control(void *hal, MpiCmd cmd_type, void *param)
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{
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HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
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switch ((MpiCmd)cmd_type) {
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case MPP_DEC_SET_FRAME_INFO : {
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/* commit buffer stride */
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RK_U32 width = mpp_frame_get_width((MppFrame)param);
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RK_U32 height = mpp_frame_get_height((MppFrame)param);
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MppFrameFormat fmt = mpp_frame_get_fmt((MppFrame)param);
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mpp_frame_set_hor_stride((MppFrame)param, vp9_hor_align(width));
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mpp_frame_set_ver_stride((MppFrame)param, vp9_ver_align(height));
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if (MPP_FRAME_FMT_IS_FBC(fmt)) {
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vdpu34x_afbc_align_calc(p_hal->slots, (MppFrame)param, 0);
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} else {
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mpp_frame_set_hor_stride((MppFrame)param, vp9_hor_align(width));
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mpp_frame_set_ver_stride((MppFrame)param, vp9_ver_align(height));
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}
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} break;
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default : {
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} break;
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}
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(void)hal;
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return MPP_OK;
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}
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@@ -210,6 +210,8 @@ static __inline RK_U32 mpp_is_32bit()
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}
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RK_S32 axb_div_c(RK_S32 a, RK_S32 b, RK_S32 c);
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RK_U32 mpp_align_16(RK_U32 val);
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RK_U32 mpp_align_64(RK_U32 val);
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#ifdef __cplusplus
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}
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@@ -106,3 +106,13 @@ RK_S32 axb_div_c(RK_S32 a, RK_S32 b, RK_S32 c)
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(RK_U32)c * (RK_U32)b) >> shift) * sign;
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}
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}
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RK_U32 mpp_align_16(RK_U32 val)
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{
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return MPP_ALIGN(val, 16);
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}
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RK_U32 mpp_align_64(RK_U32 val)
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{
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return MPP_ALIGN(val, 64);
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}
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