[mpp_dec] Calc FBC buffer size on SET_FRAME_INFO

Determine FBC alignment when set frame info control

Change-Id: Ibc0c6c455029a58875b820c17b7d94cc4e64cdda
Signed-off-by: Rimon Xu <rimon.xu@rock-chips.com>

mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c

@@ -1216,7 +1216,9 @@ MPP_RET vdpu34x_h264d_control(void *hal, MpiCmd cmd_type, void *param)
         if (fmt == MPP_FMT_YUV422SP) {
             mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align_422);
         }
-        if (imgwidth > 1920 || imgheight > 1088) {
+        if (MPP_FRAME_FMT_IS_FBC(fmt)) {
+            vdpu34x_afbc_align_calc(p_hal->frame_slots, (MppFrame)param, 16);
+        } else if (imgwidth > 1920 || imgheight > 1088) {
             mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, rkv_hor_align_256_odds);
         }
         break;

mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c

@@ -1375,10 +1375,19 @@ static MPP_RET hal_h265d_vdpu34x_flush(void *hal)
 static MPP_RET hal_h265d_vdpu34x_control(void *hal, MpiCmd cmd_type, void *param)
 {
     MPP_RET ret = MPP_OK;
+    HalH265dCtx *p_hal = (HalH265dCtx *)hal;
 
     (void)hal;
-    (void)param;
     switch ((MpiCmd)cmd_type) {
+    case MPP_DEC_SET_FRAME_INFO: {
+        MppFrame frame = (MppFrame)param;
+        MppFrameFormat fmt = mpp_frame_get_fmt(frame);
+
+        if (MPP_FRAME_FMT_IS_FBC(fmt)) {
+            vdpu34x_afbc_align_calc(p_hal->slots, frame, 16);
+        }
+        break;
+    }
     case MPP_DEC_SET_OUTPUT_FORMAT: {
     } break;
     default:

mpp/hal/rkdec/inc/vdpu34x_com.h

@@ -18,6 +18,7 @@
 #define __VDPU34X_COM_H__
 
 #include "mpp_device.h"
+#include "mpp_buf_slot.h"
 #include "vdpu34x.h"
 
 #define OFFSET_COMMON_REGS          (8 * sizeof(RK_U32))
@@ -457,6 +458,7 @@ RK_S32 get_rcb_buf_size(Vdpu34xRcbInfo *info, RK_S32 width, RK_S32 height);
 void vdpu34x_setup_rcb(Vdpu34xRegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdpu34xRcbInfo *info);
 RK_S32 vdpu34x_compare_rcb_size(const void *a, const void *b);
 void vdpu34x_setup_statistic(Vdpu34xRegCommon *com, Vdpu34xRegStatistic *sta);
+void vdpu34x_afbc_align_calc(MppBufSlots slots, MppFrame frame, RK_U32 expand);
 
 #ifdef  __cplusplus
 }

mpp/hal/rkdec/vdpu34x_com.c

@@ -21,6 +21,7 @@
 #include "mpp_log.h"
 #include "mpp_buffer.h"
 #include "mpp_common.h"
+#include "mpp_compat_impl.h"
 
 #include "vdpu34x_com.h"
 
@@ -177,3 +178,17 @@ void vdpu34x_setup_statistic(Vdpu34xRegCommon *com, Vdpu34xRegStatistic *sta)
     sta->reg270.bus2mc_buffer_qos_level = 255;
     sta->reg271_wr_wait_cycle_qos = 0;
 }
+
+void vdpu34x_afbc_align_calc(MppBufSlots slots, MppFrame frame, RK_U32 expand)
+{
+    RK_U32 ver_stride = 0;
+    RK_U32 img_height = mpp_frame_get_height(frame);
+
+    mpp_slots_set_prop(slots, SLOTS_HOR_ALIGN, mpp_align_64);
+    mpp_slots_set_prop(slots, SLOTS_VER_ALIGN, mpp_align_16);
+    ver_stride = mpp_align_16(img_height);
+    if (*compat_ext_fbc_buf_size) {
+        ver_stride += expand;
+    }
+    mpp_frame_set_ver_stride(frame, ver_stride);
+}

mpp/hal/rkdec/vp9d/hal_vp9d_vdpu34x.c

@@ -1041,21 +1041,26 @@ static MPP_RET hal_vp9d_vdpu34x_flush(void *hal)
 
 static MPP_RET hal_vp9d_vdpu34x_control(void *hal, MpiCmd cmd_type, void *param)
 {
+    HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
+
     switch ((MpiCmd)cmd_type) {
     case MPP_DEC_SET_FRAME_INFO : {
         /* commit buffer stride */
         RK_U32 width = mpp_frame_get_width((MppFrame)param);
         RK_U32 height = mpp_frame_get_height((MppFrame)param);
+        MppFrameFormat fmt = mpp_frame_get_fmt((MppFrame)param);
 
-        mpp_frame_set_hor_stride((MppFrame)param, vp9_hor_align(width));
+        if (MPP_FRAME_FMT_IS_FBC(fmt)) {
-        mpp_frame_set_ver_stride((MppFrame)param, vp9_ver_align(height));
+            vdpu34x_afbc_align_calc(p_hal->slots, (MppFrame)param, 0);
+        } else {
+            mpp_frame_set_hor_stride((MppFrame)param, vp9_hor_align(width));
+            mpp_frame_set_ver_stride((MppFrame)param, vp9_ver_align(height));
+        }
     } break;
     default : {
     } break;
     }
 
-    (void)hal;
-
     return MPP_OK;
 }
 

osal/inc/mpp_common.h

@@ -210,6 +210,8 @@ static __inline RK_U32 mpp_is_32bit()
 }
 
 RK_S32 axb_div_c(RK_S32 a, RK_S32 b, RK_S32 c);
+RK_U32 mpp_align_16(RK_U32 val);
+RK_U32 mpp_align_64(RK_U32 val);
 
 #ifdef __cplusplus
 }

osal/mpp_common.cpp

@@ -106,3 +106,13 @@ RK_S32 axb_div_c(RK_S32 a, RK_S32 b, RK_S32 c)
                          (RK_U32)c * (RK_U32)b) >> shift) * sign;
     }
 }
+
+RK_U32 mpp_align_16(RK_U32 val)
+{
+    return MPP_ALIGN(val, 16);
+}
+
+RK_U32 mpp_align_64(RK_U32 val)
+{
+    return MPP_ALIGN(val, 64);
+}