[mpp_enc]: Update osd data cfg

1. Add new structure: MppEncOSDData2
2. Different osd layer use separate buffer

Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I3be533eb602f23192086f56e06a1439dbb19c35c

inc/mpp_meta.h

@@ -78,6 +78,7 @@ typedef enum MppMetaKey_e {
     KEY_LONG_REF_IDX            = FOURCC_META('l', 't', 'i', 'd'),
     KEY_ROI_DATA                = FOURCC_META('r', 'o', 'i', ' '),
     KEY_OSD_DATA                = FOURCC_META('o', 's', 'd', ' '),
+    KEY_OSD_DATA2               = FOURCC_META('o', 's', 'd', '2'),
     KEY_USER_DATA               = FOURCC_META('u', 's', 'r', 'd'),
     KEY_USER_DATAS              = FOURCC_META('u', 'r', 'd', 's'),
 

inc/rk_venc_cmd.h

@@ -1122,6 +1122,22 @@ typedef struct MppEncOSDData_t {
     MppEncOSDRegion     region[8];
 } MppEncOSDData;
 
+typedef struct MppEncOSDRegion2_t {
+    RK_U32              enable;
+    RK_U32              inverse;
+    RK_U32              start_mb_x;
+    RK_U32              start_mb_y;
+    RK_U32              num_mb_x;
+    RK_U32              num_mb_y;
+    RK_U32              buf_offset;
+    MppBuffer           buf;
+} MppEncOSDRegion2;
+
+typedef struct MppEncOSDData2_t {
+    RK_U32              num_region;
+    MppEncOSDRegion2    region[8];
+} MppEncOSDData2;
+
 typedef struct MppEncUserData_t {
     RK_U32              len;
     void                *pdata;

mpp/base/mpp_meta.cpp

@@ -45,6 +45,7 @@ static MppMetaDef meta_defs[] = {
 
     {   KEY_ROI_DATA,           TYPE_PTR,       },
     {   KEY_OSD_DATA,           TYPE_PTR,       },
+    {   KEY_OSD_DATA2,          TYPE_PTR,       },
     {   KEY_USER_DATA,          TYPE_PTR,       },
     {   KEY_USER_DATAS,         TYPE_PTR,       },
     {   KEY_MV_LIST,            TYPE_PTR,       },

mpp/hal/rkenc/common/vepu541_common.c

@@ -528,12 +528,56 @@ typedef struct Vepu541OsdReg_t {
     RK_U32  osd_addr[8];
 } Vepu541OsdReg;
 
+#define SET_OSD_INV_THR(index, reg, region)\
+    if(region[index].inverse)   \
+        reg.osd_ithd_r##index = ENC_DEFAULT_OSD_INV_THR;
+
+static MPP_RET copy2osd2(MppEncOSDData2* dst, MppEncOSDData *src1, MppEncOSDData2 *src2)
+{
+    MPP_RET ret = MPP_OK;
+    RK_U32 i = 0;
+
+    if (src1) {
+        dst->num_region = src1->num_region;
+        for (i = 0; i < src1->num_region; i++) {
+            dst->region[i].enable       = src1->region[i].enable;
+            dst->region[i].inverse      = src1->region[i].inverse;
+            dst->region[i].start_mb_x   = src1->region[i].start_mb_x;
+            dst->region[i].start_mb_y   = src1->region[i].start_mb_y;
+            dst->region[i].num_mb_x     = src1->region[i].num_mb_x;
+            dst->region[i].num_mb_y     = src1->region[i].num_mb_y;
+            dst->region[i].buf_offset   = src1->region[i].buf_offset;
+            dst->region[i].buf          = src1->buf;
+        }
+        ret = MPP_OK;
+    } else if (src2) {
+        memcpy(dst, src2, sizeof(MppEncOSDData2));
+        ret = MPP_OK;
+    } else {
+        ret = MPP_NOK;
+    }
+    return ret;
+}
+
 MPP_RET vepu541_set_osd(Vepu541OsdCfg *cfg)
 {
     Vepu541OsdReg *regs = (Vepu541OsdReg *)(cfg->reg_base + (size_t)VEPU541_OSD_CFG_OFFSET);
     MppDev dev = cfg->dev;
     MppEncOSDPltCfg *plt_cfg = cfg->plt_cfg;
-    MppEncOSDData *osd = cfg->osd_data;
+    MppEncOSDData2 osd;
+
+    if (copy2osd2(&osd, cfg->osd_data, cfg->osd_data2))
+        return MPP_NOK;
+
+    if (osd.num_region == 0)
+        return MPP_OK;
+
+    if (osd.num_region > 8) {
+        mpp_err_f("do NOT support more than 8 regions invalid num %d\n",
+                  osd.num_region);
+        mpp_assert(osd.num_region <= 8);
+        return MPP_NOK;
+    }
 
     if (plt_cfg->type == MPP_ENC_OSD_PLT_TYPE_USERDEF) {
         MppDevRegWrCfg wr_cfg;
@@ -554,49 +598,38 @@ MPP_RET vepu541_set_osd(Vepu541OsdCfg *cfg)
     regs->reg112.osd_e = 0;
     regs->reg112.osd_inv_e = 0;
 
-    if (NULL == osd || osd->num_region == 0 || NULL == osd->buf)
+    RK_U32 i = 0;
-        return MPP_OK;
+    MppEncOSDRegion2 *region = osd.region;
+    MppEncOSDRegion2 *tmp = region;
+    RK_U32 num = osd.num_region;
 
-    if (osd->num_region > 8) {
+    for (i = 0; i < num; i++, tmp++) {
-        mpp_err_f("do NOT support more than 8 regions invalid num %d\n",
+        regs->reg112.osd_e      |= tmp->enable << i;
-                  osd->num_region);
+        regs->reg112.osd_inv_e  |= tmp->inverse << i;
-        mpp_assert(osd->num_region <= 8);
-        return MPP_NOK;
-    }
-
-    MppBuffer buf = osd->buf;
-    RK_S32 fd = mpp_buffer_get_fd(buf);
-    if (fd < 0) {
-        mpp_err_f("invalid osd buffer fd %d\n", fd);
-        return MPP_NOK;
-    }
-
-    size_t buf_size = mpp_buffer_get_size(buf);
-    RK_U32 num = osd->num_region;
-    RK_U32 k = 0;
-    MppEncOSDRegion *region = osd->region;
-    MppEncOSDRegion *tmp = region;
-
-    for (k = 0; k < num; k++, tmp++) {
-        regs->reg112.osd_e      |= tmp->enable << k;
-        regs->reg112.osd_inv_e  |= tmp->inverse << k;
 
         if (tmp->enable && tmp->num_mb_x && tmp->num_mb_y) {
-            Vepu541OsdPos *pos = &regs->osd_pos[k];
+            Vepu541OsdPos *pos = &regs->osd_pos[i];
             size_t blk_len = tmp->num_mb_x * tmp->num_mb_y * 256;
+            RK_S32 fd = 0;
+            RK_U32 buf_size = 0;
 
             pos->osd_lt_x = tmp->start_mb_x;
             pos->osd_lt_y = tmp->start_mb_y;
             pos->osd_rb_x = tmp->start_mb_x + tmp->num_mb_x - 1;
             pos->osd_rb_y = tmp->start_mb_y + tmp->num_mb_y - 1;
 
-            regs->osd_addr[k] = fd;
+            buf_size = mpp_buffer_get_size(tmp->buf);
-
+            fd = mpp_buffer_get_fd(tmp->buf);
+            if (fd < 0) {
+                mpp_err_f("invalid osd buffer fd %d\n", fd);
+                return MPP_NOK;
+            }
+            regs->osd_addr[i] = fd;
 
             if (tmp->buf_offset) {
                 MppDevRegOffsetCfg trans_cfg;
 
-                trans_cfg.reg_idx = VEPU541_OSD_ADDR_IDX_BASE + k;
+                trans_cfg.reg_idx = VEPU541_OSD_ADDR_IDX_BASE + i;
                 trans_cfg.offset = tmp->buf_offset;
                 mpp_dev_ioctl(cfg->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
             }
@@ -605,28 +638,20 @@ MPP_RET vepu541_set_osd(Vepu541OsdCfg *cfg)
             if (buf_size < tmp->buf_offset + blk_len ||
                 (tmp->buf_offset & 0xf)) {
                 mpp_err_f("invalid osd cfg: %d x:y:w:h:off %d:%d:%d:%d:%x\n",
-                          k, tmp->start_mb_x, tmp->start_mb_y,
+                          i, tmp->start_mb_x, tmp->start_mb_y,
                           tmp->num_mb_x, tmp->num_mb_y, tmp->buf_offset);
             }
         }
     }
 
-    if (region[0].inverse)
+    SET_OSD_INV_THR(0, regs->reg113, region);
-        regs->reg113.osd_ithd_r0 = ENC_DEFAULT_OSD_INV_THR;
+    SET_OSD_INV_THR(1, regs->reg113, region);
-    if (region[1].inverse)
+    SET_OSD_INV_THR(2, regs->reg113, region);
-        regs->reg113.osd_ithd_r1 = ENC_DEFAULT_OSD_INV_THR;
+    SET_OSD_INV_THR(3, regs->reg113, region);
-    if (region[2].inverse)
+    SET_OSD_INV_THR(4, regs->reg113, region);
-        regs->reg113.osd_ithd_r2 = ENC_DEFAULT_OSD_INV_THR;
+    SET_OSD_INV_THR(5, regs->reg113, region);
-    if (region[3].inverse)
+    SET_OSD_INV_THR(6, regs->reg113, region);
-        regs->reg113.osd_ithd_r3 = ENC_DEFAULT_OSD_INV_THR;
+    SET_OSD_INV_THR(7, regs->reg113, region);
-    if (region[4].inverse)
-        regs->reg113.osd_ithd_r4 = ENC_DEFAULT_OSD_INV_THR;
-    if (region[5].inverse)
-        regs->reg113.osd_ithd_r5 = ENC_DEFAULT_OSD_INV_THR;
-    if (region[6].inverse)
-        regs->reg113.osd_ithd_r6 = ENC_DEFAULT_OSD_INV_THR;
-    if (region[7].inverse)
-        regs->reg113.osd_ithd_r7 = ENC_DEFAULT_OSD_INV_THR;
 
     return MPP_OK;
 }
@@ -743,7 +768,20 @@ MPP_RET vepu540_set_osd(Vepu541OsdCfg *cfg)
     Vepu540OsdReg *regs = (Vepu540OsdReg *)(cfg->reg_base + (size_t)VEPU540_OSD_CFG_OFFSET);
     MppDev dev = cfg->dev;
     MppEncOSDPltCfg *plt_cfg = cfg->plt_cfg;
-    MppEncOSDData *osd = cfg->osd_data;
+    MppEncOSDData2 osd;
+
+    if (copy2osd2(&osd, cfg->osd_data, cfg->osd_data2))
+        return MPP_NOK;
+
+    if (osd.num_region == 0)
+        return MPP_OK;
+
+    if (osd.num_region > 8) {
+        mpp_err_f("do NOT support more than 8 regions invalid num %d\n",
+                  osd.num_region);
+        mpp_assert(osd.num_region <= 8);
+        return MPP_NOK;
+    }
 
     if (plt_cfg->type == MPP_ENC_OSD_PLT_TYPE_USERDEF) {
         MppDevRegWrCfg wr_cfg;
@@ -765,27 +803,10 @@ MPP_RET vepu540_set_osd(Vepu541OsdCfg *cfg)
     regs->reg094.osd_ch_inv_en = 0;
     regs->reg094.osd_lu_inv_msk = 0;
 
-    if (NULL == osd || osd->num_region == 0 || NULL == osd->buf)
+    RK_U32 num = osd.num_region;
-        return MPP_OK;
-    if (osd->num_region > 8) {
-        mpp_err_f("do NOT support more than 8 regions invalid num %d\n",
-                  osd->num_region);
-        mpp_assert(osd->num_region <= 8);
-        return MPP_NOK;
-    }
-
-    MppBuffer buf = osd->buf;
-    RK_S32 fd = mpp_buffer_get_fd(buf);
-    if (fd < 0) {
-        mpp_err_f("invalid osd buffer fd %d\n", fd);
-        return MPP_NOK;
-    }
-
-    size_t buf_size = mpp_buffer_get_size(buf);
-    RK_U32 num = osd->num_region;
     RK_U32 k = 0;
-    MppEncOSDRegion *region = osd->region;
+    MppEncOSDRegion2 *region = osd.region;
-    MppEncOSDRegion *tmp = region;
+    MppEncOSDRegion2 *tmp = region;
 
     for (k = 0; k < num; k++, tmp++) {
         regs->reg112.osd_e          |= tmp->enable << k;
@@ -795,12 +816,20 @@ MPP_RET vepu540_set_osd(Vepu541OsdCfg *cfg)
         if (tmp->enable && tmp->num_mb_x && tmp->num_mb_y) {
             Vepu541OsdPos *pos = &regs->osd_pos[k];
             size_t blk_len = tmp->num_mb_x * tmp->num_mb_y * 256;
+            RK_S32 fd = -1;
+            size_t buf_size = 0;
 
             pos->osd_lt_x = tmp->start_mb_x;
             pos->osd_lt_y = tmp->start_mb_y;
             pos->osd_rb_x = tmp->start_mb_x + tmp->num_mb_x - 1;
             pos->osd_rb_y = tmp->start_mb_y + tmp->num_mb_y - 1;
 
+            buf_size = mpp_buffer_get_size(tmp->buf);
+            fd = mpp_buffer_get_fd(tmp->buf);
+            if (fd < 0) {
+                mpp_err_f("invalid osd buffer fd %d\n", fd);
+                return MPP_NOK;
+            }
             regs->osd_addr[k] = fd;
 
             if (tmp->buf_offset) {
@@ -821,22 +850,14 @@ MPP_RET vepu540_set_osd(Vepu541OsdCfg *cfg)
         }
     }
 
-    if (region[0].inverse)
+    SET_OSD_INV_THR(0, regs->reg113, region);
-        regs->reg113.osd_ithd_r0 = ENC_DEFAULT_OSD_INV_THR;
+    SET_OSD_INV_THR(1, regs->reg113, region);
-    if (region[1].inverse)
+    SET_OSD_INV_THR(2, regs->reg113, region);
-        regs->reg113.osd_ithd_r1 = ENC_DEFAULT_OSD_INV_THR;
+    SET_OSD_INV_THR(3, regs->reg113, region);
-    if (region[2].inverse)
+    SET_OSD_INV_THR(4, regs->reg113, region);
-        regs->reg113.osd_ithd_r2 = ENC_DEFAULT_OSD_INV_THR;
+    SET_OSD_INV_THR(5, regs->reg113, region);
-    if (region[3].inverse)
+    SET_OSD_INV_THR(6, regs->reg113, region);
-        regs->reg113.osd_ithd_r3 = ENC_DEFAULT_OSD_INV_THR;
+    SET_OSD_INV_THR(7, regs->reg113, region);
-    if (region[4].inverse)
-        regs->reg113.osd_ithd_r4 = ENC_DEFAULT_OSD_INV_THR;
-    if (region[5].inverse)
-        regs->reg113.osd_ithd_r5 = ENC_DEFAULT_OSD_INV_THR;
-    if (region[6].inverse)
-        regs->reg113.osd_ithd_r6 = ENC_DEFAULT_OSD_INV_THR;
-    if (region[7].inverse)
-        regs->reg113.osd_ithd_r7 = ENC_DEFAULT_OSD_INV_THR;
 
     return MPP_OK;
 }

mpp/hal/rkenc/common/vepu541_common.h

@@ -132,6 +132,7 @@ typedef struct Vepu541OsdCfg_t {
     MppDev              dev;
     MppEncOSDPltCfg     *plt_cfg;
     MppEncOSDData       *osd_data;
+    MppEncOSDData2      *osd_data2;
 } Vepu541OsdCfg;
 
 #ifdef __cplusplus

mpp/hal/rkenc/h264e/hal_h264e_vepu541.c

@@ -164,6 +164,7 @@ static MPP_RET hal_h264e_vepu541_init(void *hal, MppEncHalCfg *cfg)
     p->osd_cfg.dev = p->dev;
     p->osd_cfg.plt_cfg = &p->cfg->plt_cfg;
     p->osd_cfg.osd_data = NULL;
+    p->osd_cfg.osd_data2 = NULL;
 
 DONE:
     if (ret)
@@ -303,6 +304,7 @@ static MPP_RET hal_h264e_vepu541_get_task(void *hal, HalEncTask *task)
 
         mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
         mpp_meta_get_ptr(meta, KEY_OSD_DATA, (void **)&ctx->osd_cfg.osd_data);
+        mpp_meta_get_ptr(meta, KEY_OSD_DATA2, (void **)&ctx->osd_cfg.osd_data2);
     }
     hal_h264e_dbg_func("leave %p\n", hal);
 

mpp/hal/rkenc/h265e/hal_h265e_vepu541.c

@@ -630,6 +630,7 @@ MPP_RET hal_h265e_v541_init(void *hal, MppEncHalCfg *cfg)
     ctx->osd_cfg.dev = ctx->dev;
     ctx->osd_cfg.plt_cfg = &ctx->cfg->plt_cfg;
     ctx->osd_cfg.osd_data = NULL;
+    ctx->osd_cfg.osd_data2 = NULL;
 
     ctx->frame_type = INTRA_FRAME;
     hal_h265e_leave();
@@ -1826,6 +1827,7 @@ MPP_RET hal_h265e_v541_get_task(void *hal, HalEncTask *task)
         MppMeta meta = mpp_frame_get_meta(frame);
         mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
         mpp_meta_get_ptr(meta, KEY_OSD_DATA, (void **)&ctx->osd_cfg.osd_data);
+        mpp_meta_get_ptr(meta, KEY_OSD_DATA2, (void **)&ctx->osd_cfg.osd_data2);
     }
     memset(&ctx->feedback, 0, sizeof(vepu541_h265_fbk));