diff --git a/inc/mpp_rc_defs.h b/inc/mpp_rc_defs.h index 9eb93f01..c5643f2d 100644 --- a/inc/mpp_rc_defs.h +++ b/inc/mpp_rc_defs.h @@ -184,6 +184,7 @@ typedef struct EncRcCommonInfo_t { /* rc to hal */ RK_S32 bit_target; + RK_S32 bit_target_fix; RK_S32 bit_max; RK_S32 bit_min; diff --git a/inc/rk_venc_cmd.h b/inc/rk_venc_cmd.h index 70d963dd..4bd7ab92 100644 --- a/inc/rk_venc_cmd.h +++ b/inc/rk_venc_cmd.h @@ -1433,7 +1433,12 @@ typedef enum MppEncFineTuneCfgChange_e { MPP_ENC_TUNE_CFG_CHANGE_DEBLUR_STR = (1 << 2), MPP_ENC_TUNE_CFG_CHANGE_ANTI_FLICKER_STR = (1 << 3), MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_I = (1 << 5), - MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_P = (1 << 6) + MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_P = (1 << 6), + MPP_ENC_TUNE_CFG_CHANGE_ATR_STR_I = (1 << 7), + MPP_ENC_TUNE_CFG_CHANGE_ATR_STR_P = (1 << 8), + MPP_ENC_TUNE_CFG_CHANGE_ATL_STR = (1 << 9), + MPP_ENC_TUNE_CFG_CHANGE_SAO_STR_I = (1 << 10), + MPP_ENC_TUNE_CFG_CHANGE_SAO_STR_P = (1 << 11) } MppEncFineTuneCfgChange; typedef struct MppEncFineTuneCfg_t { @@ -1445,6 +1450,11 @@ typedef struct MppEncFineTuneCfg_t { RK_S32 anti_flicker_str; RK_S32 lambda_idx_i; RK_S32 lambda_idx_p; + RK_S32 atr_str_i;/* line_en */ + RK_S32 atr_str_p;/* line_en */ + RK_S32 atl_str;/* anti_stripe */ + RK_S32 sao_str_i;/* anti blur */ + RK_S32 sao_str_p;/* anti blur */ } MppEncFineTuneCfg; #endif /*__RK_VENC_CMD_H__*/ diff --git a/mpp/base/mpp_enc_cfg.cpp b/mpp/base/mpp_enc_cfg.cpp index 457d4303..a378f85d 100644 --- a/mpp/base/mpp_enc_cfg.cpp +++ b/mpp/base/mpp_enc_cfg.cpp @@ -261,7 +261,12 @@ public: ENTRY(tune, deblur_str, S32, RK_S32, MPP_ENC_TUNE_CFG_CHANGE_DEBLUR_STR, tune, deblur_str) \ ENTRY(tune, anti_flicker_str,S32, RK_S32, MPP_ENC_TUNE_CFG_CHANGE_ANTI_FLICKER_STR,tune, anti_flicker_str) \ ENTRY(tune, lambda_idx_i, S32, RK_S32, MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_I, tune, lambda_idx_i) \ - ENTRY(tune, lambda_idx_p, S32, RK_S32, MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_P, tune, lambda_idx_p) + ENTRY(tune, lambda_idx_p, S32, RK_S32, MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_P, tune, lambda_idx_p) \ + ENTRY(tune, atr_str_i, S32, RK_S32, MPP_ENC_TUNE_CFG_CHANGE_ATR_STR_I, tune, atr_str_i) \ + ENTRY(tune, atr_str_p, S32, RK_S32, MPP_ENC_TUNE_CFG_CHANGE_ATR_STR_P, tune, atr_str_p) \ + ENTRY(tune, atl_str, S32, RK_S32, MPP_ENC_TUNE_CFG_CHANGE_ATL_STR, tune, atl_str) \ + ENTRY(tune, sao_str_i, S32, RK_S32, MPP_ENC_TUNE_CFG_CHANGE_SAO_STR_I, tune, sao_str_i) \ + ENTRY(tune, sao_str_p, S32, RK_S32, MPP_ENC_TUNE_CFG_CHANGE_SAO_STR_P, tune, sao_str_p) static void mpp_enc_cfg_fill(MppTrie trie, MppCfgApi **cfgs) { diff --git a/mpp/codec/enc/h265/h265e_api.c b/mpp/codec/enc/h265/h265e_api.c index 5de1e93e..142da68e 100644 --- a/mpp/codec/enc/h265/h265e_api.c +++ b/mpp/codec/enc/h265/h265e_api.c @@ -113,6 +113,11 @@ static MPP_RET h265e_init(void *ctx, EncImplCfg *ctrlCfg) p->cfg->tune.lambda_idx_i = 2; p->cfg->tune.lambda_idx_p = 4; p->cfg->tune.anti_flicker_str = 2; + p->cfg->tune.atr_str_i = 3; + p->cfg->tune.atr_str_p = 0; + p->cfg->tune.atl_str = 1; + p->cfg->tune.sao_str_i = 0; + p->cfg->tune.sao_str_p = 1; /* * default prep: diff --git a/mpp/codec/mpp_enc_impl.cpp b/mpp/codec/mpp_enc_impl.cpp index 04987400..508861d0 100644 --- a/mpp/codec/mpp_enc_impl.cpp +++ b/mpp/codec/mpp_enc_impl.cpp @@ -886,6 +886,46 @@ MPP_RET mpp_enc_proc_tune_cfg(MppEncFineTuneCfg *dst, MppEncFineTuneCfg *src) ret = MPP_ERR_VALUE; } + if (change & MPP_ENC_TUNE_CFG_CHANGE_ATR_STR_I) + dst->atr_str_i = src->atr_str_i; + + if (dst->atr_str_i < 0 || dst->atr_str_i > 3) { + mpp_err("invalid atr_str not in range [0 : 3]\n"); + ret = MPP_ERR_VALUE; + } + + if (change & MPP_ENC_TUNE_CFG_CHANGE_ATR_STR_P) + dst->atr_str_p = src->atr_str_p; + + if (dst->atr_str_p < 0 || dst->atr_str_p > 3) { + mpp_err("invalid atr_str not in range [0 : 3]\n"); + ret = MPP_ERR_VALUE; + } + + if (change & MPP_ENC_TUNE_CFG_CHANGE_ATL_STR) + dst->atl_str = src->atl_str; + + if (dst->atl_str < 0 || dst->atl_str > 3) { + mpp_err("invalid atr_str not in range [0 : 3]\n"); + ret = MPP_ERR_VALUE; + } + + if (change & MPP_ENC_TUNE_CFG_CHANGE_SAO_STR_I) + dst->sao_str_i = src->sao_str_i; + + if (dst->sao_str_i < 0 || dst->sao_str_i > 3) { + mpp_err("invalid atr_str not in range [0 : 3]\n"); + ret = MPP_ERR_VALUE; + } + + if (change & MPP_ENC_TUNE_CFG_CHANGE_SAO_STR_P) + dst->sao_str_p = src->sao_str_p; + + if (dst->sao_str_p < 0 || dst->sao_str_p > 3) { + mpp_err("invalid atr_str not in range [0 : 3]\n"); + ret = MPP_ERR_VALUE; + } + if (change & MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_I) dst->lambda_idx_i = src->lambda_idx_i; diff --git a/mpp/codec/rc/rc_ctx.h b/mpp/codec/rc/rc_ctx.h index 6a8d4033..0fc1ffc4 100644 --- a/mpp/codec/rc/rc_ctx.h +++ b/mpp/codec/rc/rc_ctx.h @@ -52,9 +52,14 @@ typedef struct RcModelV2Ctx_t { MppDataV2 *pre_i_mean_qp; MppDataV2 *madi; MppDataV2 *madp; + MppDataV2 *motion_level; + MppDataV2 *complex_level; RK_S32 target_bps; RK_S32 pre_target_bits; + RK_S32 pre_target_bits_fix; + RK_S64 pre_target_bits_fix_count; + RK_S64 pre_real_bits_count; RK_S32 pre_real_bits; RK_S32 frm_bits_thr; RK_S32 ins_bps; diff --git a/mpp/codec/rc/rc_model_v2.c b/mpp/codec/rc/rc_model_v2.c index 86dde8b4..b367ad75 100644 --- a/mpp/codec/rc/rc_model_v2.c +++ b/mpp/codec/rc/rc_model_v2.c @@ -30,6 +30,7 @@ #define I_WINDOW_LEN 2 #define P_WINDOW1_LEN 5 #define P_WINDOW2_LEN 8 +#define MAX_BIT_COUNT_VALUE 1000000000000000 static const RK_S32 max_i_delta_qp[51] = { 640, 640, 640, 640, 640, 640, 640, 640, 640, 640, 640, 640, 640, 640, @@ -129,6 +130,14 @@ MPP_RET bits_model_param_deinit(RcModelV2Ctx *ctx) mpp_data_deinit_v2(ctx->gop_bits); ctx->gop_bits = NULL; } + if (ctx->motion_level != NULL) { + mpp_data_deinit_v2(ctx->motion_level); + ctx->motion_level = NULL; + } + if (ctx->complex_level != NULL) { + mpp_data_deinit_v2(ctx->complex_level); + ctx->complex_level = NULL; + } rc_dbg_func("leave %p\n", ctx); return MPP_OK; } @@ -137,6 +146,7 @@ MPP_RET bits_model_param_init(RcModelV2Ctx *ctx) { RK_S32 gop_len = ctx->usr_cfg.igop; RcFpsCfg *fps = &ctx->usr_cfg.fps; + RK_S32 mad_len = 10; RK_U32 stat_len = fps->fps_out_num * ctx->usr_cfg.stats_time / fps->fps_out_denom; stat_len = stat_len ? stat_len : 1; @@ -210,6 +220,19 @@ MPP_RET bits_model_param_init(RcModelV2Ctx *ctx) return MPP_ERR_MALLOC; } } + + mpp_data_init_v2(&ctx->motion_level, mad_len, 0); + if (ctx->motion_level == NULL) { + mpp_err("motion_level init fail mad_len %d\n", mad_len); + return MPP_ERR_MALLOC; + } + + mpp_data_init_v2(&ctx->complex_level, mad_len, 0); + if (ctx->complex_level == NULL) { + mpp_err("complex_level init fail mad_len %d\n", mad_len); + return MPP_ERR_MALLOC; + } + return MPP_OK; } @@ -431,6 +454,7 @@ MPP_RET bits_model_alloc(RcModelV2Ctx *ctx, EncRcTaskInfo *cfg, RK_S64 total_bit RK_S32 vi_scale = ctx->vi_scale; RK_S32 alloc_bits = 0; RK_S32 super_bit_thr = 0x7fffffff; + RK_S64 total_bits_fix = total_bits; ctx->i_scale = 80 * ctx->i_sumbits / (2 * ctx->p_sumbits); i_scale = ctx->i_scale; @@ -519,6 +543,10 @@ MPP_RET bits_model_alloc(RcModelV2Ctx *ctx, EncRcTaskInfo *cfg, RK_S64 total_bit ctx->cur_super_thd = super_bit_thr; cfg->bit_target = alloc_bits; + if (cfg->frame_type == INTRA_FRAME) + cfg->bit_target_fix = total_bits_fix * 240 / (240 + 16 * (gop_len - 1)); + else + cfg->bit_target_fix = total_bits_fix * 16 / (240 + 16 * (gop_len - 1)); mpp_assert(alloc_bits); @@ -613,6 +641,13 @@ MPP_RET calc_cbr_ratio(void *ctx, EncRcTaskInfo *cfg) mpp_assert(target_bps > 0); + p->pre_real_bits_count = p->pre_real_bits_count + pre_real_bits; + p->pre_target_bits_fix_count = p->pre_target_bits_fix_count + p->pre_target_bits_fix; + if (p->pre_real_bits_count > MAX_BIT_COUNT_VALUE || p->pre_target_bits_fix_count > MAX_BIT_COUNT_VALUE) { + p->pre_real_bits_count = 0; + p->pre_target_bits_fix_count = 0; + } + if (pre_target_bits > pre_real_bits) bit_diff_ratio = 52 * (pre_real_bits - pre_target_bits) / pre_target_bits; else @@ -1487,6 +1522,10 @@ MPP_RET rc_model_v2_hal_start(void *ctx, EncRcTask *task) RK_S32 quality_min = info->quality_min; RK_S32 quality_max = info->quality_max; RK_S32 quality_target = info->quality_target; + RK_S32 min_i_frame_qp = usr_cfg->fqp_min_i; + RK_S32 min_p_frame_qp = usr_cfg->fqp_min_p; + RK_S32 max_i_frame_qp = usr_cfg->fqp_max_i; + RK_S32 max_p_frame_qp = usr_cfg->fqp_max_p; rc_dbg_func("enter p %p task %p\n", p, task); @@ -1516,6 +1555,8 @@ MPP_RET rc_model_v2_hal_start(void *ctx, EncRcTask *task) /* setup quality parameters */ if (p->first_frm_flg && frm->is_intra) { RK_S32 i_quality_delta = usr_cfg->i_quality_delta; + p->pre_target_bits_fix_count = 0; + p->pre_real_bits_count = 0; if (info->quality_target < 0) { if (info->bit_target) { @@ -1541,12 +1582,55 @@ MPP_RET rc_model_v2_hal_start(void *ctx, EncRcTask *task) } else { RK_S32 qp_scale = p->cur_scale_qp + p->next_ratio; RK_S32 start_qp = 0; + RK_S32 qpmin = 26; + RK_S32 cplx = mpp_data_sum_v2(p->complex_level); + RK_S32 md = mpp_data_sum_v2(p->motion_level); + RK_S32 md3 = mpp_data_get_pre_val_v2(p->motion_level, 0) + mpp_data_get_pre_val_v2(p->motion_level, + 1) + mpp_data_get_pre_val_v2(p->motion_level, 2); + + if (RC_AVBR == usr_cfg->mode || RC_VBR == usr_cfg->mode || RC_CBR == usr_cfg->mode) { + if (md >= 700) { + if (md >= 1400) + qpmin = (frm->is_intra ? min_i_frame_qp : min_p_frame_qp) + (md3 > 300 ? 3 : 2); + else + qpmin = (frm->is_intra ? min_i_frame_qp : min_p_frame_qp) + (md3 > 300 ? 2 : 1); + + if (cplx >= 15) + qpmin ++; + } else if (RC_CBR != usr_cfg->mode) { + if (md > 100) { + if (cplx >= 16) + qpmin = (frm->is_intra ? min_i_frame_qp : min_p_frame_qp) + 1; + else if (cplx >= 10) + qpmin = (frm->is_intra ? min_i_frame_qp : min_p_frame_qp) + 0; + } else { + qpmin = (frm->is_intra ? min_i_frame_qp : min_p_frame_qp); + if (cplx >= 15) + qpmin += 3; + else if (cplx >= 10) + qpmin += 2; + else if (cplx >= 5) + qpmin += 1; + } + } + if (qpmin > info->quality_max) + qpmin = info->quality_max; + if (qpmin < info->quality_min) + qpmin = info->quality_min; + } if (frm->is_intra && !frm->is_i_refresh) { RK_S32 i_quality_delta = usr_cfg->i_quality_delta; + RK_S32 qp_scale_t = qp_scale = + mpp_clip(qp_scale, (info->quality_min << 6), (info->quality_max << 6)); + + qp_scale_t = (qp_scale + p->next_i_ratio) >> 6; + if (qp_scale_t >= 35 && p->pre_i_qp <= 33) + start_qp = (p->pre_i_qp * 307 + qp_scale_t * 717) >> 10; + else + start_qp = (p->pre_i_qp + qp_scale_t) >> 1; + - qp_scale = mpp_clip(qp_scale, (info->quality_min << 6), (info->quality_max << 6)); - start_qp = ((p->pre_i_qp + ((qp_scale + p->next_i_ratio) >> 6)) >> 1); if (i_quality_delta) { RK_U32 index = mpp_clip(mpp_data_mean_v2(p->madi) / 4, 0, 7); @@ -1560,10 +1644,12 @@ MPP_RET rc_model_v2_hal_start(void *ctx, EncRcTask *task) usr_cfg->i_quality_delta, max_ip_delta, start_qp - i_quality_delta, p->reenc_cnt); - if (!p->reenc_cnt) { - start_qp -= i_quality_delta; - } + //if (!p->reenc_cnt) { + start_qp -= i_quality_delta; + //} } + start_qp = mpp_clip(start_qp, qpmin, info->quality_max); + start_qp = mpp_clip(start_qp, qpmin, max_i_frame_qp); start_qp = mpp_clip(start_qp, info->quality_min, info->quality_max); p->start_qp = start_qp; @@ -1573,13 +1659,12 @@ MPP_RET rc_model_v2_hal_start(void *ctx, EncRcTask *task) if (p->usr_cfg.debreath_cfg.enable) { calc_debreath_qp(ctx); } - } else { - p->cur_scale_qp = qp_scale; } p->gop_frm_cnt = 0; p->gop_qp_sum = 0; } else { + qp_scale = mpp_clip(qp_scale, (qpmin << 6), (info->quality_max << 6)); qp_scale = mpp_clip(qp_scale, (info->quality_min << 6), (info->quality_max << 6)); p->cur_scale_qp = qp_scale; rc_dbg_rc("qp %d -> %d\n", p->start_qp, qp_scale >> 6); @@ -1588,7 +1673,16 @@ MPP_RET rc_model_v2_hal_start(void *ctx, EncRcTask *task) rc_dbg_rc("qp %d -> %d (vi)\n", p->start_qp, p->start_qp - usr_cfg->vi_quality_delta); p->start_qp -= usr_cfg->vi_quality_delta; } + p->start_qp = mpp_clip(p->start_qp, qpmin, max_p_frame_qp); } + if (p->pre_target_bits_fix_count * 90 / 100 > p->pre_real_bits_count) { + p->start_qp = mpp_clip(p->start_qp, info->quality_min, 35); + } else if (p->pre_target_bits_fix_count * 100 / 100 > p->pre_real_bits_count) { + p->start_qp = mpp_clip(p->start_qp, info->quality_min, 37); + } else if (p->pre_target_bits_fix_count * 107 / 100 > p->pre_real_bits_count) { + p->start_qp = mpp_clip(p->start_qp, info->quality_min, 39); + } + p->start_qp = mpp_clip(p->start_qp, qpmin, 51); } if (usr_cfg->hier_qp_cfg.hier_qp_en && !p->reenc_cnt) { @@ -1705,6 +1799,9 @@ MPP_RET rc_model_v2_end(void *ctx, EncRcTask *task) if (usr_cfg->mode == RC_FIXQP) goto DONE; + rc_dbg_rc("motion_level %u, complex_level %u\n", cfg->motion_level, cfg->complex_level); + mpp_data_update_v2(p->motion_level, cfg->motion_level); + mpp_data_update_v2(p->complex_level, cfg->complex_level); cfg->rt_bits = p->ins_bps; p->last_inst_bps = p->ins_bps; p->first_frm_flg = 0; @@ -1723,6 +1820,7 @@ MPP_RET rc_model_v2_end(void *ctx, EncRcTask *task) p->scale_qp = p->cur_scale_qp; p->prev_md_prop = 0; p->pre_target_bits = cfg->bit_target; + p->pre_target_bits_fix = cfg->bit_target_fix; p->pre_real_bits = cfg->bit_real; p->on_drop = 0; diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu510.c b/mpp/hal/rkenc/h265e/hal_h265e_vepu510.c index 1624bb6c..5775b7b9 100644 --- a/mpp/hal/rkenc/h265e/hal_h265e_vepu510.c +++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu510.c @@ -58,6 +58,10 @@ typedef struct Vepu510H265Fbk_t { RK_U32 st_mb_num; RK_U32 st_ctu_num; RK_U32 st_smear_cnt[5]; + RK_S32 reg_idx; + RK_U32 acc_cover16_num; + RK_U32 acc_bndry16_num; + RK_U32 acc_zero_mv; RK_S8 tgt_sub_real_lvl[6]; } Vepu510H265Fbk; @@ -184,6 +188,28 @@ static RK_S32 atf_b16_intra_wgt0[4] = {16, 22, 27, 28}; static RK_S32 atf_b16_intra_wgt1[4] = {16, 20, 25, 26}; static RK_S32 atf_b16_intra_wgt2[4] = {16, 18, 20, 24}; +static RK_S32 smear_qp_strength[8] = {4, 6, 7, 7, 3, 5, 7, 7}; +static RK_S32 smear_strength[8] = {1, 1, 1, 1, 1, 1, 1, 1}; +static RK_S32 smear_common_intra_r_dep0[8] = {224, 224, 200, 200, 224, 224, 200, 200}; +static RK_S32 smear_common_intra_r_dep1[8] = {224, 224, 180, 200, 224, 224, 180, 200}; +static RK_S32 smear_bndry_intra_r_dep0[8] = {240, 240, 240, 240, 240, 240, 240, 240}; +static RK_S32 smear_bndry_intra_r_dep1[8] = {240, 240, 240, 240, 240, 240, 240, 240}; +static RK_S32 smear_thre_madp_stc_cover0[8] = {20, 22, 22, 22, 20, 22, 22, 30}; +static RK_S32 smear_thre_madp_stc_cover1[8] = {20, 22, 22, 22, 20, 22, 22, 30}; +static RK_S32 smear_thre_madp_mov_cover0[8] = {10, 9, 9, 9, 10, 9, 9, 6}; +static RK_S32 smear_thre_madp_mov_cover1[8] = {10, 9, 9, 9, 10, 9, 9, 6}; + +static RK_S32 smear_flag_cover_thd0[8] = {12, 13, 13, 13, 12, 13, 13, 17}; +static RK_S32 smear_flag_cover_thd1[8] = {61, 70, 70, 70, 61, 70, 70, 90}; +static RK_S32 smear_flag_bndry_thd0[8] = {12, 12, 12, 12, 12, 12, 12, 12}; +static RK_S32 smear_flag_bndry_thd1[8] = {73, 73, 73, 73, 73, 73, 73, 73}; + +static RK_S32 smear_flag_cover_wgt[3] = {1, 0, -3}; +static RK_S32 smear_flag_cover_intra_wgt0[3] = { -12, 0, 12}; +static RK_S32 smear_flag_cover_intra_wgt1[3] = { -12, 0, 12}; +static RK_S32 smear_flag_bndry_wgt[3] = {0, 0, 0}; +static RK_S32 smear_flag_bndry_intra_wgt0[3] = { -12, 0, 12}; +static RK_S32 smear_flag_bndry_intra_wgt1[3] = { -12, 0, 12}; static RK_U32 rdo_lambda_table_I[60] = { 0x00000012, 0x00000017, @@ -470,11 +496,13 @@ static void vepu510_h265_set_atr_regs(H265eVepu510Sqi *reg_sqi, MppEncSceneMode } } -static void vepu510_h265_set_anti_blur_regs(H265eVepu510Sqi *reg_sqi, int anti_blur_en) +static void vepu510_h265_set_anti_blur_regs(H265eVepu510Sqi *reg_sqi, int anti_blur_level) { H265eVepu510Sqi *reg = reg_sqi; - - reg->subj_anti_blur_thd.anti_blur_en = anti_blur_en; + if (anti_blur_level >= 1) + reg->subj_anti_blur_thd.anti_blur_en = 1; + else + reg->subj_anti_blur_thd.anti_blur_en = 0; reg->subj_anti_blur_thd.blur_low_madi_thd = 5; reg->subj_anti_blur_thd.blur_high_madi_thd = 27; reg->subj_anti_blur_thd.blur_low_cnt_thd = 0; @@ -488,7 +516,7 @@ static void vepu510_h265_set_anti_blur_regs(H265eVepu510Sqi *reg_sqi, int anti_b reg->subj_anti_blur_sao.sao_ofst_thd_bo_chroma = 4; } -static void vepu510_h265_set_anti_stripe_regs(H265eVepu510Sqi *reg_sqi) +static void vepu510_h265_set_anti_stripe_regs(H265eVepu510Sqi *reg_sqi, int atl_level) { pre_cst_par* pre_i32 = (pre_cst_par*)®_sqi->preintra32_cst; pre_cst_par* pre_i16 = (pre_cst_par*)®_sqi->preintra16_cst; @@ -562,78 +590,18 @@ static void vepu510_h265_set_anti_stripe_regs(H265eVepu510Sqi *reg_sqi) pre_i32->cst_wgt3.lambda_mv_bit_1 = 4; // lv16 pre_i16->cst_wgt3.lambda_mv_bit_0 = 4; // lv8 pre_i16->cst_wgt3.lambda_mv_bit_1 = 3; // lv4 - - pre_i32->cst_wgt3.anti_strp_e = 1; + if (atl_level >= 1) + pre_i32->cst_wgt3.anti_strp_e = 1; + else + pre_i32->cst_wgt3.anti_strp_e = 0; } static void vepu510_h265_rdo_cfg(H265eV510HalContext *ctx, H265eVepu510Sqi *reg, MppEncSceneMode sm) { - reg->subj_opt_cfg.subj_opt_en = 1;//(sm == MPP_ENC_SCENE_MODE_IPC); + reg->subj_opt_cfg.subj_opt_en = 1; reg->subj_opt_cfg.subj_opt_strength = 3; reg->subj_opt_cfg.aq_subj_en = (sm == MPP_ENC_SCENE_MODE_IPC); reg->subj_opt_cfg.aq_subj_strength = 4; - reg->subj_opt_dpth_thd.common_thre_num_grdn_point_dep0 = 64; - reg->subj_opt_dpth_thd.common_thre_num_grdn_point_dep1 = 32; - reg->subj_opt_dpth_thd.common_thre_num_grdn_point_dep2 = 16; - reg->subj_opt_inrar_coef.common_rdo_cu_intra_r_coef_dep0 = 192; - reg->subj_opt_inrar_coef.common_rdo_cu_intra_r_coef_dep1 = 160; - - /* anti smear */ - reg->smear_opt_cfg0.anti_smear_en = (sm == MPP_ENC_SCENE_MODE_IPC); - reg->smear_opt_cfg0.smear_stor_en = 0; - reg->smear_opt_cfg0.smear_load_en = 0; - reg->smear_opt_cfg0.smear_strength = 3; - reg->smear_opt_cfg0.thre_mv_inconfor_cime = 8; - reg->smear_opt_cfg0.thre_mv_confor_cime = 2; - reg->smear_opt_cfg0.thre_mv_inconfor_cime_gmv = 8; - reg->smear_opt_cfg0.thre_mv_confor_cime_gmv = 2; - reg->smear_opt_cfg0.thre_num_mv_confor_cime = 3; - reg->smear_opt_cfg0.thre_num_mv_confor_cime_gmv = 2; - reg->smear_opt_cfg0.frm_static = 1; - - reg->smear_opt_cfg1.dist0_frm_avg = 0; - reg->smear_opt_cfg1.thre_dsp_static = 10; - reg->smear_opt_cfg1.thre_dsp_mov = 15; - reg->smear_opt_cfg1.thre_dist_mv_confor_cime = 32; - - reg->smear_madp_thd.thre_madp_stc_dep0 = 10; - reg->smear_madp_thd.thre_madp_stc_dep1 = 8; - reg->smear_madp_thd.thre_madp_stc_dep2 = 8; - reg->smear_madp_thd.thre_madp_mov_dep0 = 16; - reg->smear_madp_thd.thre_madp_mov_dep1 = 18; - reg->smear_madp_thd.thre_madp_mov_dep2 = 20; - - reg->smear_stat_thd.thre_num_pt_stc_dep0 = 47; - reg->smear_stat_thd.thre_num_pt_stc_dep1 = 11; - reg->smear_stat_thd.thre_num_pt_stc_dep2 = 3; - reg->smear_stat_thd.thre_num_pt_mov_dep0 = 47; - reg->smear_stat_thd.thre_num_pt_mov_dep1 = 11; - reg->smear_stat_thd.thre_num_pt_mov_dep2 = 3; - - reg->smear_bmv_dist_thd0.thre_ratio_dist_mv_confor_cime_gmv0 = 21; - reg->smear_bmv_dist_thd0.thre_ratio_dist_mv_confor_cime_gmv1 = 16; - reg->smear_bmv_dist_thd0.thre_ratio_dist_mv_inconfor_cime_gmv0 = 48; - reg->smear_bmv_dist_thd0.thre_ratio_dist_mv_inconfor_cime_gmv1 = 34; - - reg->smear_bmv_dist_thd1.thre_ratio_dist_mv_inconfor_cime_gmv2 = 32; - reg->smear_bmv_dist_thd1.thre_ratio_dist_mv_inconfor_cime_gmv3 = 29; - reg->smear_bmv_dist_thd1.thre_ratio_dist_mv_inconfor_cime_gmv4 = 27; - - reg->smear_min_bndry_gmv.thre_min_num_confor_csu0_bndry_cime_gmv = 0; - reg->smear_min_bndry_gmv.thre_max_num_confor_csu0_bndry_cime_gmv = 3; - reg->smear_min_bndry_gmv.thre_min_num_inconfor_csu0_bndry_cime_gmv = 0; - reg->smear_min_bndry_gmv.thre_max_num_inconfor_csu0_bndry_cime_gmv = 3; - reg->smear_min_bndry_gmv.thre_split_dep0 = 2; - reg->smear_min_bndry_gmv.thre_zero_srgn = 8; - reg->smear_min_bndry_gmv.madi_thre_dep0 = 22; - reg->smear_min_bndry_gmv.madi_thre_dep1 = 18; - - reg->smear_madp_cov_thd.thre_madp_stc_cover0 = 20; - reg->smear_madp_cov_thd.thre_madp_stc_cover1 = 20; - reg->smear_madp_cov_thd.thre_madp_mov_cover0 = 10; - reg->smear_madp_cov_thd.thre_madp_mov_cover1 = 10; - reg->smear_madp_cov_thd.smear_qp_strength = 10; - reg->smear_madp_cov_thd.smear_thre_qp = 30; /* skin_opt */ reg->skin_opt_cfg.skin_en = 0; @@ -650,10 +618,6 @@ static void vepu510_h265_rdo_cfg(H265eV510HalContext *ctx, H265eVepu510Sqi *reg, reg->skin_chrm_thd.thre_min_skin_v = 135; reg->subj_opt_dqp1.skin_thre_qp = 31; - /* text_opt */ - reg->subj_opt_dqp1.bndry_rdo_cu_intra_r_coef_dep0 = 240; - reg->subj_opt_dqp1.bndry_rdo_cu_intra_r_coef_dep1 = 224; - /* 0x00002100 reg2112 */ reg->cudecis_thd0.base_thre_rough_mad32_intra = 9; reg->cudecis_thd0.delta0_thre_rough_mad32_intra = 10; @@ -766,16 +730,16 @@ static void vepu510_h265_rdo_cfg(H265eV510HalContext *ctx, H265eVepu510Sqi *reg, reg->cudecis_thd11.delta6_thre_mad_fme_ratio_inter = 4; reg->cudecis_thd11.delta7_thre_mad_fme_ratio_inter = 4; - vepu510_h265_set_anti_stripe_regs(reg); + vepu510_h265_set_anti_stripe_regs(reg, ctx->cfg->tune.atl_str); if (ctx->frame_type == INTRA_FRAME) - vepu510_h265_set_atr_regs(reg, sm, 3); + vepu510_h265_set_atr_regs(reg, sm, ctx->cfg->tune.atr_str_i); else - vepu510_h265_set_atr_regs(reg, sm, 0); + vepu510_h265_set_atr_regs(reg, sm, ctx->cfg->tune.atr_str_p); if (ctx->frame_type == INTRA_FRAME) - vepu510_h265_set_anti_blur_regs(reg, 0); + vepu510_h265_set_anti_blur_regs(reg, ctx->cfg->tune.sao_str_i); else - vepu510_h265_set_anti_blur_regs(reg, 1); + vepu510_h265_set_anti_blur_regs(reg, ctx->cfg->tune.sao_str_p); } static void vepu510_h265_atf_cfg(H265eVepu510Sqi *reg, RK_S32 atf_str) @@ -839,6 +803,111 @@ static void vepu510_h265_atf_cfg(H265eVepu510Sqi *reg, RK_S32 atf_str) p_rdo_noskip->atf_wgt.wgt3 = 16; } +static void vepu510_h265_smear_cfg(H265eVepu510Sqi *reg, H265eV510HalContext *ctx) +{ + RK_S32 frame_num = ctx->frame_num; + RK_S32 frame_keyint = ctx->cfg->rc.gop; + RK_U32 cover_num = ctx->feedback.acc_cover16_num; + RK_U32 bndry_num = ctx->feedback.acc_bndry16_num; + RK_U32 st_ctu_num = ctx->feedback.st_ctu_num; + RK_S32 deblur_en = ctx->cfg->tune.deblur_en; + RK_S32 deblur_str = ctx->cfg->tune.deblur_str; + RK_S16 flag_cover = 0; + RK_S16 flag_bndry = 0; + + if (cover_num * 1000 < smear_flag_cover_thd0[deblur_str] * st_ctu_num) + flag_cover = 0; + else if (cover_num * 1000 < smear_flag_cover_thd1[deblur_str] * st_ctu_num) + flag_cover = 1; + else + flag_cover = 2; + + if (bndry_num * 1000 < smear_flag_bndry_thd0[deblur_str] * st_ctu_num) + flag_bndry = 0; + else if (bndry_num * 1000 < smear_flag_bndry_thd1[deblur_str] * st_ctu_num) + flag_bndry = 1; + else + flag_bndry = 2; + + reg->subj_opt_dpth_thd.common_thre_num_grdn_point_dep0 = 64; + reg->subj_opt_dpth_thd.common_thre_num_grdn_point_dep1 = 32; + reg->subj_opt_dpth_thd.common_thre_num_grdn_point_dep2 = 16; + reg->subj_opt_inrar_coef.common_rdo_cu_intra_r_coef_dep0 = smear_common_intra_r_dep0[deblur_str] + smear_flag_cover_intra_wgt0[flag_bndry]; + reg->subj_opt_inrar_coef.common_rdo_cu_intra_r_coef_dep1 = smear_common_intra_r_dep1[deblur_str] + smear_flag_cover_intra_wgt1[flag_bndry]; + + /* anti smear */ + reg->smear_opt_cfg0.anti_smear_en = 1; + if (deblur_en == 0) + reg->smear_opt_cfg0.anti_smear_en = 0; + reg->smear_opt_cfg0.smear_strength = smear_strength[deblur_str] + smear_flag_bndry_wgt[deblur_en]; + reg->smear_opt_cfg0.thre_mv_inconfor_cime = 8; + reg->smear_opt_cfg0.thre_mv_confor_cime = 2; + reg->smear_opt_cfg0.thre_mv_inconfor_cime_gmv = 8; + reg->smear_opt_cfg0.thre_mv_confor_cime_gmv = 2; + reg->smear_opt_cfg0.thre_num_mv_confor_cime = 3; + reg->smear_opt_cfg0.thre_num_mv_confor_cime_gmv = 2; + reg->smear_opt_cfg0.frm_static = 1; + + if (((frame_num) % frame_keyint == 0) || reg->smear_opt_cfg0.frm_static == 0 || (frame_num) % frame_keyint == 1) { + reg->smear_opt_cfg0.smear_load_en = 0; + } else { + reg->smear_opt_cfg0.smear_load_en = 1; + } + + if (((frame_num) % frame_keyint == 0) || reg->smear_opt_cfg0.frm_static == 0 || (frame_num) % frame_keyint == frame_keyint - 1) { + reg->smear_opt_cfg0.smear_stor_en = 0; + } else { + reg->smear_opt_cfg0.smear_stor_en = 1; + } + + reg->smear_opt_cfg1.dist0_frm_avg = 0; + reg->smear_opt_cfg1.thre_dsp_static = 10; + reg->smear_opt_cfg1.thre_dsp_mov = 15; + reg->smear_opt_cfg1.thre_dist_mv_confor_cime = 32; + + reg->smear_madp_thd.thre_madp_stc_dep0 = 10; + reg->smear_madp_thd.thre_madp_stc_dep1 = 8; + reg->smear_madp_thd.thre_madp_stc_dep2 = 8; + reg->smear_madp_thd.thre_madp_mov_dep0 = 16; + reg->smear_madp_thd.thre_madp_mov_dep1 = 18; + reg->smear_madp_thd.thre_madp_mov_dep2 = 20; + + reg->smear_stat_thd.thre_num_pt_stc_dep0 = 47; + reg->smear_stat_thd.thre_num_pt_stc_dep1 = 11; + reg->smear_stat_thd.thre_num_pt_stc_dep2 = 3; + reg->smear_stat_thd.thre_num_pt_mov_dep0 = 47; + reg->smear_stat_thd.thre_num_pt_mov_dep1 = 11; + reg->smear_stat_thd.thre_num_pt_mov_dep2 = 3; + + reg->smear_bmv_dist_thd0.thre_ratio_dist_mv_confor_cime_gmv0 = 21; + reg->smear_bmv_dist_thd0.thre_ratio_dist_mv_confor_cime_gmv1 = 16; + reg->smear_bmv_dist_thd0.thre_ratio_dist_mv_inconfor_cime_gmv0 = 48; + reg->smear_bmv_dist_thd0.thre_ratio_dist_mv_inconfor_cime_gmv1 = 34; + + reg->smear_bmv_dist_thd1.thre_ratio_dist_mv_inconfor_cime_gmv2 = 32; + reg->smear_bmv_dist_thd1.thre_ratio_dist_mv_inconfor_cime_gmv3 = 29; + reg->smear_bmv_dist_thd1.thre_ratio_dist_mv_inconfor_cime_gmv4 = 27; + + reg->smear_min_bndry_gmv.thre_min_num_confor_csu0_bndry_cime_gmv = 0; + reg->smear_min_bndry_gmv.thre_max_num_confor_csu0_bndry_cime_gmv = 3; + reg->smear_min_bndry_gmv.thre_min_num_inconfor_csu0_bndry_cime_gmv = 0; + reg->smear_min_bndry_gmv.thre_max_num_inconfor_csu0_bndry_cime_gmv = 3; + reg->smear_min_bndry_gmv.thre_split_dep0 = 2; + reg->smear_min_bndry_gmv.thre_zero_srgn = 8; + reg->smear_min_bndry_gmv.madi_thre_dep0 = 22; + reg->smear_min_bndry_gmv.madi_thre_dep1 = 18; + + reg->smear_madp_cov_thd.thre_madp_stc_cover0 = smear_thre_madp_stc_cover0[deblur_str]; + reg->smear_madp_cov_thd.thre_madp_stc_cover1 = smear_thre_madp_stc_cover1[deblur_str]; + reg->smear_madp_cov_thd.thre_madp_mov_cover0 = smear_thre_madp_mov_cover0[deblur_str]; + reg->smear_madp_cov_thd.thre_madp_mov_cover1 = smear_thre_madp_mov_cover1[deblur_str]; + reg->smear_madp_cov_thd.smear_qp_strength = smear_qp_strength[deblur_str] + smear_flag_cover_wgt[flag_cover]; + reg->smear_madp_cov_thd.smear_thre_qp = 30; + + reg->subj_opt_dqp1.bndry_rdo_cu_intra_r_coef_dep0 = smear_bndry_intra_r_dep0[deblur_str] + smear_flag_bndry_intra_wgt0[flag_bndry]; + reg->subj_opt_dqp1.bndry_rdo_cu_intra_r_coef_dep1 = smear_bndry_intra_r_dep1[deblur_str] + smear_flag_bndry_intra_wgt1[flag_bndry]; +} + static void vepu510_h265_global_cfg_set(H265eV510HalContext *ctx, H265eV510RegSet *regs) { MppEncHwCfg *hw = &ctx->cfg->hw; @@ -850,6 +919,7 @@ static void vepu510_h265_global_cfg_set(H265eV510HalContext *ctx, H265eV510RegSe vepu510_h265_rdo_cfg(ctx, reg_sqi, sm); vepu510_h265_atf_cfg(reg_sqi, atf_str); + vepu510_h265_smear_cfg(reg_sqi, ctx); memcpy(®_param->pprd_lamb_satd_0_51[0], lamd_satd_qp_510, sizeof(lamd_satd_qp)); if (ctx->frame_type == INTRA_FRAME) { @@ -1882,8 +1952,8 @@ MPP_RET hal_h265e_v510_gen_regs(void *hal, HalEncTask *task) reg_frm->rdo_cfg.cu_inter_e = 0xdb; reg_frm->rdo_cfg.lambda_qp_use_avg_cu16_flag = (sm == MPP_ENC_SCENE_MODE_IPC); reg_frm->rdo_cfg.yuvskip_calc_en = 1; - reg_frm->rdo_cfg.atf_e = 1; - reg_frm->rdo_cfg.atr_e = (sm == MPP_ENC_SCENE_MODE_IPC); + reg_frm->rdo_cfg.atf_e = (sm == MPP_ENC_SCENE_MODE_IPC); + reg_frm->rdo_cfg.atr_e = 1; if (syn->pp.num_long_term_ref_pics_sps) { reg_frm->rdo_cfg.ltm_col = 0; @@ -2134,6 +2204,10 @@ static MPP_RET vepu510_h265_set_feedback(H265eV510HalContext *ctx, HalEncTask *e fb->st_lvl8_inter_num += elem->st.st_pnum_p8.pnum_p8; fb->st_lvl8_intra_num += elem->st.st_pnum_i8.pnum_i8; fb->st_lvl4_intra_num += elem->st.st_pnum_i4.pnum_i4; + ctx->feedback.acc_cover16_num = elem->st.st_skin_sum1.acc_cover16_num; + ctx->feedback.acc_bndry16_num = elem->st.st_skin_sum2.acc_bndry16_num; + ctx->feedback.acc_zero_mv = elem->st.acc_zero_mv; + ctx->feedback.st_ctu_num = elem->st.st_bnum_b16.num_b16; memcpy(&fb->st_cu_num_qp[0], &elem->st.st_b8_qp, 52 * sizeof(RK_U32)); if (mb4_num > 0) diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu510_tune.c b/mpp/hal/rkenc/h265e/hal_h265e_vepu510_tune.c index aa6cee07..b8b325d5 100644 --- a/mpp/hal/rkenc/h265e/hal_h265e_vepu510_tune.c +++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu510_tune.c @@ -29,7 +29,7 @@ typedef struct HalH265eVepu510Tune_t { static RK_U32 aq_thd_default[16] = { 0, 0, 0, 0, 3, 3, 5, 5, - 8, 8, 8, 15, 15, 20, 25, 25 + 8, 8, 15, 15, 20, 25, 25, 25 }; static RK_S32 aq_qp_delta_default[16] = { @@ -39,22 +39,22 @@ static RK_S32 aq_qp_delta_default[16] = { static RK_U32 aq_thd_smt_I[16] = { 1, 2, 3, 3, 3, 3, 5, 5, - 8, 8, 8, 13, 15, 20, 25, 25 + 8, 8, 13, 15, 20, 25, 25, 25 }; static RK_S32 aq_qp_delta_smt_I[16] = { -8, -7, -6, -5, -4, -3, -2, -1, - 0, 1, 2, 3, 5, 7, 8, 9 + 1, 2, 3, 5, 7, 8, 9, 9 }; static RK_U32 aq_thd_smt_P[16] = { 0, 0, 0, 0, 3, 3, 5, 5, - 8, 8, 8, 15, 15, 20, 25, 25 + 8, 8, 15, 15, 20, 25, 25, 25 }; static RK_S32 aq_qp_delta_smt_P[16] = { -8, -7, -6, -5, -4, -3, -2, -1, - 0, 1, 2, 3, 4, 6, 7, 9 + 1, 2, 3, 4, 6, 7, 9, 9 }; static HalH265eVepu510Tune *vepu510_h265e_tune_init(H265eV510HalContext *ctx) @@ -150,6 +150,7 @@ static void vepu510_h265e_tune_aq(HalH265eVepu510Tune *tune) static void vepu510_h265e_tune_reg_patch(void *p, HalEncTask *task) { HalH265eVepu510Tune *tune = (HalH265eVepu510Tune *)p; + (void)task; if (NULL == tune) return; diff --git a/test/mpi_enc_test.c b/test/mpi_enc_test.c index 05393197..78b50d2a 100644 --- a/test/mpi_enc_test.c +++ b/test/mpi_enc_test.c @@ -120,7 +120,11 @@ typedef struct { RK_S32 scene_mode; RK_S32 cu_qp_delta_depth; RK_S32 anti_flicker_str; - + RK_S32 atr_str_i; + RK_S32 atr_str_p; + RK_S32 atl_str; + RK_S32 sao_str_i; + RK_S32 sao_str_p; RK_S64 first_frm; RK_S64 first_pkt; } MpiEncTestData; @@ -182,6 +186,12 @@ MPP_RET test_ctx_init(MpiEncMultiCtxInfo *info) p->scene_mode = cmd->scene_mode; p->cu_qp_delta_depth = cmd->cu_qp_delta_depth; p->anti_flicker_str = cmd->anti_flicker_str; + p->atr_str_i = cmd->atr_str_i; + p->atr_str_p = cmd->atr_str_p; + p->atl_str = cmd->atl_str; + p->sao_str_i = cmd->sao_str_i; + p->sao_str_p = cmd->sao_str_p; + p->mdinfo_size = (MPP_VIDEO_CodingHEVC == cmd->type) ? (MPP_ALIGN(p->hor_stride, 32) >> 5) * (MPP_ALIGN(p->ver_stride, 32) >> 5) * 16 : @@ -321,6 +331,11 @@ MPP_RET test_mpp_enc_cfg_setup(MpiEncMultiCtxInfo *info) mpp_enc_cfg_set_s32(cfg, "rc:cu_qp_delta_depth", p->cu_qp_delta_depth); mpp_enc_cfg_set_s32(cfg, "tune:anti_flicker_str", p->anti_flicker_str); + mpp_enc_cfg_set_s32(cfg, "tune:atr_str_i", p->atr_str_i); + mpp_enc_cfg_set_s32(cfg, "tune:atr_str_p", p->atr_str_p); + mpp_enc_cfg_set_s32(cfg, "tune:atl_str", p->atl_str); + mpp_enc_cfg_set_s32(cfg, "tune:sao_str_i", p->sao_str_i); + mpp_enc_cfg_set_s32(cfg, "tune:sao_str_p", p->sao_str_p); mpp_enc_cfg_set_s32(cfg, "tune:scene_mode", p->scene_mode); mpp_enc_cfg_set_s32(cfg, "tune:deblur_en", cmd->deblur_en); diff --git a/utils/mpi_enc_utils.c b/utils/mpi_enc_utils.c index e72d1fb8..64729e3b 100644 --- a/utils/mpi_enc_utils.c +++ b/utils/mpi_enc_utils.c @@ -547,6 +547,71 @@ RK_S32 mpi_enc_opt_atf(void *ctx, const char *next) return 0; } +RK_S32 mpi_enc_opt_atl(void *ctx, const char *next) +{ + MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx; + + if (next) { + cmd->atl_str = atoi(next); + return 1; + } + + mpp_err("invalid atl_str\n"); + return 0; +} + +RK_S32 mpi_enc_opt_atr_i(void *ctx, const char *next) +{ + MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx; + + if (next) { + cmd->atr_str_i = atoi(next); + return 1; + } + + mpp_err("invalid atr_str_i\n"); + return 0; +} + +RK_S32 mpi_enc_opt_atr_p(void *ctx, const char *next) +{ + MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx; + + if (next) { + cmd->atr_str_p = atoi(next); + return 1; + } + + mpp_err("invalid atr_str_p\n"); + return 0; +} + +RK_S32 mpi_enc_opt_sao_i(void *ctx, const char *next) +{ + MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx; + + if (next) { + cmd->sao_str_i = atoi(next); + return 1; + } + + mpp_err("invalid sao_str_i\n"); + return 0; +} + +RK_S32 mpi_enc_opt_sao_p(void *ctx, const char *next) +{ + MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx; + + if (next) { + cmd->sao_str_p = atoi(next); + return 1; + } + + mpp_err("invalid sao_str_p\n"); + return 0; +} + static MppOptInfo enc_opts[] = { {"i", "input_file", "input frame file", mpi_enc_opt_i}, {"o", "output_file", "output encoded bitstream file", mpi_enc_opt_o}, @@ -574,6 +639,11 @@ static MppOptInfo enc_opts[] = { {"dbe", "deblur enable", "deblur_en or qpmap_en, 0:close 1:open", mpi_enc_opt_dbe}, {"dbs", "deblur strength", "deblur_str 0~3: hw + sw scheme; 4~7: hw scheme", mpi_enc_opt_dbs}, {"atf", "anti_flicker_str", "anti_flicker_str, 0:off 1 2 3", mpi_enc_opt_atf}, + {"atl", "atl_str", "atl_str, 0:off 1 open", mpi_enc_opt_atl}, + {"atr_i", "atr_str_i", "atr_str_i, 0:off 1 2 3", mpi_enc_opt_atr_i}, + {"atr_p", "atr_str_p", "atr_str_p, 0:off 1 2 3", mpi_enc_opt_atr_p}, + {"sao_i", "sao_str_i", "sao_str_i, 0:off 1 2 3", mpi_enc_opt_sao_i}, + {"sao_p", "sao_str_p", "sao_str_p, 0:off 1 2 3", mpi_enc_opt_sao_p}, }; static RK_U32 enc_opt_cnt = MPP_ARRAY_ELEMS(enc_opts); diff --git a/utils/mpi_enc_utils.h b/utils/mpi_enc_utils.h index 5905fc59..02504a1a 100644 --- a/utils/mpi_enc_utils.h +++ b/utils/mpi_enc_utils.h @@ -80,6 +80,11 @@ typedef struct MpiEncTestArgs_t { /* -qpdd cu_qp_delta_depth */ RK_S32 cu_qp_delta_depth; RK_S32 anti_flicker_str; + RK_S32 atr_str_i; + RK_S32 atr_str_p; + RK_S32 atl_str; + RK_S32 sao_str_i; + RK_S32 sao_str_p; /* -dbe deblur enable flag * -dbs deblur strength