[h264e_prep]: add prep cfg interface for dsp

1. cfg sharpen parameters

export h264e_hal_debug=0x8001, to open log
export h264e_hal_debug=0x1,    to close log

Change-Id: I97322f9819cfbb6909b86afc25f84bacac9841af
Signed-off-by: Lin Kesheng <lks@rock-chips.com>

inc/rk_mpi_cmd.h

@@ -18,6 +18,7 @@
 #define __RK_MPI_CMD_H__
 
 #include "rk_type.h"
+#include "mpp_frame.h"
 
 /*
  * Command id bit usage is defined as follows:
@@ -315,6 +316,17 @@ typedef struct MppEncPrepCfg_t {
     MppFrameFormat      format_in;
     MppFrameFormat      format_out;
     RK_U32              rotation;
+
+    // sharpen
+    RK_U32              src_shp_en_y;
+    RK_U32              src_shp_en_uv;
+    RK_U32              src_shp_thr;
+    RK_U32              src_shp_div;
+    RK_U32              src_shp_w0;
+    RK_U32              src_shp_w1;
+    RK_U32              src_shp_w2;
+    RK_U32              src_shp_w3;
+    RK_U32              src_shp_w4;
 } MppEncPrepCfg;
 
 /*

mpp/codec/mpp_enc.cpp

@@ -429,7 +429,8 @@ MPP_RET mpp_enc_control(MppEnc *enc, MpiCmd cmd, void *param)
     case MPP_ENC_SET_OSD_PLT_CFG :
     case MPP_ENC_SET_OSD_DATA_CFG :
     case MPP_ENC_SET_SEI_CFG :
-    case MPP_ENC_GET_SEI_DATA : {
+    case MPP_ENC_GET_SEI_DATA :
+    case MPP_ENC_SET_PREP_CFG : {
         ret = mpp_hal_control(enc->hal, cmd, param);
     } break;
     default : {

mpp/hal/rkenc/h264e/hal_h264e.h

@@ -18,10 +18,11 @@
 #define __HAL_H264E_H__
 
 #include "vpu.h"
+#include "rk_mpi_cmd.h"
+#include "mpp_packet.h"
 #include "mpp_log.h"
 #include "mpp_hal.h"
 
-#include "mpp_packet.h"
 #include "h264e_syntax.h"
 
 extern RK_U32 h264e_hal_log_mode;
@@ -35,6 +36,7 @@ extern RK_U32 h264e_hal_log_mode;
 #define H264E_HAL_LOG_DPB               0x00001000
 #define H264E_HAL_LOG_HEADER            0x00002000
 #define H264E_HAL_LOG_SEI               0x00004000
+#define H264E_HAL_LOG_PP                0x00008000
 
 #define H264E_HAL_LOG_DETAIL            0x00010000
 
@@ -42,6 +44,7 @@ extern RK_U32 h264e_hal_log_mode;
 
 
 
+
 #define H264E_HAL_MASK_2b               (RK_U32)0x00000003
 #define H264E_HAL_MASK_3b               (RK_U32)0x00000007
 #define H264E_HAL_MASK_4b               (RK_U32)0x0000000F
@@ -106,6 +109,12 @@ extern RK_U32 h264e_hal_log_mode;
                     { mpp_log(fmt, ## __VA_ARGS__); }\
             } while (0)
 
+#define h264e_hal_log_pp(fmt, ...) \
+            do {\
+                if (h264e_hal_log_mode & H264E_HAL_LOG_PP)\
+                    { mpp_log(fmt, ## __VA_ARGS__); }\
+            } while (0)
+
 #define H264E_HAL_MIN(a,b) ( (a)<(b) ? (a) : (b) )
 #define H264E_HAL_MAX(a,b) ( (a)>(b) ? (a) : (b) )
 #define H264E_HAL_MIN3(a,b,c) H264E_HAL_MIN((a),H264E_HAL_MIN((b),(c)))
@@ -398,6 +407,7 @@ typedef struct h264e_hal_context_t {
     RK_U32                          osd_plt_type; //0:user define, 1:default
     MppEncOSDData                   osd_data;
     MppEncSeiMode                   sei_mode;
+    MppEncPrepCfg                   prep_cfg;
 } h264e_hal_context;
 
 #endif

mpp/hal/rkenc/h264e/hal_h264e_rkv.c

@@ -3048,7 +3048,8 @@ MPP_RET hal_h264e_rkv_set_osd_regs(h264e_hal_context *ctx, h264e_rkv_reg_set *re
     return MPP_OK;
 }
 
-MPP_RET hal_h264e_rkv_set_pp_regs(h264e_rkv_reg_set *regs, h264e_syntax *syn, MppBuffer hw_buf_w, MppBuffer hw_buf_r, RK_U32 frame_cnt,
+MPP_RET hal_h264e_rkv_set_pp_regs(h264e_rkv_reg_set *regs, h264e_syntax *syn, MppEncPrepCfg *prep_cfg,
+                                  MppBuffer hw_buf_w, MppBuffer hw_buf_r, RK_U32 frame_cnt,
                                   h264e_hal_rkv_coveragetest_cfg *test)
 {
     RK_S32 k = 0;
@@ -3156,8 +3157,18 @@ MPP_RET hal_h264e_rkv_set_pp_regs(h264e_rkv_reg_set *regs, h264e_syntax *syn, Mp
                 stridey = (stridey + 1) * 2 - 1;
         }
         stridec = (regs->swreg14.src_cfmt == 4 || regs->swreg14.src_cfmt == 6) ? stridey : ((stridey + 1) / 2 - 1);
-        regs->swreg23.src_ystrid    = stridey; //syn->swreg23.src_ystrid;
+        regs->swreg23.src_ystrid    = stridey;
-        regs->swreg23.src_cstrid    = stridec; //syn->swreg23.src_cstrid;    ////YUV420 planar;
+        regs->swreg23.src_cstrid    = stridec;
+
+        regs->swreg19.src_shp_y    = prep_cfg->src_shp_en_y;
+        regs->swreg19.src_shp_c    = prep_cfg->src_shp_en_uv;
+        regs->swreg19.src_shp_div  = prep_cfg->src_shp_div;
+        regs->swreg19.src_shp_thld = prep_cfg->src_shp_thr;
+        regs->swreg21_scr_stbl[0]  = prep_cfg->src_shp_w0;
+        regs->swreg21_scr_stbl[1]  = prep_cfg->src_shp_w1;
+        regs->swreg21_scr_stbl[2]  = prep_cfg->src_shp_w2;
+        regs->swreg21_scr_stbl[3]  = prep_cfg->src_shp_w3;
+        regs->swreg21_scr_stbl[4]  = prep_cfg->src_shp_w4;
 
         (void)test;
     }
@@ -3304,7 +3315,7 @@ MPP_RET hal_h264e_rkv_gen_regs(void *hal, HalTaskInfo *task)
     regs->swreg13.axi_brsp_cke      = 0x7f; //syn->swreg13.axi_brsp_cke;
     regs->swreg13.cime_dspw_orsd    = 0x0;
 
-    hal_h264e_rkv_set_pp_regs(regs, syn, bufs->hw_pp_buf[buf2_idx], bufs->hw_pp_buf[1 - buf2_idx], ctx->frame_cnt, test_cfg);
+    hal_h264e_rkv_set_pp_regs(regs, syn, &ctx->prep_cfg, bufs->hw_pp_buf[buf2_idx], bufs->hw_pp_buf[1 - buf2_idx], ctx->frame_cnt, test_cfg);
     hal_h264e_rkv_set_ioctl_extra_info(&ioctl_reg_info->extra_info, syn, regs);
 
     regs->swreg24_adr_srcy     = syn->input_luma_addr; //syn->addr_cfg.adr_srcy;
@@ -3851,6 +3862,10 @@ MPP_RET hal_h264e_rkv_control(void *hal, RK_S32 cmd_type, void *param)
         hal_h264e_rkv_get_extra_info(ctx, (MppPacket *)param);
         break;
     }
+    case MPP_ENC_SET_PREP_CFG: {
+        memcpy(&ctx->prep_cfg, param, sizeof(ctx->prep_cfg));
+        break;
+    }
     default : {
         h264e_hal_log_err("unrecognizable cmd type %x", cmd_type);
     } break;