diff --git a/mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c b/mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
index 6d05d636..83ac2994 100644
--- a/mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
+++ b/mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
@@ -907,12 +907,6 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal,  HalTaskInfo *syn)
     hw_regs = (Vdpu34xH265dRegSet*)reg_ctx->hw_regs;
     memset(hw_regs, 0, sizeof(Vdpu34xH265dRegSet));
 
-    if (reg_ctx->is_v34x) {
-        hal_h265d_v345_output_pps_packet(hal, syn->dec.syntax.data);
-    } else {
-        hal_h265d_output_pps_packet(hal, syn->dec.syntax.data);
-    }
-
     if (NULL == reg_ctx->hw_regs) {
         return MPP_ERR_NULL_PTR;
     }
@@ -1135,6 +1129,12 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal,  HalTaskInfo *syn)
         return MPP_OK;
     }
 
+    if (reg_ctx->is_v34x) {
+        hal_h265d_v345_output_pps_packet(hal, syn->dec.syntax.data);
+    } else {
+        hal_h265d_output_pps_packet(hal, syn->dec.syntax.data);
+    }
+
     trans_cfg.reg_idx = 161;
     trans_cfg.offset = reg_ctx->spspps_offset;
     mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
diff --git a/mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c b/mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c
index 6530ee9c..730397d9 100644
--- a/mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c
+++ b/mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c
@@ -713,8 +713,6 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal,  HalTaskInfo *syn)
     hw_regs = (Vdpu382H265dRegSet*)reg_ctx->hw_regs;
     memset(hw_regs, 0, sizeof(Vdpu382H265dRegSet));
 
-    hal_h265d_v382_output_pps_packet(hal, syn->dec.syntax.data);
-
     if (NULL == reg_ctx->hw_regs) {
         return MPP_ERR_NULL_PTR;
     }
@@ -911,6 +909,7 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal,  HalTaskInfo *syn)
                 SET_POC_HIGNBIT_INFO(hw_regs->highpoc, i, poc_highbit, 3);
         }
     }
+    hal_h265d_v382_output_pps_packet(hal, syn->dec.syntax.data);
 
     trans_cfg.reg_idx = 161;
     trans_cfg.offset = reg_ctx->spspps_offset;
diff --git a/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c b/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c
index a6702c05..4a81eb5d 100644
--- a/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c
+++ b/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c
@@ -925,8 +925,6 @@ static MPP_RET hal_h265d_vdpu383_gen_regs(void *hal,  HalTaskInfo *syn)
     hw_regs = (Vdpu383H265dRegSet*)reg_ctx->hw_regs;
     memset(hw_regs, 0, sizeof(Vdpu383H265dRegSet));
 
-    hal_h265d_v345_output_pps_packet(hal, syn->dec.syntax.data);
-
     if (NULL == reg_ctx->hw_regs) {
         return MPP_ERR_NULL_PTR;
     }
@@ -1066,22 +1064,6 @@ static MPP_RET hal_h265d_vdpu383_gen_regs(void *hal,  HalTaskInfo *syn)
 
     hal_h265d_vdpu383_rps(syn->dec.syntax.data, rps_ptr, reg_ctx->sw_rps_buf, reg_ctx->fast_mode);
 
-    MppDevRegOffsetCfg trans_cfg;
-
-    /* pps */
-    hw_regs->common_addr.reg131_gbl_base = reg_ctx->bufs_fd;
-    hw_regs->h265d_paras.reg67_global_len = 0xc; //22 * 8;
-
-    trans_cfg.reg_idx = 131;
-    trans_cfg.offset = reg_ctx->spspps_offset;
-    mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
-
-    /* rps */
-    hw_regs->common_addr.reg129_rps_base = reg_ctx->bufs_fd;
-    trans_cfg.reg_idx = 129;
-    trans_cfg.offset = reg_ctx->rps_offset;
-    mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
-
     hw_regs->common_addr.reg128_strm_base = mpp_buffer_get_fd(streambuf);
     hw_regs->h265d_paras.reg66_stream_len = ((dxva_ctx->bitstream_size + 15) & (~15)) + 64;
     aglin_offset =  hw_regs->h265d_paras.reg66_stream_len - dxva_ctx->bitstream_size;
@@ -1163,6 +1145,24 @@ static MPP_RET hal_h265d_vdpu383_gen_regs(void *hal,  HalTaskInfo *syn)
         return MPP_OK;
     }
 
+    MppDevRegOffsetCfg trans_cfg;
+
+    /* pps */
+    hw_regs->common_addr.reg131_gbl_base = reg_ctx->bufs_fd;
+    hw_regs->h265d_paras.reg67_global_len = 0xc; //22 * 8;
+
+    trans_cfg.reg_idx = 131;
+    trans_cfg.offset = reg_ctx->spspps_offset;
+    mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
+
+    /* rps */
+    hw_regs->common_addr.reg129_rps_base = reg_ctx->bufs_fd;
+    trans_cfg.reg_idx = 129;
+    trans_cfg.offset = reg_ctx->rps_offset;
+    mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
+
+    hal_h265d_v345_output_pps_packet(hal, syn->dec.syntax.data);
+
     for (i = 0; i < (RK_S32)MPP_ARRAY_ELEMS(dxva_ctx->pp.RefPicList); i++) {
 
         if (dxva_ctx->pp.RefPicList[i].bPicEntry != 0xff &&