package/mpp
1
0
Fork 0
mirror of https://github.com/nyanmisaka/mpp.git synced 2025-10-04 08:46:24 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

feat[vepu510]: Sync code from enc_tune branch

Browse Source 
1. Add anti-line tuning
2. Adjust AQ assignment
3. Add smart encoding
4. Add deblur/qpmap routine
5. Add atf & four level intensity control atf
6. Add atr anti_blur function
7. Add real time bitrate output
8. Add smear buffer for vepu510

Change-Id: Iae661686f6adacd0b5ec57c102c184e2537dfc7d
Signed-off-by: Tingjin Huang <timkingh.huang@rock-chips.com>
This commit is contained in:
toby.zhang
2024-05-23 16:13:35 +08:00
committed by Tingjin Huang
parent 02095f66d3
commit 03696728e1
21 changed files with 1500 additions and 1107 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
inc/mpp_meta.h
View File

@@ -80,6 +80,7 @@ typedef enum MppMetaKey_e {
KEY_LONG_REF_IDX = FOURCC_META('l', 't', 'i', 'd'),
KEY_ENC_AVERAGE_QP = FOURCC_META('a', 'v', 'g', 'q'),
KEY_ENC_START_QP = FOURCC_META('s', 't', 'r', 'q'),
KEY_ENC_BPS_RT = FOURCC_META('r', 't', 'b', 'r'), /* realtime bps */
KEY_ROI_DATA = FOURCC_META('r', 'o', 'i', ' '),
KEY_OSD_DATA = FOURCC_META('o', 's', 'd', ' '),
KEY_OSD_DATA2 = FOURCC_META('o', 's', 'd', '2'),

1
inc/mpp_rc_api.h
View File

@@ -50,6 +50,7 @@ typedef enum RcMode_e {
RC_CBR,
RC_FIXQP,
RC_AVBR,
RC_SMT,
RC_CVBR,
RC_QVBR,
RC_LEARNING,

5
inc/mpp_rc_defs.h
View File

@@ -215,7 +215,10 @@ typedef struct EncRcCommonInfo_t {
RK_S32 scene_mode;
RK_S32 last_scene_mode;
RK_S32 reserve[5];
/* rc stats info: real time bits */
RK_S32 rt_bits;
RK_S32 reserve[4];
} EncRcTaskInfo;
typedef struct EncRcTask_s {

12
inc/rk_venc_cmd.h
View File

@@ -1428,15 +1428,21 @@ typedef enum MppEncSceneMode_e {
typedef enum MppEncFineTuneCfgChange_e {
/* change on scene mode */
MPP_ENC_TUNE_CFG_CHANGE_SCENE_MODE = (1 << 0),
MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_I = (1 << 5),
MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_P = (1 << 6)
MPP_ENC_TUNE_CFG_CHANGE_SCENE_MODE = (1 << 0),
MPP_ENC_TUNE_CFG_CHANGE_DEBLUR_EN = (1 << 1),
MPP_ENC_TUNE_CFG_CHANGE_DEBLUR_STR = (1 << 2),
MPP_ENC_TUNE_CFG_CHANGE_ANTI_FLICKER_STR = (1 << 3),
MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_I = (1 << 5),
MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_P = (1 << 6)
} MppEncFineTuneCfgChange;
typedef struct MppEncFineTuneCfg_t {
RK_U32 change;
MppEncSceneMode scene_mode;
RK_S32 deblur_en; /* qpmap_en */
RK_S32 deblur_str; /* deblur strength */
RK_S32 anti_flicker_str;
RK_S32 lambda_idx_i;
RK_S32 lambda_idx_p;
} MppEncFineTuneCfg;

1
inc/rk_venc_rc.h
View File

@@ -28,6 +28,7 @@ typedef enum MppEncRcMode_e {
MPP_ENC_RC_MODE_CBR,
MPP_ENC_RC_MODE_FIXQP,
MPP_ENC_RC_MODE_AVBR,
MPP_ENC_RC_MODE_SMTRC,
MPP_ENC_RC_MODE_BUTT
} MppEncRcMode;

1
mpp/base/mpp_2str.c
View File

@@ -72,6 +72,7 @@ const char *strof_rc_mode(MppEncRcMode rc_mode)
"cbr",
"fixqp",
"avbr",
"smtrc"
};
if (rc_mode >= MPP_ENC_RC_MODE_VBR && rc_mode < MPP_ENC_RC_MODE_BUTT)

3
mpp/base/mpp_enc_cfg.cpp
View File

@@ -257,6 +257,9 @@ public:
ENTRY(hw, qbias_en, S32, RK_S32, MPP_ENC_HW_CFG_CHANGE_QBIAS_EN, hw, qbias_en) \
/* quality fine tuning config */ \
ENTRY(tune, scene_mode, S32, MppEncSceneMode, MPP_ENC_TUNE_CFG_CHANGE_SCENE_MODE, tune, scene_mode) \
ENTRY(tune, deblur_en, S32, RK_S32, MPP_ENC_TUNE_CFG_CHANGE_DEBLUR_EN, tune, deblur_en) \
ENTRY(tune, deblur_str, S32, RK_S32, MPP_ENC_TUNE_CFG_CHANGE_DEBLUR_STR, tune, deblur_str) \
ENTRY(tune, anti_flicker_str,S32, RK_S32, MPP_ENC_TUNE_CFG_CHANGE_ANTI_FLICKER_STR,tune, anti_flicker_str) \
ENTRY(tune, lambda_idx_i, S32, RK_S32, MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_I, tune, lambda_idx_i) \
ENTRY(tune, lambda_idx_p, S32, RK_S32, MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_P, tune, lambda_idx_p)

1
mpp/base/mpp_meta.cpp
View File

@@ -56,6 +56,7 @@ static MppMetaDef meta_defs[] = {
{ KEY_LONG_REF_IDX, TYPE_S32, },
{ KEY_ENC_AVERAGE_QP, TYPE_S32, },
{ KEY_ENC_START_QP, TYPE_S32, },
{ KEY_ENC_BPS_RT, TYPE_S32, },
{ KEY_ROI_DATA, TYPE_PTR, },
{ KEY_ROI_DATA2, TYPE_PTR, },

1
mpp/codec/enc/h265/h265e_api.c
View File

@@ -112,6 +112,7 @@ static MPP_RET h265e_init(void *ctx, EncImplCfg *ctrlCfg)
p->cfg->tune.scene_mode = MPP_ENC_SCENE_MODE_DEFAULT;
p->cfg->tune.lambda_idx_i = 2;
p->cfg->tune.lambda_idx_p = 4;
p->cfg->tune.anti_flicker_str = 2;
/*
* default prep:

2
mpp/codec/inc/mpp_rc.h
View File

@@ -128,7 +128,7 @@ RK_S32 mpp_data_avg(MppData *p, RK_S32 len, RK_S32 num, RK_S32 denom);
void mpp_pid_reset(MppPIDCtx *p);
void mpp_pid_set_param(MppPIDCtx *p, RK_S32 coef_p, RK_S32 coef_i, RK_S32 coef_d, RK_S32 div, RK_S32 len);
void mpp_pid_update(MppPIDCtx *p, RK_S32 val);
void mpp_pid_update(MppPIDCtx *p, RK_S32 val, RK_S32 is_reset);
RK_S32 mpp_pid_calc(MppPIDCtx *ctx);
#ifdef __cplusplus

30
mpp/codec/mpp_enc_impl.cpp
View File

@@ -862,16 +862,35 @@ MPP_RET mpp_enc_proc_tune_cfg(MppEncFineTuneCfg *dst, MppEncFineTuneCfg *src)
if (dst->scene_mode < MPP_ENC_SCENE_MODE_DEFAULT ||
dst->scene_mode >= MPP_ENC_SCENE_MODE_BUTT) {
mpp_err("invalid scene mode %d not in range [%d:%d]\n", dst->scene_mode,
mpp_err("invalid scene mode %d not in range [%d, %d]\n", dst->scene_mode,
MPP_ENC_SCENE_MODE_DEFAULT, MPP_ENC_SCENE_MODE_BUTT - 1);
ret = MPP_ERR_VALUE;
}
if (change & MPP_ENC_TUNE_CFG_CHANGE_DEBLUR_EN)
dst->deblur_en = src->deblur_en;
if (change & MPP_ENC_TUNE_CFG_CHANGE_DEBLUR_STR)
dst->deblur_str = src->deblur_str;
if (dst->deblur_str < 0 || dst->deblur_str > 7) {
mpp_err("invalid deblur strength not in range [0, 7]\n");
ret = MPP_ERR_VALUE;
}
if (change & MPP_ENC_TUNE_CFG_CHANGE_ANTI_FLICKER_STR)
dst->anti_flicker_str = src->anti_flicker_str;
if (dst->anti_flicker_str < 0 || dst->anti_flicker_str > 3) {
mpp_err("invalid anti_flicker_str not in range [0 : 3]\n");
ret = MPP_ERR_VALUE;
}
if (change & MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_I)
dst->lambda_idx_i = src->lambda_idx_i;
if (dst->lambda_idx_i < 0 || dst->lambda_idx_i > 8) {
mpp_err("invalid lambda idx i not in range [0 : 8]\n");
mpp_err("invalid lambda idx i not in range [0, 8]\n");
ret = MPP_ERR_VALUE;
}
@@ -879,7 +898,7 @@ MPP_RET mpp_enc_proc_tune_cfg(MppEncFineTuneCfg *dst, MppEncFineTuneCfg *src)
dst->lambda_idx_p = src->lambda_idx_p;
if (dst->lambda_idx_p < 0 || dst->lambda_idx_p > 8) {
mpp_err("invalid lambda idx i not in range [0 : 8]\n");
mpp_err("invalid lambda idx i not in range [0, 8]\n");
ret = MPP_ERR_VALUE;
}
@@ -1152,6 +1171,7 @@ static const char *name_of_rc_mode[] = {
"cbr",
"fixqp",
"avbr",
"smtrc"
};
static void update_rc_cfg_log(MppEncImpl *impl, const char* fmt, ...)
@@ -1237,6 +1257,9 @@ static void set_rc_cfg(RcCfg *cfg, MppEncCfgSet *cfg_set)
case MPP_ENC_RC_MODE_FIXQP: {
cfg->mode = RC_FIXQP;
} break;
case MPP_ENC_RC_MODE_SMTRC: {
cfg->mode = RC_SMT;
} break;
default : {
cfg->mode = RC_AVBR;
} break;
@@ -2253,6 +2276,7 @@ static MPP_RET set_enc_info_to_packet(MppEncImpl *enc, HalEncTask *hal_task)
/* frame type */
mpp_meta_set_s32(meta, KEY_OUTPUT_INTRA, frm->is_intra);
mpp_meta_set_s32(meta, KEY_OUTPUT_PSKIP, frm->force_pskip || is_pskip);
mpp_meta_set_s32(meta, KEY_ENC_BPS_RT, rc_task->info.rt_bits);
if (rc_task->info.frame_type == INTER_VI_FRAME)
mpp_meta_set_s32(meta, KEY_ENC_USE_LTR, rc_task->cpb.refr.lt_idx);

4
mpp/codec/mpp_rc.cpp
View File

@@ -155,7 +155,7 @@ void mpp_pid_set_param(MppPIDCtx *ctx, RK_S32 coef_p, RK_S32 coef_i, RK_S32 coef
ctx, coef_p, coef_i, coef_d, div, len);
}
void mpp_pid_update(MppPIDCtx *ctx, RK_S32 val)
void mpp_pid_update(MppPIDCtx *ctx, RK_S32 val, RK_S32 is_reset)
{
mpp_rc_dbg_rc("RC: pid ctx %p update val %d\n", ctx, val);
mpp_rc_dbg_rc("RC: pid ctx %p before update P %d I %d D %d\n", ctx, ctx->p, ctx->i, ctx->d);
@@ -169,7 +169,7 @@ void mpp_pid_update(MppPIDCtx *ctx, RK_S32 val)
/*
* pid control is a short time control, it needs periodically reset
*/
if (ctx->count >= ctx->len)
if (is_reset && ctx->count >= ctx->len)
mpp_pid_reset(ctx);
}

1
mpp/codec/rc/rc_model_v2.c
View File

@@ -1705,6 +1705,7 @@ MPP_RET rc_model_v2_end(void *ctx, EncRcTask *task)
if (usr_cfg->mode == RC_FIXQP)
goto DONE;
cfg->rt_bits = p->ins_bps;
p->last_inst_bps = p->ins_bps;
p->first_frm_flg = 0;

1704
mpp/codec/rc/rc_model_v2_smt.c
View File

File diff suppressed because it is too large Load Diff

55
mpp/hal/rkenc/common/vepu510_common.h
View File

@@ -823,33 +823,33 @@ typedef struct Vepu510RcRoi_t {
/* 0x00001054 reg1045 */
struct {
RK_U32 aq_stp_s0 : 5;
RK_U32 aq_stp_0t1 : 5;
RK_U32 aq_stp_1t2 : 5;
RK_U32 aq_stp_2t3 : 5;
RK_U32 aq_stp_3t4 : 5;
RK_U32 aq_stp_4t5 : 5;
RK_U32 reserved : 2;
RK_S32 aq_stp_s0 : 5;
RK_S32 aq_stp_0t1 : 5;
RK_S32 aq_stp_1t2 : 5;
RK_S32 aq_stp_2t3 : 5;
RK_S32 aq_stp_3t4 : 5;
RK_S32 aq_stp_4t5 : 5;
RK_S32 reserved : 2;
} aq_stp0;
/* 0x00001058 reg1046 */
struct {
RK_U32 aq_stp_5t6 : 5;
RK_U32 aq_stp_6t7 : 5;
RK_U32 aq_stp_7t8 : 5;
RK_U32 aq_stp_8t9 : 5;
RK_U32 aq_stp_9t10 : 5;
RK_U32 aq_stp_10t11 : 5;
RK_U32 reserved : 2;
RK_S32 aq_stp_5t6 : 5;
RK_S32 aq_stp_6t7 : 5;
RK_S32 aq_stp_7t8 : 5;
RK_S32 aq_stp_8t9 : 5;
RK_S32 aq_stp_9t10 : 5;
RK_S32 aq_stp_10t11 : 5;
RK_S32 reserved : 2;
} aq_stp1;
/* 0x0000105c reg1047 */
struct {
RK_U32 aq_stp_11t12 : 5;
RK_U32 aq_stp_12t13 : 5;
RK_U32 aq_stp_13t14 : 5;
RK_U32 aq_stp_14t15 : 5;
RK_U32 aq_stp_b15 : 5;
RK_S32 aq_stp_11t12 : 5;
RK_S32 aq_stp_12t13 : 5;
RK_S32 aq_stp_13t14 : 5;
RK_S32 aq_stp_14t15 : 5;
RK_S32 aq_stp_b15 : 5;
RK_U32 reserved : 7;
} aq_stp2;
@@ -2174,6 +2174,23 @@ typedef struct Vepu510Dbg_t {
RK_U32 jpeg_fcyc;
} Vepu510Dbg;
/* ROI block configuration */
typedef struct Vepu510H264RoiBlkCfg {
RK_U32 qp_adju : 8;
RK_U32 mdc_adju_inter : 4;
RK_U32 mdc_adju_skip : 4;
RK_U32 mdc_adju_intra : 4;
RK_U32 reserved : 12;
} Vepu510H264RoiBlkCfg;
typedef struct Vepu510H265RoiBlkCfg {
RK_U32 qp_adju : 8;
RK_U32 reserved : 12;
RK_U32 mdc_adju_inter : 4;
RK_U32 mdc_adju_skip : 4;
RK_U32 mdc_adju_intra : 4;
} Vepu510H265RoiBlkCfg;
#ifdef __cplusplus
extern "C" {
#endif

19
mpp/hal/rkenc/h264e/hal_h264e_vepu510.c
View File

@@ -402,7 +402,7 @@ static void setup_hal_bufs(HalH264eVepu510Ctx *ctx)
(ctx->pixel_buf_size != pixel_buf_size) ||
(ctx->thumb_buf_size != thumb_buf_size) ||
(new_max_cnt > old_max_cnt)) {
size_t sizes[2];
size_t sizes[3];
hal_h264e_dbg_detail("frame size %d -> %d max count %d -> %d\n",
ctx->pixel_buf_size, pixel_buf_size,
@@ -412,9 +412,11 @@ static void setup_hal_bufs(HalH264eVepu510Ctx *ctx)
sizes[0] = pixel_buf_size;
/* thumb buffer */
sizes[1] = thumb_buf_size;
/* smear buffer */
sizes[2] = MPP_ALIGN(aligned_w / 64, 16) * MPP_ALIGN(aligned_h / 16, 16);
new_max_cnt = MPP_MAX(new_max_cnt, old_max_cnt);
hal_bufs_setup(ctx->hw_recn, new_max_cnt, 2, sizes);
hal_bufs_setup(ctx->hw_recn, new_max_cnt, MPP_ARRAY_ELEMS(sizes), sizes);
ctx->pixel_buf_fbc_hdr_size = pixel_buf_fbc_hdr_size;
ctx->pixel_buf_fbc_bdy_size = pixel_buf_fbc_bdy_size;
@@ -1261,12 +1263,17 @@ static void setup_vepu510_rc_base(HalVepu510RegSet *regs, HalH264eVepu510Ctx *ct
reg_frm->common.rc_cfg.aq_en = 1;
reg_frm->common.rc_cfg.rc_ctu_num = mb_w;
reg_frm->common.rc_qp.rc_qp_range = (slice->slice_type == H264_I_SLICE) ?
hw->qp_delta_row_i : hw->qp_delta_row;
reg_frm->common.rc_qp.rc_max_qp = qp_max;
reg_frm->common.rc_qp.rc_min_qp = qp_min;
reg_frm->common.rc_tgt.ctu_ebit = mb_target_bits_mul_16;
if (rc->rc_mode == MPP_ENC_RC_MODE_SMTRC) {
reg_frm->common.rc_qp.rc_qp_range = 0;
} else {
reg_frm->common.rc_qp.rc_qp_range = (slice->slice_type == H264_I_SLICE) ?
hw->qp_delta_row_i : hw->qp_delta_row;
}
{
/* fixed frame level QP */
RK_S32 fqp_min, fqp_max;
@@ -1544,6 +1551,7 @@ static void setup_vepu510_recn_refr(HalH264eVepu510Ctx *ctx, HalVepu510RegSet *r
if (curr && curr->cnt) {
MppBuffer buf_pixel = curr->buf[0];
MppBuffer buf_thumb = curr->buf[1];
MppBuffer buf_smear = curr->buf[2];
RK_S32 fd = mpp_buffer_get_fd(buf_pixel);
mpp_assert(buf_pixel);
@@ -1552,11 +1560,13 @@ static void setup_vepu510_recn_refr(HalH264eVepu510Ctx *ctx, HalVepu510RegSet *r
reg_frm->common.rfpw_h_addr = fd;
reg_frm->common.rfpw_b_addr = fd;
reg_frm->common.dspw_addr = mpp_buffer_get_fd(buf_thumb);
reg_frm->common.adr_smear_wr = mpp_buffer_get_fd(buf_smear);
}
if (refr && refr->cnt) {
MppBuffer buf_pixel = refr->buf[0];
MppBuffer buf_thumb = refr->buf[1];
MppBuffer buf_smear = curr->buf[2];
RK_S32 fd = mpp_buffer_get_fd(buf_pixel);
mpp_assert(buf_pixel);
@@ -1565,6 +1575,7 @@ static void setup_vepu510_recn_refr(HalH264eVepu510Ctx *ctx, HalVepu510RegSet *r
reg_frm->common.rfpr_h_addr = fd;
reg_frm->common.rfpr_b_addr = fd;
reg_frm->common.dspr_addr = mpp_buffer_get_fd(buf_thumb);
reg_frm->common.adr_smear_rd = mpp_buffer_get_fd(buf_smear);
}
mpp_dev_multi_offset_update(ctx->offsets, 164, fbc_hdr_size);
mpp_dev_multi_offset_update(ctx->offsets, 166, fbc_hdr_size);

566
mpp/hal/rkenc/h265e/hal_h265e_vepu510.c
View File

@@ -84,10 +84,10 @@ typedef struct Vepu510H265eFrmCfg_t {
Vepu541OsdCfg osd_cfg;
void *roi_data;
/* gdr roi cfg */
MppBuffer roi_base_cfg_buf;
/* roi buffer for qpmap or gdr */
MppBuffer roir_buf;
RK_S32 roir_buf_size;
void *roi_base_cfg_sw_buf;
RK_S32 roi_base_buf_size;
/* variable length cfg */
MppDevRegOffCfgs *reg_cfg;
@@ -110,7 +110,7 @@ typedef struct H265eV510HalContext_t {
MppCbCtx *output_cb;
/* @frame_cnt starts from ZERO */
RK_U32 frame_count;
RK_S32 frame_count;
/* frame parallel info */
RK_S32 task_cnt;
@@ -128,8 +128,7 @@ typedef struct H265eV510HalContext_t {
RK_S32 frame_type;
RK_S32 last_frame_type;
/* @frame_cnt starts from ZERO */
RK_U32 frame_cnt;
MppBufferGroup roi_grp;
void *roi_data;
MppEncCfgSet *cfg;
MppDevRegOffCfgs *reg_cfg;
@@ -164,19 +163,27 @@ typedef struct H265eV510HalContext_t {
#include "hal_h265e_vepu510_tune.c"
static RK_U32 aq_thd_default[16] = {
0, 0, 0, 0,
3, 3, 5, 5,
8, 8, 8, 15,
15, 20, 25, 25
};
static RK_S32 atf_b32_skip_thd2[4] = {15, 15, 15, 200};
static RK_S32 atf_b32_skip_thd3[4] = {72, 72, 72, 1000};
static RK_S32 atf_b32_skip_wgt0[4] = {16, 20, 20, 16};
static RK_S32 atf_b32_skip_wgt3[4] = {16, 16, 16, 17};
static RK_S32 atf_b16_skip_thd2[4] = {15, 15, 15, 200};
static RK_S32 atf_b16_skip_thd3[4] = {25, 25, 25, 1000};
static RK_S32 atf_b16_skip_wgt0[4] = {16, 20, 20, 16};
static RK_S32 atf_b16_skip_wgt3[4] = {16, 16, 16, 17};
static RK_S32 atf_b32_intra_thd0[4] = {20, 20, 20, 24};
static RK_S32 atf_b32_intra_thd1[4] = {40, 40, 40, 48};
static RK_S32 atf_b32_intra_thd2[4] = {60, 72, 72, 96};
static RK_S32 atf_b32_intra_wgt0[4] = {16, 22, 27, 28};
static RK_S32 atf_b32_intra_wgt1[4] = {16, 20, 25, 26};
static RK_S32 atf_b32_intra_wgt2[4] = {16, 18, 20, 24};
static RK_S32 atf_b16_intra_thd0[4] = {20, 20, 20, 24};
static RK_S32 atf_b16_intra_thd1[4] = {40, 40, 40, 48};
static RK_S32 atf_b16_intra_thd2[4] = {60, 72, 72, 96};
static RK_S32 atf_b16_intra_wgt0[4] = {16, 22, 27, 28};
static RK_S32 atf_b16_intra_wgt1[4] = {16, 20, 25, 26};
static RK_S32 atf_b16_intra_wgt2[4] = {16, 18, 20, 24};
static RK_S32 aq_qp_dealt_default[16] = {
-8, -7, -6, -5,
-4, -3, -2, -1,
0, 1, 2, 3,
4, 5, 6, 8,
};
static RK_U32 rdo_lambda_table_I[60] = {
0x00000012, 0x00000017,
@@ -321,7 +328,9 @@ static MPP_RET vepu510_h265_setup_hal_bufs(H265eV510HalContext *ctx)
}
if (frame_size > ctx->frame_size || new_max_cnt > old_max_cnt) {
size_t size[3] = {0};
size_t size[4] = {0};
RK_S32 ctu_w = (prep->width + 31) / 32;
RK_S32 ctu_h = (prep->height + 31) / 32;
hal_bufs_deinit(ctx->dpb_bufs);
hal_bufs_init(&ctx->dpb_bufs);
@@ -330,12 +339,14 @@ static MPP_RET vepu510_h265_setup_hal_bufs(H265eV510HalContext *ctx)
size[0] = ctx->fbc_header_len + ((mb_wd64 * mb_h64) << 12) * 3 / 2; //fbc_h + fbc_b
size[1] = (mb_wd64 * mb_h64 << 8);
size[2] = MPP_ALIGN(mb_wd64 * mb_h64 * 16 * 4, 256) * 16;
/* smear bufs */
size[3] = MPP_ALIGN(ctu_w, 16) * MPP_ALIGN(ctu_h, 16);
new_max_cnt = MPP_MAX(new_max_cnt, old_max_cnt);
hal_h265e_dbg_detail("frame size %d -> %d max count %d -> %d\n",
ctx->frame_size, frame_size, old_max_cnt, new_max_cnt);
hal_bufs_setup(ctx->dpb_bufs, new_max_cnt, 3, size);
hal_bufs_setup(ctx->dpb_bufs, new_max_cnt, MPP_ARRAY_ELEMS(size), size);
ctx->frame_size = frame_size;
ctx->max_buf_cnt = new_max_cnt;
@@ -344,13 +355,220 @@ static MPP_RET vepu510_h265_setup_hal_bufs(H265eV510HalContext *ctx)
return ret;
}
static void vepu510_h265_rdo_cfg(H265eVepu510Sqi *reg, MppEncSceneMode sm)
static void vepu510_h265_set_atr_regs(H265eVepu510Sqi *reg_sqi, MppEncSceneMode sm, int atr_level)
{
rdo_skip_par *p_rdo_skip = NULL;
rdo_noskip_par *p_rdo_noskip = NULL;
pre_cst_par *p_pre_cst = NULL;
// atr_level 0~3
// 0 close
// 1 weak
// 2 medium
// 3 strong
H265eVepu510Sqi *reg = reg_sqi;
(void)sm;
if (atr_level == 0) {
reg->block_opt_cfg.block_en = 0;
reg->cmplx_opt_cfg.cmplx_en = 0;
reg->line_opt_cfg.line_en = 0;
} else {
reg->block_opt_cfg.block_en = 0;
reg->cmplx_opt_cfg.cmplx_en = 0;
reg->line_opt_cfg.line_en = 1;
}
reg->subj_opt_cfg.subj_opt_en = (sm == MPP_ENC_SCENE_MODE_IPC);
if (atr_level == 3) {
reg->block_opt_cfg.block_thre_cst_best_mad = 1000;
reg->block_opt_cfg.block_thre_cst_best_grdn_blk = 39;
reg->block_opt_cfg.thre_num_grdnt_point_cmplx = 3;
reg->block_opt_cfg.block_delta_qp_flag = 3;
reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep0 = 4000;
reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep1 = 2000;
reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_mad_dep2 = 200;
reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_grdn_blk_dep0 = 977;
reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep1 = 0;
reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep2 = 488;
reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep0 = 4;
reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep1 = 30;//20
reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep2 = 30;//20
reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep0 = 7;//7
reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep1 = 6;//8
reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep0 = 1;
reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep1 = 50;
reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep2 = 50;
reg->subj_opt_dqp0.line_thre_qp = 20;
reg->subj_opt_dqp0.block_strength = 4;
reg->subj_opt_dqp0.block_thre_qp = 30;
reg->subj_opt_dqp0.cmplx_strength = 4;
reg->subj_opt_dqp0.cmplx_thre_qp = 34;
reg->subj_opt_dqp0.cmplx_thre_max_grdn_blk = 32;
} else if (atr_level == 2) {
reg->block_opt_cfg.block_thre_cst_best_mad = 1000;
reg->block_opt_cfg.block_thre_cst_best_grdn_blk = 39;
reg->block_opt_cfg.thre_num_grdnt_point_cmplx = 3;
reg->block_opt_cfg.block_delta_qp_flag = 3;
reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep0 = 4000;
reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep1 = 2000;
reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_mad_dep2 = 200;
reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_grdn_blk_dep0 = 977;
reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep1 = 0;
reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep2 = 488;
reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep0 = 3;
reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep1 = 20;
reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep2 = 20;
reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep0 = 7;
reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep1 = 8;
reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep0 = 1;
reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep1 = 60;
reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep2 = 60;
reg->subj_opt_dqp0.line_thre_qp = 25;
reg->subj_opt_dqp0.block_strength = 4;
reg->subj_opt_dqp0.block_thre_qp = 30;
reg->subj_opt_dqp0.cmplx_strength = 4;
reg->subj_opt_dqp0.cmplx_thre_qp = 34;
reg->subj_opt_dqp0.cmplx_thre_max_grdn_blk = 32;
} else {
reg->block_opt_cfg.block_thre_cst_best_mad = 1000;
reg->block_opt_cfg.block_thre_cst_best_grdn_blk = 39;
reg->block_opt_cfg.thre_num_grdnt_point_cmplx = 3;
reg->block_opt_cfg.block_delta_qp_flag = 3;
reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep0 = 6000;
reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep1 = 2000;
reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_mad_dep2 = 300;
reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_grdn_blk_dep0 = 1280;
reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep1 = 0;
reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep2 = 512;
reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep0 = 3;
reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep1 = 20;
reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep2 = 20;
reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep0 = 7;
reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep1 = 8;
reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep0 = 1;
reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep1 = 70;
reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep2 = 70;
reg->subj_opt_dqp0.line_thre_qp = 30;
reg->subj_opt_dqp0.block_strength = 4;
reg->subj_opt_dqp0.block_thre_qp = 30;
reg->subj_opt_dqp0.cmplx_strength = 4;
reg->subj_opt_dqp0.cmplx_thre_qp = 34;
reg->subj_opt_dqp0.cmplx_thre_max_grdn_blk = 32;
}
}
static void vepu510_h265_set_anti_blur_regs(H265eVepu510Sqi *reg_sqi, int anti_blur_en)
{
H265eVepu510Sqi *reg = reg_sqi;
reg->subj_anti_blur_thd.anti_blur_en = anti_blur_en;
reg->subj_anti_blur_thd.blur_low_madi_thd = 5;
reg->subj_anti_blur_thd.blur_high_madi_thd = 27;
reg->subj_anti_blur_thd.blur_low_cnt_thd = 0;
reg->subj_anti_blur_thd.blur_hight_cnt_thd = 0;
reg->subj_anti_blur_thd.blur_sum_cnt_thd = 5;
reg->subj_anti_blur_sao.blur_motion_thd = 32;
reg->subj_anti_blur_sao.sao_ofst_thd_eo_luma = 2;
reg->subj_anti_blur_sao.sao_ofst_thd_bo_luma = 4;
reg->subj_anti_blur_sao.sao_ofst_thd_eo_chroma = 2;
reg->subj_anti_blur_sao.sao_ofst_thd_bo_chroma = 4;
}
static void vepu510_h265_set_anti_stripe_regs(H265eVepu510Sqi *reg_sqi)
{
pre_cst_par* pre_i32 = (pre_cst_par*)&reg_sqi->preintra32_cst;
pre_cst_par* pre_i16 = (pre_cst_par*)&reg_sqi->preintra16_cst;
pre_i32->cst_madi_thd0.madi_thd0 = 5;
pre_i32->cst_madi_thd0.madi_thd1 = 15;
pre_i32->cst_madi_thd0.madi_thd2 = 5;
pre_i32->cst_madi_thd0.madi_thd3 = 3;
pre_i32->cst_madi_thd1.madi_thd4 = 3;
pre_i32->cst_madi_thd1.madi_thd5 = 6;
pre_i32->cst_madi_thd1.madi_thd6 = 7;
pre_i32->cst_madi_thd1.madi_thd7 = 5;
pre_i32->cst_madi_thd2.madi_thd8 = 10;
pre_i32->cst_madi_thd2.madi_thd9 = 5;
pre_i32->cst_madi_thd2.madi_thd10 = 7;
pre_i32->cst_madi_thd2.madi_thd11 = 5;
pre_i32->cst_madi_thd3.madi_thd12 = 7;
pre_i32->cst_madi_thd3.madi_thd13 = 5;
pre_i32->cst_madi_thd3.mode_th = 5;
pre_i32->cst_wgt0.wgt0 = 20;
pre_i32->cst_wgt0.wgt1 = 18;
pre_i32->cst_wgt0.wgt2 = 19;
pre_i32->cst_wgt0.wgt3 = 18;
pre_i32->cst_wgt1.wgt4 = 12;
pre_i32->cst_wgt1.wgt5 = 6;
pre_i32->cst_wgt1.wgt6 = 13;
pre_i32->cst_wgt1.wgt7 = 9;
pre_i32->cst_wgt2.wgt8 = 12;
pre_i32->cst_wgt2.wgt9 = 6;
pre_i32->cst_wgt2.wgt10 = 13;
pre_i32->cst_wgt2.wgt11 = 9;
pre_i32->cst_wgt3.wgt12 = 18;
pre_i32->cst_wgt3.wgt13 = 17;
pre_i32->cst_wgt3.wgt14 = 17;
pre_i16->cst_madi_thd0.madi_thd0 = 5;
pre_i16->cst_madi_thd0.madi_thd1 = 15;
pre_i16->cst_madi_thd0.madi_thd2 = 5;
pre_i16->cst_madi_thd0.madi_thd3 = 3;
pre_i16->cst_madi_thd1.madi_thd4 = 3;
pre_i16->cst_madi_thd1.madi_thd5 = 6;
pre_i16->cst_madi_thd1.madi_thd6 = 7;
pre_i16->cst_madi_thd1.madi_thd7 = 5;
pre_i16->cst_madi_thd2.madi_thd8 = 10;
pre_i16->cst_madi_thd2.madi_thd9 = 5;
pre_i16->cst_madi_thd2.madi_thd10 = 7;
pre_i16->cst_madi_thd2.madi_thd11 = 5;
pre_i16->cst_madi_thd3.madi_thd12 = 7;
pre_i16->cst_madi_thd3.madi_thd13 = 5;
pre_i16->cst_madi_thd3.mode_th = 5;
pre_i16->cst_wgt0.wgt0 = 20;
pre_i16->cst_wgt0.wgt1 = 18;
pre_i16->cst_wgt0.wgt2 = 19;
pre_i16->cst_wgt0.wgt3 = 18;
pre_i16->cst_wgt1.wgt4 = 12;
pre_i16->cst_wgt1.wgt5 = 6;
pre_i16->cst_wgt1.wgt6 = 13;
pre_i16->cst_wgt1.wgt7 = 9;
pre_i16->cst_wgt2.wgt8 = 12;
pre_i16->cst_wgt2.wgt9 = 6;
pre_i16->cst_wgt2.wgt10 = 13;
pre_i16->cst_wgt2.wgt11 = 9;
pre_i16->cst_wgt3.wgt12 = 18;
pre_i16->cst_wgt3.wgt13 = 17;
pre_i16->cst_wgt3.wgt14 = 17;
pre_i32->cst_madi_thd3.qp_thd = 28;
pre_i32->cst_wgt3.lambda_mv_bit_0 = 5; // lv32
pre_i32->cst_wgt3.lambda_mv_bit_1 = 4; // lv16
pre_i16->cst_wgt3.lambda_mv_bit_0 = 4; // lv8
pre_i16->cst_wgt3.lambda_mv_bit_1 = 3; // lv4
pre_i32->cst_wgt3.anti_strp_e = 1;
}
static void vepu510_h265_rdo_cfg(H265eV510HalContext *ctx, H265eVepu510Sqi *reg, MppEncSceneMode sm)
{
reg->subj_opt_cfg.subj_opt_en = 1;//(sm == MPP_ENC_SCENE_MODE_IPC);
reg->subj_opt_cfg.subj_opt_strength = 3;
reg->subj_opt_cfg.aq_subj_en = (sm == MPP_ENC_SCENE_MODE_IPC);
reg->subj_opt_cfg.aq_subj_strength = 4;
@@ -433,167 +651,9 @@ static void vepu510_h265_rdo_cfg(H265eVepu510Sqi *reg, MppEncSceneMode sm)
reg->subj_opt_dqp1.skin_thre_qp = 31;
/* text_opt */
reg->block_opt_cfg.block_en = (sm == MPP_ENC_SCENE_MODE_IPC);
reg->block_opt_cfg.block_thre_cst_best_mad = 1000;
reg->block_opt_cfg.block_thre_cst_best_grdn_blk = 39;
reg->block_opt_cfg.thre_num_grdnt_point_cmplx = 3;
reg->block_opt_cfg.block_delta_qp_flag = 3;
reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep0 = 4000;
reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep1 = 2000;
reg->cmplx_opt_cfg.cmplx_en = (sm == MPP_ENC_SCENE_MODE_IPC);
reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_mad_dep2 = 200;
reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_grdn_blk_dep0 = 977;
reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep1 = 0;
reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep2 = 488;
reg->line_opt_cfg.line_en = (sm == MPP_ENC_SCENE_MODE_IPC);
reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep0 = 3;
reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep1 = 20;
reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep2 = 20;
reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep0 = 8;
reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep1 = 8;
reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep0 = 1;
reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep1 = 78;
reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep2 = 78;
reg->subj_opt_dqp0.line_thre_qp = 34;
reg->subj_opt_dqp0.block_strength = 4;
reg->subj_opt_dqp0.block_thre_qp = 30;
reg->subj_opt_dqp0.cmplx_strength = 4;
reg->subj_opt_dqp0.cmplx_thre_qp = 34;
reg->subj_opt_dqp0.cmplx_thre_max_grdn_blk = 32;
reg->subj_opt_dqp1.bndry_rdo_cu_intra_r_coef_dep0 = 240;
reg->subj_opt_dqp1.bndry_rdo_cu_intra_r_coef_dep1 = 224;
p_rdo_skip = &reg->rdo_b32_skip;
p_rdo_skip->atf_thd0.madp_thd0 = 5 ;
p_rdo_skip->atf_thd0.madp_thd1 = 10 ;
p_rdo_skip->atf_thd1.madp_thd2 = 15 ;
p_rdo_skip->atf_thd1.madp_thd3 = 72 ;
p_rdo_skip->atf_wgt0.wgt0 = 20 ;
p_rdo_skip->atf_wgt0.wgt1 = 16 ;
p_rdo_skip->atf_wgt0.wgt2 = 16 ;
p_rdo_skip->atf_wgt0.wgt3 = 16 ;
p_rdo_noskip = &reg->rdo_b32_inter;
p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
p_rdo_noskip->atf_wgt.wgt0 = 16;
p_rdo_noskip->atf_wgt.wgt1 = 16;
p_rdo_noskip->atf_wgt.wgt2 = 16;
p_rdo_noskip = &reg->rdo_b32_intra;
p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
p_rdo_noskip->atf_wgt.wgt0 = 27;
p_rdo_noskip->atf_wgt.wgt1 = 25;
p_rdo_noskip->atf_wgt.wgt2 = 20;
p_rdo_skip = &reg->rdo_b16_skip;
p_rdo_skip->atf_thd0.madp_thd0 = 1 ;
p_rdo_skip->atf_thd0.madp_thd1 = 10 ;
p_rdo_skip->atf_thd1.madp_thd2 = 15 ;
p_rdo_skip->atf_thd1.madp_thd3 = 25 ;
p_rdo_skip->atf_wgt0.wgt0 = 20 ;
p_rdo_skip->atf_wgt0.wgt1 = 16 ;
p_rdo_skip->atf_wgt0.wgt2 = 16 ;
p_rdo_skip->atf_wgt0.wgt3 = 16 ;
p_rdo_skip->atf_wgt1.wgt4 = 16 ;
p_rdo_noskip = &reg->rdo_b16_inter;
p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
p_rdo_noskip->atf_wgt.wgt0 = 16;
p_rdo_noskip->atf_wgt.wgt1 = 16;
p_rdo_noskip->atf_wgt.wgt2 = 16;
p_rdo_noskip->atf_wgt.wgt3 = 16;
p_rdo_noskip = &reg->rdo_b16_intra;
p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
p_rdo_noskip->atf_wgt.wgt0 = 27;
p_rdo_noskip->atf_wgt.wgt1 = 25;
p_rdo_noskip->atf_wgt.wgt2 = 20;
p_rdo_noskip->atf_wgt.wgt3 = 16;
p_pre_cst = &reg->preintra32_cst;
p_pre_cst->cst_madi_thd0.madi_thd0 = 5;
p_pre_cst->cst_madi_thd0.madi_thd1 = 15;
p_pre_cst->cst_madi_thd0.madi_thd2 = 5;
p_pre_cst->cst_madi_thd0.madi_thd3 = 3;
p_pre_cst->cst_madi_thd1.madi_thd4 = 3;
p_pre_cst->cst_madi_thd1.madi_thd5 = 6;
p_pre_cst->cst_madi_thd1.madi_thd6 = 7;
p_pre_cst->cst_madi_thd1.madi_thd7 = 5;
p_pre_cst->cst_madi_thd2.madi_thd8 = 10;
p_pre_cst->cst_madi_thd2.madi_thd9 = 5;
p_pre_cst->cst_madi_thd2.madi_thd10 = 7;
p_pre_cst->cst_madi_thd2.madi_thd11 = 5;
p_pre_cst->cst_madi_thd3.madi_thd12 = 10;
p_pre_cst->cst_madi_thd3.madi_thd13 = 5;
p_pre_cst->cst_wgt0.wgt0 = 20;
p_pre_cst->cst_wgt0.wgt1 = 18;
p_pre_cst->cst_wgt0.wgt2 = 19;
p_pre_cst->cst_wgt0.wgt3 = 18;
p_pre_cst->cst_wgt1.wgt4 = 12;
p_pre_cst->cst_wgt1.wgt5 = 6;
p_pre_cst->cst_wgt1.wgt6 = 13;
p_pre_cst->cst_wgt1.wgt7 = 9;
p_pre_cst->cst_wgt2.wgt8 = 12;
p_pre_cst->cst_wgt2.wgt9 = 6;
p_pre_cst->cst_wgt2.wgt10 = 13;
p_pre_cst->cst_wgt2.wgt11 = 9;
p_pre_cst->cst_wgt3.wgt12 = 18;
p_pre_cst->cst_wgt3.wgt13 = 17;
p_pre_cst->cst_wgt3.wgt14 = 17;
p_pre_cst->cst_wgt3.lambda_mv_bit_0 = 5;
p_pre_cst->cst_wgt3.lambda_mv_bit_1 = 4;
p_pre_cst->cst_wgt3.anti_strp_e = 0;
p_pre_cst->cst_madi_thd3.mode_th = 5;
p_pre_cst->cst_madi_thd3.qp_thd = 28;
p_pre_cst = &reg->preintra16_cst;
p_pre_cst->cst_madi_thd0.madi_thd0 = 5;
p_pre_cst->cst_madi_thd0.madi_thd1 = 15;
p_pre_cst->cst_madi_thd0.madi_thd2 = 5;
p_pre_cst->cst_madi_thd0.madi_thd3 = 3;
p_pre_cst->cst_madi_thd1.madi_thd4 = 3;
p_pre_cst->cst_madi_thd1.madi_thd5 = 6;
p_pre_cst->cst_madi_thd1.madi_thd6 = 5;
p_pre_cst->cst_madi_thd1.madi_thd7 = 5;
p_pre_cst->cst_madi_thd2.madi_thd8 = 7;
p_pre_cst->cst_madi_thd2.madi_thd9 = 5;
p_pre_cst->cst_madi_thd2.madi_thd10 = 5;
p_pre_cst->cst_madi_thd2.madi_thd11 = 5;
p_pre_cst->cst_madi_thd3.madi_thd12 = 7;
p_pre_cst->cst_madi_thd3.madi_thd13 = 5;
p_pre_cst->cst_wgt0.wgt0 = 20;
p_pre_cst->cst_wgt0.wgt1 = 18;
p_pre_cst->cst_wgt0.wgt2 = 19;
p_pre_cst->cst_wgt0.wgt3 = 18;
p_pre_cst->cst_wgt1.wgt4 = 12;
p_pre_cst->cst_wgt1.wgt5 = 6;
p_pre_cst->cst_wgt1.wgt6 = 13;
p_pre_cst->cst_wgt1.wgt7 = 9;
p_pre_cst->cst_wgt2.wgt8 = 12;
p_pre_cst->cst_wgt2.wgt9 = 6;
p_pre_cst->cst_wgt2.wgt10 = 13;
p_pre_cst->cst_wgt2.wgt11 = 9;
p_pre_cst->cst_wgt3.wgt12 = 18;
p_pre_cst->cst_wgt3.wgt13 = 17;
p_pre_cst->cst_wgt3.wgt14 = 17;
p_pre_cst->cst_wgt3.lambda_mv_bit_0 = 4;
p_pre_cst->cst_wgt3.lambda_mv_bit_1 = 3;
p_pre_cst->cst_madi_thd3.mode_th = 5;
/* 0x00002100 reg2112 */
reg->cudecis_thd0.base_thre_rough_mad32_intra = 9;
reg->cudecis_thd0.delta0_thre_rough_mad32_intra = 10;
@@ -705,37 +765,99 @@ static void vepu510_h265_rdo_cfg(H265eVepu510Sqi *reg, MppEncSceneMode sm)
reg->cudecis_thd11.delta5_thre_mad_fme_ratio_inter = 4;
reg->cudecis_thd11.delta6_thre_mad_fme_ratio_inter = 4;
reg->cudecis_thd11.delta7_thre_mad_fme_ratio_inter = 4;
vepu510_h265_set_anti_stripe_regs(reg);
if (ctx->frame_type == INTRA_FRAME)
vepu510_h265_set_atr_regs(reg, sm, 3);
else
vepu510_h265_set_atr_regs(reg, sm, 0);
if (ctx->frame_type == INTRA_FRAME)
vepu510_h265_set_anti_blur_regs(reg, 0);
else
vepu510_h265_set_anti_blur_regs(reg, 1);
}
static void vepu510_h265_atf_cfg(H265eVepu510Sqi *reg, RK_S32 atf_str)
{
rdo_skip_par *p_rdo_skip = NULL;
rdo_noskip_par *p_rdo_noskip = NULL;
p_rdo_skip = &reg->rdo_b32_skip;
p_rdo_skip->atf_thd0.madp_thd0 = 5 ;
p_rdo_skip->atf_thd0.madp_thd1 = 10 ;
p_rdo_skip->atf_thd1.madp_thd2 = atf_b32_skip_thd2[atf_str];
p_rdo_skip->atf_thd1.madp_thd3 = atf_b32_skip_thd3[atf_str];
p_rdo_skip->atf_wgt0.wgt0 = atf_b32_skip_wgt0[atf_str];
p_rdo_skip->atf_wgt0.wgt1 = 16 ;
p_rdo_skip->atf_wgt0.wgt2 = 16 ;
p_rdo_skip->atf_wgt0.wgt3 = atf_b32_skip_wgt3[atf_str];
p_rdo_noskip = &reg->rdo_b32_inter;
p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
p_rdo_noskip->atf_wgt.wgt0 = 16;
p_rdo_noskip->atf_wgt.wgt1 = 16;
p_rdo_noskip->atf_wgt.wgt2 = 16;
p_rdo_noskip = &reg->rdo_b32_intra;
p_rdo_noskip->ratf_thd0.madp_thd0 = atf_b32_intra_thd0[atf_str];
p_rdo_noskip->ratf_thd0.madp_thd1 = atf_b32_intra_thd1[atf_str];
p_rdo_noskip->ratf_thd1.madp_thd2 = atf_b32_intra_thd2[atf_str];
p_rdo_noskip->atf_wgt.wgt0 = atf_b32_intra_wgt0[atf_str];
p_rdo_noskip->atf_wgt.wgt1 = atf_b32_intra_wgt1[atf_str];
p_rdo_noskip->atf_wgt.wgt2 = atf_b32_intra_wgt2[atf_str];
p_rdo_skip = &reg->rdo_b16_skip;
p_rdo_skip->atf_thd0.madp_thd0 = 1 ;
p_rdo_skip->atf_thd0.madp_thd1 = 10 ;
p_rdo_skip->atf_thd1.madp_thd2 = atf_b16_skip_thd2[atf_str];
p_rdo_skip->atf_thd1.madp_thd3 = atf_b16_skip_thd3[atf_str];
p_rdo_skip->atf_wgt0.wgt0 = atf_b16_skip_wgt0[atf_str];
p_rdo_skip->atf_wgt0.wgt1 = 16 ;
p_rdo_skip->atf_wgt0.wgt2 = 16 ;
p_rdo_skip->atf_wgt0.wgt3 = atf_b16_skip_wgt3[atf_str];
p_rdo_skip->atf_wgt1.wgt4 = 16 ;
p_rdo_noskip = &reg->rdo_b16_inter;
p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
p_rdo_noskip->atf_wgt.wgt0 = 16;
p_rdo_noskip->atf_wgt.wgt1 = 16;
p_rdo_noskip->atf_wgt.wgt2 = 16;
p_rdo_noskip->atf_wgt.wgt3 = 16;
p_rdo_noskip = &reg->rdo_b16_intra;
p_rdo_noskip->ratf_thd0.madp_thd0 = atf_b16_intra_thd0[atf_str];
p_rdo_noskip->ratf_thd0.madp_thd1 = atf_b16_intra_thd1[atf_str];
p_rdo_noskip->ratf_thd1.madp_thd2 = atf_b16_intra_thd2[atf_str];
p_rdo_noskip->atf_wgt.wgt0 = atf_b16_intra_wgt0[atf_str];
p_rdo_noskip->atf_wgt.wgt1 = atf_b16_intra_wgt1[atf_str];
p_rdo_noskip->atf_wgt.wgt2 = atf_b16_intra_wgt2[atf_str];
p_rdo_noskip->atf_wgt.wgt3 = 16;
}
static void vepu510_h265_global_cfg_set(H265eV510HalContext *ctx, H265eV510RegSet *regs)
{
MppEncHwCfg *hw = &ctx->cfg->hw;
RK_U32 i;
Vepu510RcRoi *rc_regs = &regs->reg_rc_roi;
H265eVepu510Param *reg_param = &regs->reg_param;
H265eVepu510Sqi *reg_sqi = &regs->reg_sqi;
MppEncSceneMode sm = ctx->cfg->tune.scene_mode;
RK_S32 atf_str = ctx->cfg->tune.anti_flicker_str;
RK_S32 lambda_idx = 0;
vepu510_h265_rdo_cfg(reg_sqi, sm);
vepu510_h265_rdo_cfg(ctx, reg_sqi, sm);
vepu510_h265_atf_cfg(reg_sqi, atf_str);
memcpy(&reg_param->pprd_lamb_satd_0_51[0], lamd_satd_qp_510, sizeof(lamd_satd_qp));
if (ctx->frame_type == INTRA_FRAME) {
RK_U8 *thd = (RK_U8 *)&rc_regs->aq_tthd0;
for (i = 0; i < MPP_ARRAY_ELEMS(aq_thd_default); i++) {
thd[i] = hw->aq_thrd_i[i];
}
reg_param->iprd_lamb_satd_ofst.lambda_satd_offset = 11;
lambda_idx = ctx->cfg->tune.lambda_idx_i;
memcpy(&reg_param->rdo_wgta_qp_grpa_0_51[0],
&rdo_lambda_table_I[lambda_idx], H265E_LAMBDA_TAB_SIZE);
} else {
RK_U8 *thd = (RK_U8 *)&rc_regs->aq_tthd0;
for (i = 0; i < MPP_ARRAY_ELEMS(aq_thd_default); i++) {
thd[i] = hw->aq_thrd_p[i];
}
reg_param->iprd_lamb_satd_ofst.lambda_satd_offset = 11;
lambda_idx = ctx->cfg->tune.lambda_idx_p;
memcpy(&reg_param->rdo_wgta_qp_grpa_0_51[0],
@@ -747,6 +869,8 @@ static void vepu510_h265_global_cfg_set(H265eV510HalContext *ctx, H265eV510RegSe
if (hw->qbias_en) {
reg_param->qnt_bias_comb.qnt_f_bias_i = hw->qbias_i;
reg_param->qnt_bias_comb.qnt_f_bias_p = hw->qbias_p;
} else if (ctx->smart_en) {
reg_param->qnt_bias_comb.qnt_f_bias_i = 144;
}
/* CIME */
@@ -831,10 +955,10 @@ MPP_RET hal_h265e_v510_deinit(void *hal)
if (!frm)
continue;
if (frm->roi_base_cfg_buf) {
mpp_buffer_put(frm->roi_base_cfg_buf);
frm->roi_base_cfg_buf = NULL;
frm->roi_base_buf_size = 0;
if (frm->roir_buf) {
mpp_buffer_put(frm->roir_buf);
frm->roir_buf = NULL;
frm->roir_buf_size = 0;
}
MPP_FREE(frm->roi_base_cfg_sw_buf);
@@ -871,6 +995,11 @@ MPP_RET hal_h265e_v510_deinit(void *hal)
ctx->reg_cfg = NULL;
}
if (ctx->roi_grp) {
mpp_buffer_group_put(ctx->roi_grp);
ctx->roi_grp = NULL;
}
if (ctx->tune) {
vepu510_h265e_tune_deinit(ctx->tune);
ctx->tune = NULL;
@@ -907,7 +1036,7 @@ MPP_RET hal_h265e_v510_init(void *hal, MppEncHalCfg *cfg)
ctx->cfg = cfg->cfg;
hal_bufs_init(&ctx->dpb_bufs);
ctx->frame_cnt = 0;
ctx->frame_count = -1;
ctx->frame_cnt_gen_ready = 0;
ctx->enc_mode = 1;
cfg->cap_recn_out = 1;
@@ -931,11 +1060,6 @@ MPP_RET hal_h265e_v510_init(void *hal, MppEncHalCfg *cfg)
hw->qbias_p = 85;
hw->qbias_en = 0;
memcpy(hw->aq_thrd_i, aq_thd_default, sizeof(hw->aq_thrd_i));
memcpy(hw->aq_thrd_p, aq_thd_default, sizeof(hw->aq_thrd_p));
memcpy(hw->aq_step_i, aq_qp_dealt_default, sizeof(hw->aq_step_i));
memcpy(hw->aq_step_p, aq_qp_dealt_default, sizeof(hw->aq_step_p));
for (j = 0; j < MPP_ARRAY_ELEMS(hw->mode_bias); j++)
hw->mode_bias[j] = 8;
}
@@ -1114,12 +1238,18 @@ static MPP_RET vepu510_h265_set_rc_regs(H265eV510HalContext *ctx, H265eV510RegSe
reg_frm->common.rc_cfg.rc_en = 1;
reg_frm->common.rc_cfg.aq_en = 1;
reg_frm->common.rc_cfg.rc_ctu_num = mb_wd32;
reg_frm->common.rc_qp.rc_qp_range = (ctx->frame_type == INTRA_FRAME) ?
hw->qp_delta_row_i : hw->qp_delta_row;
reg_frm->common.rc_qp.rc_max_qp = rc_cfg->quality_max;
reg_frm->common.rc_qp.rc_min_qp = rc_cfg->quality_min;
reg_frm->common.rc_tgt.ctu_ebit = ctu_target_bits_mul_16;
if (ctx->smart_en) {
reg_frm->common.rc_qp.rc_qp_range = 0;
} else {
reg_frm->common.rc_qp.rc_qp_range = (ctx->frame_type == INTRA_FRAME) ?
hw->qp_delta_row_i : hw->qp_delta_row;
}
{
/* fixed frame qp */
RK_S32 fqp_min, fqp_max;
@@ -1430,10 +1560,10 @@ void vepu510_h265_set_hw_address(H265eV510HalContext *ctx, H265eVepu510Frame *re
mpp_dev_multi_offset_update(ctx->reg_cfg, 166, ctx->fbc_header_len);
if (md_info_buf) {
regs->common.enc_pic.mei_stor = 1;
regs->common.enc_pic.mei_stor = 1;
regs->common.meiw_addr = mpp_buffer_get_fd(md_info_buf);
} else {
regs->common.enc_pic.mei_stor = 0;
regs->common.enc_pic.mei_stor = 0;
regs->common.meiw_addr = 0;
}
@@ -1453,6 +1583,10 @@ void vepu510_h265_set_hw_address(H265eV510HalContext *ctx, H265eVepu510Frame *re
regs->common.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
regs->common.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
/* smear bufs */
regs->common.adr_smear_rd = mpp_buffer_get_fd(ref_buf->buf[3]);
regs->common.adr_smear_wr = mpp_buffer_get_fd(recon_buf->buf[3]);
}
static MPP_RET vepu510_h265e_save_pass1_patch(H265eV510RegSet *regs, H265eV510HalContext *ctx,
@@ -1676,8 +1810,8 @@ MPP_RET hal_h265e_v510_gen_regs(void *hal, HalEncTask *task)
pic_h32 = (syn->pp.pic_height + 31) / 32;
hal_h265e_dbg_simple("frame %d | type %d | start gen regs",
ctx->frame_cnt, ctx->frame_type);
ctx->frame_count, ctx->frame_type);
vepu510_h265e_tune_aq_prepare(ctx->tune);
memset(regs, 0, sizeof(H265eV510RegSet));
reg_ctl->enc_strt.lkt_num = 0;
@@ -1748,7 +1882,7 @@ MPP_RET hal_h265e_v510_gen_regs(void *hal, HalEncTask *task)
reg_frm->rdo_cfg.cu_inter_e = 0xdb;
reg_frm->rdo_cfg.lambda_qp_use_avg_cu16_flag = (sm == MPP_ENC_SCENE_MODE_IPC);
reg_frm->rdo_cfg.yuvskip_calc_en = 1;
reg_frm->rdo_cfg.atf_e = (sm == MPP_ENC_SCENE_MODE_IPC);
reg_frm->rdo_cfg.atf_e = 1;
reg_frm->rdo_cfg.atr_e = (sm == MPP_ENC_SCENE_MODE_IPC);
if (syn->pp.num_long_term_ref_pics_sps) {
@@ -1793,7 +1927,7 @@ MPP_RET hal_h265e_v510_gen_regs(void *hal, HalEncTask *task)
ctx->cfg->prep.width, ctx->cfg->prep.height);
/*paramet cfg*/
vepu510_h265_global_cfg_set(ctx, regs);
vepu510_h265e_tune_reg_patch(ctx->tune);
vepu510_h265e_tune_reg_patch(ctx->tune, task);
/* two pass register patch */
if (frm->save_pass1)
@@ -2211,6 +2345,8 @@ MPP_RET hal_h265e_v510_get_task(void *hal, HalEncTask *task)
ctx->syn = (H265eSyntax_new *)task->syntax.data;
ctx->dpb = (H265eDpb*)ctx->syn->dpb;
ctx->smart_en = (ctx->cfg->rc.rc_mode == MPP_ENC_RC_MODE_SMTRC);
ctx->qpmap_en = ctx->cfg->tune.deblur_en;
if (vepu510_h265_setup_hal_bufs(ctx)) {
hal_h265e_err("vepu541_h265_allocate_buffers failed, free buffers and return\n");
@@ -2219,7 +2355,6 @@ MPP_RET hal_h265e_v510_get_task(void *hal, HalEncTask *task)
}
ctx->last_frame_type = ctx->frame_type;
frm_cfg = ctx->frms[task_idx];
ctx->frm = frm_cfg;
@@ -2228,6 +2363,7 @@ MPP_RET hal_h265e_v510_get_task(void *hal, HalEncTask *task)
} else {
ctx->frame_type = INTER_P_FRAME;
}
if (!frm_status->reencode && mpp_frame_has_meta(task->frame)) {
MppMeta meta = mpp_frame_get_meta(frame);

118
mpp/hal/rkenc/h265e/hal_h265e_vepu510_tune.c
View File

@@ -18,15 +18,48 @@
#include "hal_h265e_vepu510_reg.h"
typedef struct HalH265eVepu510Tune_t {
H265eV510HalContext *ctx;
H265eV510HalContext *ctx;
RK_S32 pre_madp[2];
RK_S32 pre_madi[2];
RK_U8 *qm_mv_buf; /* qpmap move flag buffer */
RK_U32 qm_mv_buf_size;
RK_S32 pre_madp[2];
RK_S32 pre_madi[2];
} HalH265eVepu510Tune;
static RK_U32 aq_thd_default[16] = {
0, 0, 0, 0, 3, 3, 5, 5,
8, 8, 8, 15, 15, 20, 25, 25
};
static RK_S32 aq_qp_delta_default[16] = {
-8, -7, -6, -5, -4, -3, -2, -1,
1, 2, 3, 4, 5, 6, 7, 8
};
static RK_U32 aq_thd_smt_I[16] = {
1, 2, 3, 3, 3, 3, 5, 5,
8, 8, 8, 13, 15, 20, 25, 25
};
static RK_S32 aq_qp_delta_smt_I[16] = {
-8, -7, -6, -5, -4, -3, -2, -1,
0, 1, 2, 3, 5, 7, 8, 9
};
static RK_U32 aq_thd_smt_P[16] = {
0, 0, 0, 0, 3, 3, 5, 5,
8, 8, 8, 15, 15, 20, 25, 25
};
static RK_S32 aq_qp_delta_smt_P[16] = {
-8, -7, -6, -5, -4, -3, -2, -1,
0, 1, 2, 3, 4, 6, 7, 9
};
static HalH265eVepu510Tune *vepu510_h265e_tune_init(H265eV510HalContext *ctx)
{
HalH265eVepu510Tune *tune = mpp_malloc(HalH265eVepu510Tune, 1);
HalH265eVepu510Tune *tune = mpp_calloc(HalH265eVepu510Tune, 1);
if (NULL == tune)
return tune;
@@ -40,33 +73,72 @@ static HalH265eVepu510Tune *vepu510_h265e_tune_init(H265eV510HalContext *ctx)
static void vepu510_h265e_tune_deinit(void *tune)
{
HalH265eVepu510Tune *t = (HalH265eVepu510Tune *)tune;
MPP_FREE(t->qm_mv_buf);
MPP_FREE(tune);
}
static void vepu510_h265e_tune_aq_prepare(HalH265eVepu510Tune *tune)
{
if (tune == NULL) {
return;
}
H265eV510HalContext *ctx = tune->ctx;
MppEncHwCfg *hw = &ctx->cfg->hw;
if (ctx->smart_en) {
memcpy(hw->aq_thrd_i, aq_thd_smt_I, sizeof(hw->aq_thrd_i));
memcpy(hw->aq_thrd_p, aq_thd_smt_P, sizeof(hw->aq_thrd_p));
memcpy(hw->aq_step_i, aq_qp_delta_smt_I, sizeof(hw->aq_step_i));
memcpy(hw->aq_step_p, aq_qp_delta_smt_P, sizeof(hw->aq_step_p));
} else {
memcpy(hw->aq_thrd_i, aq_thd_default, sizeof(hw->aq_thrd_i));
memcpy(hw->aq_thrd_p, aq_thd_default, sizeof(hw->aq_thrd_p));
memcpy(hw->aq_step_i, aq_qp_delta_default, sizeof(hw->aq_step_i));
memcpy(hw->aq_step_p, aq_qp_delta_default, sizeof(hw->aq_step_p));
}
}
static void vepu510_h265e_tune_aq(HalH265eVepu510Tune *tune)
{
H265eV510HalContext *ctx = tune->ctx;
Vepu510H265eFrmCfg *frm_cfg = ctx->frm;
H265eV510RegSet *regs = frm_cfg->regs_set;
Vepu510RcRoi *r = &regs->reg_rc_roi;
MppEncHwCfg *hw = &ctx->cfg->hw;
RK_U32 i = 0;
RK_S32 aq_step[16];
r->aq_stp0.aq_stp_s0 = -8;
r->aq_stp0.aq_stp_0t1 = -7;
r->aq_stp0.aq_stp_1t2 = -6;
r->aq_stp0.aq_stp_2t3 = -5;
r->aq_stp0.aq_stp_3t4 = -4;
r->aq_stp0.aq_stp_4t5 = -3;
r->aq_stp1.aq_stp_5t6 = -2;
r->aq_stp1.aq_stp_6t7 = -1;
RK_U8 *thd = (RK_U8 *)&r->aq_tthd0;
for (i = 0; i < MPP_ARRAY_ELEMS(aq_thd_default); i++) {
if (ctx->frame_type == INTRA_FRAME) {
thd[i] = hw->aq_thrd_i[i];
aq_step[i] = hw->aq_step_i[i] & 0x1F;
} else {
thd[i] = hw->aq_thrd_p[i];
aq_step[i] = hw->aq_step_p[i] & 0x1F;
}
}
r->aq_stp0.aq_stp_s0 = aq_step[0];
r->aq_stp0.aq_stp_0t1 = aq_step[1];
r->aq_stp0.aq_stp_1t2 = aq_step[2];
r->aq_stp0.aq_stp_2t3 = aq_step[3];
r->aq_stp0.aq_stp_3t4 = aq_step[4];
r->aq_stp0.aq_stp_4t5 = aq_step[5];
r->aq_stp1.aq_stp_5t6 = aq_step[6];
r->aq_stp1.aq_stp_6t7 = aq_step[7];
r->aq_stp1.aq_stp_7t8 = 0;
r->aq_stp1.aq_stp_8t9 = 1;
r->aq_stp1.aq_stp_9t10 = 2;
r->aq_stp1.aq_stp_10t11 = 3;
r->aq_stp2.aq_stp_11t12 = 4;
r->aq_stp2.aq_stp_12t13 = 5;
r->aq_stp2.aq_stp_13t14 = 6;
r->aq_stp2.aq_stp_14t15 = 7;
r->aq_stp2.aq_stp_b15 = 8;
r->aq_stp1.aq_stp_8t9 = aq_step[8];
r->aq_stp1.aq_stp_9t10 = aq_step[9];
r->aq_stp1.aq_stp_10t11 = aq_step[10];
r->aq_stp2.aq_stp_11t12 = aq_step[11];
r->aq_stp2.aq_stp_12t13 = aq_step[12];
r->aq_stp2.aq_stp_13t14 = aq_step[13];
r->aq_stp2.aq_stp_14t15 = aq_step[14];
r->aq_stp2.aq_stp_b15 = aq_step[15];
r->aq_clip.aq16_rnge = 5;
r->aq_clip.aq32_rnge = 5;
@@ -75,13 +147,9 @@ static void vepu510_h265e_tune_aq(HalH265eVepu510Tune *tune)
r->aq_clip.aq16_dif1 = 12;
}
static void vepu510_h265e_tune_reg_patch(void *p)
static void vepu510_h265e_tune_reg_patch(void *p, HalEncTask *task)
{
HalH265eVepu510Tune *tune = (HalH265eVepu510Tune *)p;
H265eV510HalContext *ctx = NULL;
RK_S32 scene_mode = 0;
(void)ctx;
(void)scene_mode;
if (NULL == tune)
return;

29
test/mpi_enc_test.c
View File

@@ -119,6 +119,7 @@ typedef struct {
RK_S32 vi_len;
RK_S32 scene_mode;
RK_S32 cu_qp_delta_depth;
RK_S32 anti_flicker_str;
RK_S64 first_frm;
RK_S64 first_pkt;
@@ -180,6 +181,7 @@ MPP_RET test_ctx_init(MpiEncMultiCtxInfo *info)
p->fps_out_num = cmd->fps_out_num;
p->scene_mode = cmd->scene_mode;
p->cu_qp_delta_depth = cmd->cu_qp_delta_depth;
p->anti_flicker_str = cmd->anti_flicker_str;
p->mdinfo_size = (MPP_VIDEO_CodingHEVC == cmd->type) ?
(MPP_ALIGN(p->hor_stride, 32) >> 5) *
(MPP_ALIGN(p->ver_stride, 32) >> 5) * 16 :
@@ -318,8 +320,11 @@ MPP_RET test_mpp_enc_cfg_setup(MpiEncMultiCtxInfo *info)
p->bps = p->width * p->height / 8 * (p->fps_out_num / p->fps_out_den);
mpp_enc_cfg_set_s32(cfg, "rc:cu_qp_delta_depth", p->cu_qp_delta_depth);
mpp_enc_cfg_set_s32(cfg, "tune:anti_flicker_str", p->anti_flicker_str);
mpp_enc_cfg_set_s32(cfg, "tune:scene_mode", p->scene_mode);
mpp_enc_cfg_set_s32(cfg, "tune:deblur_en", cmd->deblur_en);
mpp_enc_cfg_set_s32(cfg, "tune:deblur_str", cmd->deblur_str);
mpp_enc_cfg_set_s32(cfg, "prep:width", p->width);
mpp_enc_cfg_set_s32(cfg, "prep:height", p->height);
@@ -387,7 +392,8 @@ MPP_RET test_mpp_enc_cfg_setup(MpiEncMultiCtxInfo *info)
} break;
case MPP_ENC_RC_MODE_CBR :
case MPP_ENC_RC_MODE_VBR :
case MPP_ENC_RC_MODE_AVBR : {
case MPP_ENC_RC_MODE_AVBR :
case MPP_ENC_RC_MODE_SMTRC : {
mpp_enc_cfg_set_s32(cfg, "rc:qp_init", cmd->qp_init ? cmd->qp_init : -1);
mpp_enc_cfg_set_s32(cfg, "rc:qp_max", cmd->qp_max ? cmd->qp_max : 51);
mpp_enc_cfg_set_s32(cfg, "rc:qp_min", cmd->qp_min ? cmd->qp_min : 10);
@@ -508,6 +514,19 @@ MPP_RET test_mpp_enc_cfg_setup(MpiEncMultiCtxInfo *info)
goto RET;
}
if (cmd->type == MPP_VIDEO_CodingAVC || cmd->type == MPP_VIDEO_CodingHEVC) {
RcApiBrief rc_api_brief;
rc_api_brief.type = cmd->type;
rc_api_brief.name = (cmd->rc_mode == MPP_ENC_RC_MODE_SMTRC) ?
"smart" : "default";
ret = mpi->control(ctx, MPP_ENC_SET_RC_API_CURRENT, &rc_api_brief);
if (ret) {
mpp_err("mpi control enc set rc api failed ret %d\n", ret);
goto RET;
}
}
if (ref)
mpp_enc_ref_cfg_deinit(&ref);
@@ -607,7 +626,7 @@ MPP_RET test_mpp_run(MpiEncMultiCtxInfo *info)
if (ret == MPP_NOK || feof(p->fp_input)) {
p->frm_eos = 1;
if (p->frame_num < 0 || p->frame_count < p->frame_num) {
if (p->frame_num < 0) {
clearerr(p->fp_input);
rewind(p->fp_input);
p->frm_eos = 0;
@@ -818,7 +837,7 @@ MPP_RET test_mpp_run(MpiEncMultiCtxInfo *info)
meta = mpp_packet_get_meta(packet);
RK_S32 temporal_id = 0;
RK_S32 lt_idx = -1;
RK_S32 avg_qp = -1;
RK_S32 avg_qp = -1, bps_rt = -1;
RK_S32 use_lt_idx = -1;
if (MPP_OK == mpp_meta_get_s32(meta, KEY_TEMPORAL_ID, &temporal_id))
@@ -833,6 +852,10 @@ MPP_RET test_mpp_run(MpiEncMultiCtxInfo *info)
log_len += snprintf(log_buf + log_len, log_size - log_len,
" qp %2d", avg_qp);
if (MPP_OK == mpp_meta_get_s32(meta, KEY_ENC_BPS_RT, &bps_rt))
log_len += snprintf(log_buf + log_len, log_size - log_len,
" bps_rt %d", bps_rt);
if (MPP_OK == mpp_meta_get_s32(meta, KEY_ENC_USE_LTR, &use_lt_idx))
log_len += snprintf(log_buf + log_len, log_size - log_len, " vi");
}

44
utils/mpi_enc_utils.c
View File

@@ -292,7 +292,7 @@ RK_S32 mpi_enc_opt_rc(void *ctx, const char *next)
}
mpp_err("invalid rate control usage -rc rc_mode\n");
mpp_err("rc_mode 0:vbr 1:cbr 2:avbr 3:cvbr 4:fixqp\n");
mpp_err("rc_mode 0:vbr 1:cbr 2:fixqp 3:avbr 4:smtrc\n");
return 0;
}
@@ -501,6 +501,32 @@ RK_S32 mpi_enc_opt_qpdd(void *ctx, const char *next)
return 0;
}
RK_S32 mpi_enc_opt_dbe(void *ctx, const char *next)
{
MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx;
if (next) {
cmd->deblur_en = atoi(next);
return 1;
}
mpp_err("invalid deblur en\n");
return 0;
}
RK_S32 mpi_enc_opt_dbs(void *ctx, const char *next)
{
MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx;
if (next) {
cmd->deblur_str = atoi(next);
return 1;
}
mpp_err("invalid deblur str\n");
return 0;
}
RK_S32 mpi_enc_opt_help(void *ctx, const char *next)
{
(void)ctx;
@@ -508,6 +534,19 @@ RK_S32 mpi_enc_opt_help(void *ctx, const char *next)
return -1;
}
RK_S32 mpi_enc_opt_atf(void *ctx, const char *next)
{
MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx;
if (next) {
cmd->anti_flicker_str = atoi(next);
return 1;
}
mpp_err("invalid cu_qp_delta_depth\n");
return 0;
}
static MppOptInfo enc_opts[] = {
{"i", "input_file", "input frame file", mpi_enc_opt_i},
{"o", "output_file", "output encoded bitstream file", mpi_enc_opt_o},
@@ -532,6 +571,9 @@ static MppOptInfo enc_opts[] = {
{"slt", "slt file", "slt verify data file", mpi_enc_opt_slt},
{"sm", "scene mode", "scene_mode, 0:default 1:ipc", mpi_enc_opt_sm},
{"qpdd", "cu_qp_delta_depth", "cu_qp_delta_depth, 0:1:2", mpi_enc_opt_qpdd},
{"dbe", "deblur enable", "deblur_en or qpmap_en, 0:close 1:open", mpi_enc_opt_dbe},
{"dbs", "deblur strength", "deblur_str 0~3: hw + sw scheme; 4~7: hw scheme", mpi_enc_opt_dbs},
{"atf", "anti_flicker_str", "anti_flicker_str, 0:off 1 2 3", mpi_enc_opt_atf},
};
static RK_U32 enc_opt_cnt = MPP_ARRAY_ELEMS(enc_opts);

7
utils/mpi_enc_utils.h
View File

@@ -79,6 +79,13 @@ typedef struct MpiEncTestArgs_t {
/* -qpdd cu_qp_delta_depth */
RK_S32 cu_qp_delta_depth;
RK_S32 anti_flicker_str;
/* -dbe deblur enable flag
* -dbs deblur strength
*/
RK_S32 deblur_en;
RK_S32 deblur_str;
/* -v q runtime log disable flag */
RK_U32 quiet;